KR100302620B1 - Method for forming bit line of semiconductor device - Google Patents
Method for forming bit line of semiconductor device Download PDFInfo
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- KR100302620B1 KR100302620B1 KR1019990041121A KR19990041121A KR100302620B1 KR 100302620 B1 KR100302620 B1 KR 100302620B1 KR 1019990041121 A KR1019990041121 A KR 1019990041121A KR 19990041121 A KR19990041121 A KR 19990041121A KR 100302620 B1 KR100302620 B1 KR 100302620B1
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- Prior art keywords
- bit line
- forming
- oxide film
- etch
- film
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 150000004767 nitrides Chemical class 0.000 claims abstract description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 17
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 239000010410 layer Substances 0.000 claims abstract description 12
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 11
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000011229 interlayer Substances 0.000 claims abstract description 8
- 238000000206 photolithography Methods 0.000 claims abstract description 8
- 239000007772 electrode material Substances 0.000 claims abstract description 4
- 230000004888 barrier function Effects 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 2
- 230000002265 prevention Effects 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 description 3
- 229910008814 WSi2 Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
본 발명은 반도체소자의 비트라인 형성방법에 관한 것으로, 종래에는 비트라인 콘택홀과 비트라인을 정의하기 위한 사진식각이 별도로 진행됨에 따라 공정제어가 어렵고, 오정렬로 인해 공정불량이 유발될 수 있는 문제점이 있었다. 따라서, 본 발명은 소자가 형성된 반도체기판 상에 순차적으로 층간절연용 산화막 및 질화막을 형성한 다음 사진식각을 통해 비트라인이 형성될 영역의 질화막을 식각하고, 계속해서 산화막을 소정의 깊이로 식각하는 공정과; 상기 결과물 상에 전극물질로 제1폴리실리콘과 실리사이드층을 순차적으로 형성한 다음 질화막을 식각차단막으로 적용하여 에치-백을 실시함으로써, 상기 소정의 깊이로 식각된 산화막의 측면에 실리사이드 측벽을 형성함과 아울러 그 측벽이 형성되지 않은 영역의 산화막을 선택적으로 노출시키는 공정과; 상기 질화막 및 실리사이드 측벽을 마스크로 적용하여 노출된 산화막을 반도체기판이 노출될때까지 식각함으로써, 비트라인 콘택홀을 형성하는 공정과; 상기 결과물 상에 제2폴리실리콘을 형성한 다음 평탄화하여 비트라인을 형성하는 공정으로 이루어지는 반도체소자의 비트라인 형성방법을 통해 비트라인 콘택 및 비트라인을 1회의 마스크 사용으로 정의함으로써, 공정 단순화 및 오정렬 방지에 기여할 수 있으며, 또한 비트라인과 비트바라인이 층간절연용 산화막에 매립 형성되므로, 평탄화에 따른 후속공정의 적용이 용이한 효과가 있다.The present invention relates to a method for forming a bit line of a semiconductor device, and in the related art, process of the process is difficult due to the photolithography for defining the bit line contact hole and the bit line, and the process defect may be caused by misalignment. There was this. Accordingly, the present invention sequentially forms an interlayer insulating oxide film and a nitride film on a semiconductor substrate on which an element is formed, and then etches the nitride film of the region where the bit line is to be formed through photolithography, and subsequently etches the oxide film to a predetermined depth. Process; Forming a first polysilicon and a silicide layer as an electrode material on the resultant, and then etch-back by applying a nitride film as an etch barrier, thereby forming a silicide sidewall on the side of the oxide film etched to a predetermined depth And selectively exposing an oxide film in a region where the sidewall is not formed; Applying the nitride film and the silicide sidewall as a mask to etch the exposed oxide film until the semiconductor substrate is exposed, thereby forming a bit line contact hole; By forming the second polysilicon on the resultant and then flattening to form the bitline, the bitline contact and the bitline are defined by one mask using a method of forming a bitline, thereby simplifying and misaligning the process. It can contribute to the prevention, and also because the bit line and the bit bar line is buried in the interlayer insulating film, it is easy to apply the subsequent process according to the planarization.
Description
본 발명은 반도체소자의 비트라인 형성방법에 관한 것으로, 특히 메모리셀 트랜지스터의 비트라인 콘택(bit line contact) 및 비트라인을 1회의 마스크 사용으로 정의함으로써, 공정 단순화 및 오정렬(mis-align) 방지에 기여할 수 있는 반도체소자의 비트라인 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bit line of a semiconductor device, and in particular, defines a bit line contact and a bit line of a memory cell transistor by using a single mask, thereby simplifying the process and preventing mis-alignment. A method of forming a bit line of a semiconductor device that can contribute.
종래 반도체소자의 비트라인 형성방법을 첨부한 도1a 및 도1c의 수순단면도를 참조하여 상세히 설명하면 다음과 같다.A detailed description will now be made with reference to the procedure cross-sectional views of FIGS. 1A and 1C attached to a bit line forming method of a conventional semiconductor device.
먼저, 도1a에 도시한 바와같이 소자가 형성된 기판(1) 상에 층간절연용 산화막(2)을 증착한 다음 사진식각을 통해 소자의 특정영역이 선택적으로 노출되도록 산화막(2)의 일부를 식각하여 비트라인 콘택홀(3)을 형성한다.First, as shown in FIG. 1A, an oxide layer 2 for interlayer insulation is deposited on a substrate 1 on which an element is formed, and then a portion of the oxide layer 2 is etched to selectively expose a specific region of the element through photolithography. The bit line contact holes 3 are formed.
그리고, 도1b에 도시한 바와같이 상기 비트라인 콘택홀(3)이 형성된 결과물의 상부전면에 전극물질로 폴리실리콘(4)과 WSi2막(5)을 순차적으로 증착하여 비트라인 콘택홀(3)을 채운다. 이때, WSi2막(5)은 실리사이드층으로 비트라인의 저항값을 낯추기 위한 목적으로 적용된다.As shown in FIG. 1B, the polysilicon 4 and the WSi 2 film 5 are sequentially deposited on the upper surface of the resultant in which the bit line contact hole 3 is formed, thereby forming the bit line contact hole 3. ). At this time, the WSi 2 film 5 is applied to the silicide layer for the purpose of reducing the resistance of the bit line.
그리고, 도1c에 도시한 바와같이 상기 WSi2막(5) 상에 사진식각을 통해 감광막 패턴(미도시)을 형성한 다음 WSi2막(5), 폴리실리콘(4)을 식각하여 비트라인을 패터닝한다. 이때, 비트라인은 상기 비트라인 콘택홀(3)과 접속되는 폴리실리콘(4)과WSi2막(5)이 적층되어 패터닝되며, 비트바라인은 도면상에 도시된 바와같이 비트라인과 이격되어 폴리실리콘(4)과 WSi2막(5)이 적층되어 패터닝된다.Then, the bit line to the WSi 2 to form a film (not shown) photoresist pattern through a photolithography on the 5 following WSi 2 etching the film 5, a polysilicon 4, as shown in Figure 1c Pattern. At this time, the bit line is patterned by stacking the polysilicon 4 and the WSi 2 film 5 which are connected to the bit line contact hole 3, and the bit bar line is spaced apart from the bit line as shown in the drawing. Polysilicon 4 and WSi 2 film 5 are stacked and patterned.
그러나, 상기한 바와같은 종래 반도체소자의 비트라인 형성방법은 층간절연용 산화막 상에 비트라인 콘택홀을 정의하기 위한 사진식각과 WSi2막 상에 비트라인을 패터닝하기 위한 사진식각이 별도로 진행됨에 따라 공정제어가 어렵고, 아울러 오정렬로 인해 공정불량이 유발될 수 있는 문제점이 있었다.However, in the method of forming a bit line of the conventional semiconductor device as described above, as the photolithography for defining the bit line contact hole on the interlayer insulating oxide film and the photolithography for patterning the bit line on the WSi 2 film are performed separately, Process control is difficult, and also there is a problem that can cause a process defect due to misalignment.
본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 메모리셀 트랜지스터의 비트라인 콘택 및 비트라인을 1회의 마스크 사용으로 정의함으로써, 공정 단순화 및 오정렬 방지에 기여할 수 있는 반도체소자의 비트라인 형성방법을 제공하는데 있다.The present invention has been devised to solve the above-mentioned conventional problems, and an object of the present invention is to define the bit line contact and the bit line of a memory cell transistor by using a single mask, thereby contributing to process simplification and misalignment prevention. The present invention provides a method for forming a bit line of a semiconductor device.
도1a 내지 도1c는 종래 반도체소자의 비트라인 형성방법을 보인 수순단면도.1A to 1C are cross-sectional views showing a bit line forming method of a conventional semiconductor device.
도2a 내지 도2e는 본 발명의 일 실시예를 보인 수순단면도.Figures 2a to 2e is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
11:반도체기판 12:산화막11: semiconductor substrate 12: oxide film
13:질화막 14,17:폴리실리콘13: Nitride 14, 17: polysilicon
15:WSi2막 16:비트라인 콘택홀15: WSi2 film 16: bit line contact hole
상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 비트라인 형성방법은 소자가 형성된 반도체기판 상에 순차적으로 층간절연용 산화막 및 질화막을 형성한 다음 사진식각을 통해 비트라인이 형성될 영역의 질화막을 식각하고, 계속해서 산화막을 소정의 깊이로 식각하는 공정과; 상기 결과물 상에 전극물질로 제1폴리실리콘과 실리사이드층을 순차적으로 형성한 다음 질화막을 식각차단막으로 적용하여 에치-백(etch-back)을 실시함으로써, 상기 소정의 깊이로 식각된 산화막의 측면에 실리사이드 측벽을 형성함과 아울러 그 측벽이 형성되지 않은 영역의 산화막을 선택적으로 노출시키는 공정과; 상기 질화막 및 실리사이드 측벽을 마스크로 적용하여 노출된 산화막을 반도체기판이 노출될때까지 식각함으로써, 비트라인 콘택홀을 형성하는 공정과; 상기 결과물 상에 제2폴리실리콘을 형성한 다음 평탄화하여 비트라인을 형성하는 공정을 구비하여 이루어지는 것을 특징으로 한다.In the method of forming a bit line of a semiconductor device as described above, an oxide film and a nitride film for interlayer insulation are sequentially formed on a semiconductor substrate on which the device is formed. Etching the nitride film and subsequently etching the oxide film to a predetermined depth; The first polysilicon and the silicide layer are sequentially formed on the resultant as an electrode material, and then the nitride layer is applied as an etch barrier layer to perform etch-back to the side of the oxide layer etched to the predetermined depth. Forming a silicide sidewall and selectively exposing an oxide film in a region where the sidewall is not formed; Applying the nitride film and the silicide sidewall as a mask to etch the exposed oxide film until the semiconductor substrate is exposed, thereby forming a bit line contact hole; And forming a bit line by forming a second polysilicon on the resultant and then planarizing the second polysilicon.
상기한 바와같은 본 발명에 의한 반도체소자의 비트라인 형성방법을 도2a 내지 도2e의 수순단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.A method of forming a bit line of a semiconductor device according to the present invention as described above will be described in detail with reference to the procedure cross-sectional view of FIGS. 2A to 2E.
먼저, 도2a에 도시한 바와같이 소자가 형성된 반도체기판(11) 상에 순차적으로 층간절연용 산화막(12) 및 질화막(13)을 형성한 다음 사진식각을 통해 비트라인이 형성될 영역의 질화막(13)을 식각하고, 계속해서 산화막(12)을 소정의 깊이로 식각한다.First, as shown in FIG. 2A, the interlayer insulating oxide film 12 and the nitride film 13 are sequentially formed on the semiconductor substrate 11 on which the device is formed. Then, the nitride film of the region where the bit line is to be formed through photolithography ( 13) is etched, and then the oxide film 12 is etched to a predetermined depth.
그리고, 도2b에 도시한 바와같이 상기 결과물의 상부전면에 전극물질로 폴리실리콘(14)과 WSi2막(15)을 순차적으로 형성한다.As shown in FIG. 2B, polysilicon 14 and WSi 2 film 15 are sequentially formed of an electrode material on the upper surface of the resultant.
그리고, 도2c에 도시한 바와같이 상기 질화막(13)을 식각차단막으로 적용하여 WSi2막(15)과 폴리실리콘(14)을 이온반응성 식각법(reactive ion etch : RIE)을 통해 에치-백함으로써, 상기 소정의 깊이로 식각된 산화막(14)의 측면에 WSi2막(15)의 측벽을 형성함과 아울러 그 측벽이 형성되지 않은 영역의 산화막(14)을 선택적으로 노출시킨다.As shown in FIG. 2C, the nitride film 13 is applied as an etch stop layer to etch-back the WSi 2 film 15 and the polysilicon 14 through a reactive ion etch (RIE). The sidewall of the WSi 2 film 15 is formed on the side surface of the oxide film 14 etched to a predetermined depth, and the oxide film 14 in the region where the sidewall is not formed is selectively exposed.
그리고, 도2d에 도시한 바와같이 상기 질화막(13)과 WSi2막(15)의 측벽을 마스크로 적용하여 노출된 산화막(14)을 반도체기판(11)이 노출될때까지 식각함으로써, 비트라인 콘택홀(16)을 형성한다.As shown in FIG. 2D, the sidewalls of the nitride film 13 and the WSi 2 film 15 are applied as a mask to etch the exposed oxide film 14 until the semiconductor substrate 11 is exposed, thereby causing bit line contact. The hole 16 is formed.
그리고, 도2e에 도시한 바와같이 상기 비트라인 콘택홀(16)이 형성된 결과물의 상부전면에 폴리실리콘(17)을 증착한 다음 에치-백 또는 화학기계적 연마를 통해 평탄화하여 비트라인을 패터닝한다. 이때, 비트바라인은 비트라인과 이격되어 도2c의 공정진행시에 폴리실리콘(14)과 WSi2막(15)에 의해 매립되어 형성된다.As shown in FIG. 2E, polysilicon 17 is deposited on the upper surface of the resultant in which the bit line contact hole 16 is formed, and then planarized by etch-back or chemical mechanical polishing to pattern the bit line. In this case, the bit bar line is spaced apart from the bit line and is embedded by the polysilicon 14 and the WSi 2 film 15 during the process of FIG. 2C.
한편, 상기한 바와같은 본 발명의 일 실시예에서는 비트라인을 형성하는 것으로 한정하였지만, 이에 국한되지 않고 배선 형성 및 비아(VIA) 공정등에 확대 응용될 수 있다.Meanwhile, although one embodiment of the present invention as described above is limited to forming a bit line, the present invention is not limited thereto, and may be extended to wire forming and via (VIA) processes.
상기한 바와같은 본 발명에 의한 반도체소자의 비트라인 형성방법은 메모리셀 트랜지스터의 비트라인 콘택 및 비트라인을 1회의 마스크 사용으로 정의함으로써, 공정 단순화 및 오정렬 방지에 기여할 수 있으며, 또한 비트라인과 비트바라인이 층간절연용 산화막에 매립 형성되므로, 평탄화에 따른 후속공정의 적용이 용이한 효과가 있다.As described above, the method for forming a bit line of a semiconductor device according to the present invention can define the bit line contact and the bit line of a memory cell transistor by using a single mask, thereby contributing to the process simplification and preventing misalignment, and also the bit line and bit Since the barine is buried in the oxide film for interlayer insulation, it is easy to apply the subsequent process according to the planarization.
Claims (2)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990041121A KR100302620B1 (en) | 1999-09-22 | 1999-09-22 | Method for forming bit line of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990041121A KR100302620B1 (en) | 1999-09-22 | 1999-09-22 | Method for forming bit line of semiconductor device |
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| KR100302620B1 true KR100302620B1 (en) | 2001-11-02 |
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