KR100299913B1 - Hetero-junction bipolar transistor and method for fabricating the same - Google Patents

Abstract

PURPOSE: A hetero-junction bipolar transistor and a method for fabricating the same are provided to improve a speed of an reducing a parasitic capacitance between a base and the speed of a hetero-junction bipolar transistor. CONSTITUTION: A collector layer is formed on a semiconductor substrate. The collector layer is formed with upper material layers(36a,38a), lower material layers(30,32). and an intermediate material layer(34a). An insulating spacer(48) is formed on both sidewalls of the intermediate material layer(34a), the upper material layer(36a,38a), and the lower material layers(30,32). A collector electrode(52a) is formed on the lower material layers(30,32) of both sides of the upper material layers(36a,38a). A base layer(40a) is formed on the upper material layers(36a,38a). An emitter layer(42) is formed on the base layer(40a). An emitter layer(42) is contacted with the base layer(40a). A plurality of base electrodes(45,52b) are formed on the base layer(40a) of both sides of the emitter layer(42). A plurality of insulating spacers(46a,46b) is formed on both sidewalls of the emitter electrode(44) and both sidewall of the base electrodes(45,52b).

Description

Heterojunction bipolar transistor and method for manufacturing thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to heterojunction bipolar transistors (hereinafter referred to as 'HBT') and a method of manufacturing the same. More specifically, the present invention relates to a future communication device suitable for microwave applications. A heterojunction bipolar transistor.

AlGaAs / GaAs HBTs have advantages such as high speed, high power density, linearity, and low 1 / f noise.

For high speed HBT formation, it is required to reduce the capacitance between the base resistance and the base-collector.

1 is a cross-sectional view showing the structure of a conventional HBT, Figure 2 is a cross-sectional view showing the configuration of the HBT layer of FIG.

Referring to FIG. 1, a conventional base metal self-aligned HBT includes a first collector layer 2, a second collector layer 4, a base layer 6, an emitter layer 8, and a collector electrode ( 10), a base electrode 12, and an emitter electrode 14 are included.

The first and second collector layers 2, 4, the base layer 6, and the emitter layer 8 are sequentially stacked. The second collector layer 4 and the base layer 6 are formed to have a relatively narrower width than the first collector layer 2. The emitter layer 8 is formed to have a relatively narrower width than the base layer 6.

More specifically, in FIG. 2, the first collector layer 2 is an n + type GaAs material layer, the second collector layer 4 is an n− type GaAs material layer, and the base layer 6 is p + type GaAs material layer. The emitter layer 8 is, for example, a multilayer film in which an n-type AlGaAs material layer 8a, an n-type GaAs material layer 8b, and an n + type InGaAs material layer 8c are sequentially stacked.

The collector electrode 10 is formed to be electrically connected to the first collector layer 2 on the first collector layer 4 on both sides of the second collector layer 4. The base electrode 12 is formed on the base layer 6 on both sides of the emitter layer 8 so as to be electrically connected to the base layer 6. The emitter electrode 14 is formed on the emitter layer 8 so as to be electrically connected to the emitter layer 8. D1 represents the deflation width of the collector.

Problems of the HBT element as described above are as follows.

First, there is a problem in capacitance between the base and the collector. In the conventional HBT element, the HBT current is defined by the emitter layer 8 so that no current flows in the region of reference numeral 16 of the second collector layer 4. The region 16 serves as a base-collector junction region to form parasitic capacitance. This parasitic capacitance reduces the speed of the HBT.

As a method for reducing the parasitic capacitance, an isolation implantation method and a collector wet etching method have been introduced.

However, the isolation ion implantation method has a problem of increasing base sheet resistance since impurity ions pass through the base layer 6. The wet etching method has a problem in reproducibility of the process.

Second, there is a problem in collector etching. The conventional HBT device is formed by wet etching the second collector layer 4. That is, after masking the emitter and the base with a photoresist film, an etching process is performed using a wet solution such as H ₂ SO ₄ . This is because the overetch margin is considered to be sufficient as the thickness of the first collector layer 2 is about 6000 kPa. However, when the thickness of the second collector layer 4 is thick, the base layer 6 may be etched by wet etching, which is isotropic etching, thereby causing lifting of the base electrode 12. In addition, the etching of the second collector layer 4 should be stopped at the first collector layer 2, which results in non-uniformity in performing this process. Although it is believed that the overetch margin of the first collector layer 2 is sufficient, in practice, a doping peak is formed on top of the first collector layer 2 for technical reasons when forming the epitaxial layer. This doped peak layer is etched to cause a problem of increasing collector contact resistance.

Third, there is a problem in the metal resistance of the base electrode. The base electrode 12 is formed using the emitter electrode 14 as a self-aligned mask. At this time, the base electrode 12 and the emitter electrode 14 are prevented from being shorted by an undercut process of the region 16. However, the thickness of the base electrode 12 is not formed thicker than that of the emitter layer 8, and is formed to be thin with a thickness of about 2000 GPa or less. Therefore, the metal feeding resistance of the base electrode 12 is increased.

The present invention has been proposed to solve the above-mentioned problems, and can provide a parasitic capacitance between the base and the collector, and thus can improve the speed of the HBT device, and provide a reproducible heterojunction bipolar transistor and a method of manufacturing the same. Has its purpose.

Another object of the present invention is to provide a heterojunction bipolar transistor capable of forming the collector layer by self-aligned selective etching, and reducing the collector contact resistance and the base resistance, and a method of manufacturing the same.

1 is a cross-sectional view showing the structure of a conventional HBT.

2 is a cross-sectional view showing the configuration of the HBT layer of FIG.

3 is a cross-sectional view showing the structure of an HBT according to an embodiment of the present invention.

4 is a cross-sectional view showing the configuration of an HBT layer according to an embodiment of the present invention.

FIG. 5 is a stereoscopic view of part 55 of FIG.

6A through 6H are cross-sectional views sequentially illustrating a method of manufacturing HBT according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

2: n + type collector layer 4: n-type collector layer

6, 4Oa: base layer 8, 42: emitter layer

10, 52a: collector electrode 12: base electrode

14, 44: emitter electrodes D1, D2: collector deflation width

30: first collector layer 32: second collector layer

34a: third collector layer 36a: fourth collector layer

38a: Fifth collector layer 46a, 46b, 48: insulating spacer

[Configuration]

According to the present invention for achieving the above object, the manufacturing method of the HBT, the first high concentration first collector layer and the first low concentration second collector layer, the second low concentration third collector layer, the third low concentration agent on the semiconductor substrate A fourth collector layer, a fourth low concentration fifth collector layer, a base layer, an emitter layer, and an emitter electrode are sequentially formed, wherein the second and fourth collector layers comprise the third and fifth collector layers and the base layer. Forming a material having a different etching selectivity, wherein the emitter layer is formed by patterning a multilayer film including GaAs and AlGaAs; Forming a base electrode on the base layer on both sides of the emitter layer; Forming a first insulating spacer on both sidewalls of the emitter electrode and the base electrode, wherein the space between the emitter electrode and the base electrode is filled with the first insulating spacer; Etching and patterning the base layer and the fifth collector layer on each side of the base electrode by using the fourth collector layer as an etch stop layer; Removing fourth collector layers on both sides of the fifth collector layer; Dry etching the third collector layers on both sides of the fourth collector layer to have an under cut profile with respect to the fourth collector layer; Forming a second insulating spacer on an inner wall of the undercut portion, including both sides of the third collector layer; Forming a photoresist film pattern including the emitter electrode to mask a portion of the base electrodes on both sides of the emitter electrode; Forming a collector electrode layer on the entire surface of the semiconductor substrate using the photoresist film pattern as a mask, wherein the collector electrode is self-aligned on the second collector layer on both sides of the fourth collector layer by forming the collector electrode layer. Is formed.

In a preferred embodiment of this method, the third and fifth collector layers and the base layer are formed of GaAs material and the second and fourth collector layers are formed of InGaAs material.

In a preferred embodiment of this method, the method of manufacturing the HBT further comprises doping the second collector layer at a high concentration of about 1OE20 cm ^-3 to reduce the collector resistance.

In a preferred embodiment of this method, the undercut etching of the third collector layer reduces the base-collector area.

In a preferred embodiment of this method, the second insulating spacer serves to support the device.

In a preferred embodiment of this method, the collector electrode layer formed on the base electrode reduces the resistance of the base electrode.

According to the present invention for achieving the above object, the HBT includes an upper material layer and a lower material layer, and an intermediate material layer, wherein the intermediate material layer is formed to have a relatively narrow width with respect to the upper material layer; A collector layer formed to electrically connect the upper material layer and the lower material layer; A collector electrode formed to be electrically connected to a lower material layer on lower material layers on both sides of the upper material layer; An insulation layer formed on both the lower side of the upper material layer and the lower material layer of the recessed portion including both sidewalls of the intermediate material layer; A base layer formed on the upper material layer to be electrically connected to the upper material layer; An emitter layer on the base layer, the emitter layer having a smaller width than the base layer, the emitter layer being electrically connected to the base layer, and formed of a multilayer film including GaAs and AlGaAs; An emitter electrode formed on the emitter layer to be electrically connected to the emitter layer; The base layer is formed on the base layer on both sides of the emitter layer to be electrically connected to the base layer, and a part of the base electrode is formed to be relatively thick.

In a preferred embodiment of the device, the collector layer comprises a GaAs and InGaAs material layer.

In a preferred embodiment of the device, the insulating layer serves to support the device.

[Action]

The heterojunction bipolar transistor according to the present invention and its manufacturing method improve the speed of HBT and form a reproducible HBT element.

EXAMPLE

Referring to FIG. 3, a novel heterojunction bipolar transistor according to an embodiment of the present invention and a method of manufacturing the same, an n + type first collector layer and an n− type second collector layer and an n− type third collector on a semiconductor substrate A layer, an n-type fourth collector layer, an n-type fifth collector layer, a base layer, an emitter layer and an emitter electrode are sequentially formed. Base electrodes are formed on the base layers on both sides of the emitter layer. First insulating spacers are formed on both sidewalls of the emitter electrode and the base electrode. The base layer and the fifth collector layer on each side of the base electrode are etched and patterned using the fourth collector layer as an etch stop layer. The fourth collector layers on both sides of the fifth collector layer are removed. The third collector layers on both sides of the fourth collector layer are etched to have an under cut profile with respect to the fourth collector layer. Second insulating spacers are formed on inner walls of the undercut portions, including both sides of the third collector layer. The photoresist film pattern is formed to include a portion of the base electrode on both sides of the emitter electrode, including the emitter electrode, and then the collector electrode layer is formed on the entire surface of the semiconductor substrate using the mask as a mask.

The formation of the collector electrode layer forms a collector electrode on the n-type second collector layer in self alignment. With such a semiconductor device and its manufacturing method, the parasitic capacitance of the base-collector can be reduced by reducing the junction area between the base and the collector, and the base resistance can be reduced by overlapping the collector electrode layer on the base electrode when forming the collector electrode. This can improve the speed of the HBT. In addition, the collector electrode can be formed by self alignment.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 3 to 6.

3 is a cross-sectional view showing the structure of the HBT according to the embodiment of the present invention, Figure 4 is a cross-sectional view showing the configuration of the HBT layer according to the embodiment of the present invention.

Referring to FIG. 3, an HBT according to an embodiment of the present invention includes a collector layer formed on a semiconductor substrate (not shown). The collector layer comprises an upper material layer 36a, 38a, a lower material layer 30, 32, and an intermediate material layer 34a.

The intermediate material layer 34a is formed to have a relatively narrow width with respect to the upper material layers 36a and 38a. The intermediate material layer 34a is formed such that the upper material layers 36a and 38a and the lower material layers 30 and 32 are electrically connected.

Insulation spacers 48 formed on the lower portions of the upper material layers 36a and 38a and the upper portion of the lower material layers 30 and 32, including both sidewalls of the intermediate material layer 34a. The collector electrode 52a is formed on the lower material layers 30 and 32 on both sides of the upper material layers 36a and 38a to be electrically connected to the lower material layers 30 and 32. And a base layer 40a formed on the upper material layers 36a and 38a to be electrically connected to the upper material layers 36a and 38a. The emitter layer 42 has a width smaller than that of the base layer 40a on the base layer 40a and is formed to be electrically connected to the base layer 40a. The emitter layer 42 is formed of a multilayer film including GaAs and AlGaAs material layers.

The base layer 40a is formed on both sides of the emitter layer 42 so as to be electrically connected to the base layer 40a, and a part of the emitter layer 42 includes relatively thick base electrodes 45 and 52b. It also includes other insulating spacers 46a and 46b formed on both sidewalls of the emitter electrode 44 and both sidewalls of the base electrodes 45 and 52b.

The lower material layers 30 and 32 include an n + type first collector layer 30 and an n− type second collector layer 32 formed on the first collector layer 30. The intermediate material layer 34a is an n-type third collector layer 34a formed on the second collector layer 32. The upper material layers 36a and 38a include an n-type fourth collector layer 36a and an n-type fifth collector layer 38a formed on the third collector layer 34a.

Referring to FIG. 4, the structure of the HBT layer includes the first and third collector layers 30 and 34a, the fifth collector layer 38a, and the base layer 40a, for example, formed of GaAs material. The second and fourth collector layers 32 and 36a may be formed of a material having an etching selectivity different from that of the GaAs material, for example, InGaAs material.

The emitter layer 42 is, for example, a multilayer film in which an n-type AlGaAs material layer 42a, an n-type GaAs material layer 42b, and an n + type InGaAs material layer 42c are sequentially stacked.

The HBT structure as described above is used to improve the speed of the HBT.

5 is a three-dimensional view of the reference numeral 55 of FIG.

Referring to FIG. 5, A1 represents the lower area of the emitter layer 42 and A represents the junction area of the base-collector.

First, the HBT structure reduces base-collector capacitance.

The equation for obtaining a frequency at which f _max of the conventional HBT, that is, power gain becomes 1 is as follows.

In the above formula, f _t represents a frequency at which current gain becomes 1, and R _b represents a base resistance. C _bc represents the base-collector capacitance.

D1 represents the deflation width of the collector in FIG. 1. A represents the junction area of the base-collector.

To improve the speed of HBT, R _b and C _bc must be reduced. In order to reduce the C _bc , the depletion width D1 should be reduced or the junction area A of the base-collector should be reduced.

In the HBT structure of the present invention, the area of reference number 16 of the conventional HBT structure shown in FIG. 1 is etched to reduce the junction area of the base-collector.

The base-collector capacitance C _bc 'according to the present invention is obtained as follows.

In Equation 2, d represents the thickness of the third collector layer 34a. D2 denotes the deflation width of the collector in FIG. 3. A1 and A respectively represent the emitter area and the junction area of the base-collector in FIG. 5.

Referring to Equation 2, the base-collector capacitance is reduced by 60% or more for an HBT having a general emitter area of 2 * 300 μm ² . Accordingly, the f _max is increased by about 50%.

The manufacturing method of the HBT as described above is as follows.

6A to 6H are cross-sectional views sequentially illustrating a method of manufacturing HBT according to an embodiment of the present invention.

Referring to FIG. 6A, a method of manufacturing an HBT according to an embodiment of the present invention may first include an n + type first collector layer 30 and an n− type second collector layer 32 on a semiconductor substrate (not shown). , n-type third collector layer 34, n-type fourth collector layer 36, n-type fifth collector layer 38, base layer 40, emitter layer 42, and emitter electrode (44) are formed in order.

The second and fourth collector layers 32 and 36 are formed of a material having an etching selectivity different from that of the third and fifth collector layers 34 and 38 and the base layer 40. For example, the third and fifth collector layers 34 and 38 and the base layer 40 are formed of GaAs material, and the second and fourth collector layers 32 and 36 are formed of InGaAs material. .

More specifically, the second collector layer 32 is formed of an In0.2Ga0.8As material having a thickness of about 300 GPa, and the fourth collector layer 36 is formed of an In0.2Ga0.8As material having a thickness of about 100 GPa. . The fifth collector layer 38 is formed to a thickness of about 2000 mm 3.

The reason why the GaAs fifth collector layer 38 is formed after the InGaAs fourth collector layer 36 is formed is that the energy gap of the InGaAs fourth collector layer 36 is small, resulting in a breakdown voltage. This is to allow the InGaAs fourth collector layer 36 to be formed at some distance from the strong base-collector junction because it may deteriorate. Since the thickness of the GaAs fifth collector layer 38 should be within the collector deflection width, which is generally in the range of 0.4-0.8 μm, the GaAs fifth collector layer 38 was set to about 2000 mW as described above.

The thickness of the InGaAs fourth collector layer 36 is about 100 GPa, and the composition ratio of In and Ga is 0.2: 0.8 because the lattice defect increases and the energy gap decreases as the content of In increases. Because it is the composition ratio optimized to prevent this. In addition, this is also a composition ratio for securing a minimum etching selectivity for GaAs.

The GaAs third collector layer 34 has a different thickness depending on the intended use.

The InGaAs second collector layer 32 serves as an etch stop layer in a subsequent process. The collector contact resistance may be improved by increasing the doping concentration of the second collector layer 32 to 1OE20 cm ⁻³ .

The emitter layer 42 is formed by patterning a multilayer film containing GaAs and AlGaAs. More specifically, the emitter layer 42 is a multilayer film in which an n-type AlGaAs material layer 42a, an n-type GaAs material layer 42b, and an n + type InGaAs material layer 42c are sequentially stacked.

The emitter electrode 44 is formed on the emitter layer 42 to be electrically connected to the emitter layer 42. The base electrode 45 is formed to be electrically connected to the base layer 40 on the base layer 40 on both sides of the emitter layer 42.

In FIG. 6B, first insulating spacers 46a and 46b are formed on both sidewalls of the emitter electrode 44 and the base electrode 45. The first insulating spacers 46a and 46b are formed to fill between the emitter electrode 44 and the base electrode 45. The first insulating spacers 46a and 46b prevent the base layer 40 from being etched in a subsequent etching process.

Referring to FIG. 6C, the base layer 40 and the fifth collector layer 38 on each side of the base electrode 45 are etched and patterned using the fourth collector layer 36 as an etch stop layer. This etching process is carried out with a dry etching process using CCl ₂ F ₂ gas.

In FIG. 6D, the fourth collector layer 36 on both sides of the fifth collector layer 38a is removed. Removal of the fourth collector layer 36 is performed using H ₂ SO ₄ aqueous solution.

Referring to FIG. 6E, the third collector layer 34 on both sides of the fourth collector layer 36a is etched to have an undercut profile with respect to the fourth collector layer 36a. This etching process is performed by overetching the third collector layer 34 on both sides of the fourth collector layer 36a using CCl ₂ F ₂ gas. That is, an isotropic dry etching process is performed. In the undercut etching of the third collector layer 34, the second collector layer 32 is used as an etch stop layer. In addition, the fourth collector layer 36a prevents etching of the fifth collector layer 38a.

The width of the third collector layer 34a is formed to be approximately equal to the width of the emitter layer 42.

In FIG. 6F, a second insulating spacer is formed on an inner wall of the undercut portion, that is, both side walls of the third collector layer 34a, an upper portion of the second collector layer 32, and a lower portion of the fourth collector layer 36a. Form 48.

The second insulating spacer 48 serves to support the device. The undercut portion is formed so as not to be completely filled when the second insulating spacer 48 is formed, so that the subsequent collector electrode 52a is self-aligned on the second collector layer 32.

Referring to FIG. 6G, the photoresist layer pattern 50 is formed to include a portion of the base electrodes 45 and 52b on both sides of the emitter electrode 44 including the emitter electrode 44. The collector electrode layers 52a, 52b, and 52c are formed on the entire surface of the semiconductor substrate using the photoresist film pattern 50 as a mask.

Finally, when the photoresist layer pattern 50 is lifted off, as shown in FIG. 6H, the collector electrode 52a is electrically connected to the second collector layer 32 on the second collector layer 32. ) Is formed by self alignment. In addition, the collector electrode layer 52b is formed on a portion of the base electrode 45 to reduce the base resistance.

The subsequent process is the same as the manufacturing method of the general HBT.

The present invention can reduce the base-collector capacitance by reducing the junction area between the base and the collector, and can reduce the base resistance by overlapping the collector electrode layer on the base electrode when forming the collector electrode, thereby improving the speed of the HBT. Can be. In addition, there is an effect that the collector electrode can be formed by self alignment.

Claims (9)

The first high concentration first collector layer 30 and the first low concentration second collector layer 32, the second low concentration third collector layer 34, the third low concentration fourth collector layer 36, and the fourth on the semiconductor substrate The low concentration fifth collector layer 38, the base layer 40, the emitter layer 42, and the emitter electrode 44 are sequentially formed, and the second and fourth collector layers 32 and 36 are formed of the second agent. The third and fifth collector layers 34 and 38 and the base layer 40 are formed of materials having different etching selectivity, and the emitter layer 42 is formed by patterning a multilayer film including GaAs and AlGaAs. Steps; Forming a base electrode (45) on the base layer (40) on both sides of the emitter layer (42); First insulating spacers 46a and 46b are formed on both sidewalls of the emitter electrode 44 and the base electrode 45, and the first insulating spacer is between the emitter electrode 44 and the base electrode 45. Forming to be filled with (46a, 46b); Etching and patterning the base layer (40) and the fifth collector layer (38) on each side of the base electrode (45) using the fourth collector layer (36) as an etch stop layer; Removing the fourth collector layer (36) on both sides of the fifth collector layer (38a); Dry etching the third collector layer (34) on both sides of the fourth collector layer (36a) to have an under cut profile with respect to the fourth collector layer (36a); Forming a second insulating spacer (48) on an inner wall of the undercut portion, including both sides of the third collector layer (34a); Forming a photoresist film pattern (50) including the emitter electrode (44) to mask a portion of the base electrode (45) on both sides of the emitter electrode (44); Forming a collector electrode layer (52a, 52b, 52c) on the entire surface of the semiconductor substrate using the photoresist film pattern (50) as a mask, and forming the collector electrode layers (52a, 52b, 52c). The collector electrode (52a) is formed on the second collector layer (32) on both sides of the collector layer (36) in the manufacturing method of HBT. The method of claim 1, wherein the third and fifth collector layers 34, 38, and the base layer 40 are formed of a GaAs material, and the second and fourth collector layers 32, 36 are made of InGaAs material. Method for producing HBT formed. The method of claim 1, wherein the method of manufacturing HBT further comprises the step of doping the second collector layer (32) at a high concentration of about 1OE20 cm ^-3 to reduce collector resistance. The method of claim 1, wherein the undercut etching of the third collector layer (34) reduces the base-collector area. The method of claim 1, wherein the second insulating spacer (48) serves to support the device. The method of claim 1, wherein the collector electrode layer (52b) formed on the base electrode (45) reduces the resistance of the base electrode (45). An upper material layer 36a, 38a and a lower material layer 30, 32, and an intermediate material layer 34a, wherein the intermediate material layer 34a is relatively to the upper material layer 36a, 38a. A collector layer formed to have a narrow width and formed to electrically connect the upper material layers 36a and 38a and the lower material layers 30 and 32; A collector electrode (52a) formed on the lower material layers (30, 32) on both sides of the upper material layers (36a, 38a) so as to be electrically connected to the lower material layers (30, 32); An insulating layer (48) formed on the lower portion of the upper material layer (36a, 38a) and the lower material layer (30, 32) of the recessed portion including both sidewalls of the intermediate material layer (34a); A base layer 40a formed on the upper material layers 36a and 38a to be electrically connected to the upper material layers 36a and 38a; An emitter layer 42 formed on the base layer 40a having a smaller width than the base layer 40a and electrically connected to the base layer 40a, and formed of a multilayer film including GaAs and AlGaAs; ; An emitter electrode (44) formed on the emitter layer (42) to be electrically connected to the emitter layer (42); An HBT comprising a base electrode (45, 52b) formed on the base layer (40a) on both sides of the emitter layer (42) to be electrically connected to the base layer (40a), a part of which is relatively thick. 8. The HBT of claim 7 wherein the collector layer comprises a GaAs and InGaAs material layer. 8. The HBT of claim 7, wherein the insulating layer (48) serves to support the device.