JPH11145153A - Method for manufacturing compound semiconductor transistor - Google Patents
Method for manufacturing compound semiconductor transistorInfo
- Publication number
- JPH11145153A JPH11145153A JP9307266A JP30726697A JPH11145153A JP H11145153 A JPH11145153 A JP H11145153A JP 9307266 A JP9307266 A JP 9307266A JP 30726697 A JP30726697 A JP 30726697A JP H11145153 A JPH11145153 A JP H11145153A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- layer
- forming
- electrode
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 150000001875 compounds Chemical class 0.000 title claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000007747 plating Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 239000012535 impurity Substances 0.000 description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ヘテロ接合バイポ
ーラトランジスタ（ＨＢＴ）の製造方法に関し、特にエ
ミッタとベース間の漏れ電流がなく、高周波特性に優れ
たＨＢＴの製造方法に関する。The present invention relates to a method of manufacturing a heterojunction bipolar transistor (HBT), and more particularly to a method of manufacturing an HBT having no leakage current between an emitter and a base and having excellent high-frequency characteristics.
【０００２】[0002]
【従来の技術】ＨＢＴは、エミッタ層としてベース層よ
りもバンドギャップの大きい半導体材料を用いることに
よって、ベース層の不純物濃度を高くしてもエミッタ注
入効率を大きく保つことができること、化合物半導体の
優れた電子輸送特性を活かすことができることなど、ト
ランジスタの高性能化に有利な多くの利点を有してい
る。2. Description of the Related Art An HBT uses a semiconductor material having a band gap larger than that of a base layer as an emitter layer, so that the emitter injection efficiency can be kept large even if the impurity concentration of the base layer is increased. There are many advantages that are advantageous for improving the performance of a transistor, such as the fact that the electron transport characteristics can be utilized.
【０００３】ＨＢＴの有する優れた特性を引き出すため
には、寄生の抵抗と容量とを小さくすることが必要であ
り、特に、ベース電極とエミッタ電極を極力近づけるこ
とによりベース抵抗を低減することが重要である。その
ために種々のセルフアライン構造が提案されている。In order to bring out the excellent characteristics of the HBT, it is necessary to reduce parasitic resistance and capacitance. In particular, it is important to reduce the base resistance by bringing the base electrode and the emitter electrode as close as possible. It is. For that purpose, various self-aligned structures have been proposed.
【０００４】例えば、特開平８−１３９１０１号公報等
には、図４（ａ）に示すように、エミッタ電極４３を先
行して形成し、そのエミッタ電極４３をマスクとして、
ベース層４１に対してエミッタ層４２を選択的にエッチ
ングする溶液を用いてエミッタメサエッチングを行い、
同時に、ウェットエッチングの等方性を利用して電極外
周部下にアンダーカットを形成した後、図４（ｂ）に示
すように、エミッタメサを含む領域にベース電極４４を
蒸着する方法が記載されている。この方法によれば、ア
ンダーカットがあるために、エミッタ電極とベース電極
とは短絡することなくセルフアラインされる。[0004] For example, in Japanese Patent Application Laid-Open No. 8-139101, an emitter electrode 43 is formed in advance and as shown in FIG.
Emitter mesa etching is performed using a solution for selectively etching the emitter layer 42 with respect to the base layer 41,
At the same time, a method is described in which an undercut is formed under the outer periphery of the electrode by using the isotropic property of wet etching, and then, as shown in FIG. 4B, a base electrode 44 is deposited on a region including the emitter mesa. . According to this method, the emitter electrode and the base electrode are self-aligned without short-circuiting due to the undercut.
【０００５】しかし、この方法では、エミッタ電極とそ
の下のアンダーカットの形状の厳密に制御する必要があ
り、またエミッタ層４２の側壁はむき出しのままである
ので、ベース電極４４を形成する際に金属が垂直に蒸着
されるように蒸着条件をも厳密に制御する必要があっ
た。However, in this method, it is necessary to strictly control the shape of the emitter electrode and the undercut thereunder, and since the side wall of the emitter layer 42 is exposed, It was necessary to strictly control the deposition conditions so that the metal was deposited vertically.
【０００６】そこで、例えば特開平５−２７５４４４号
公報には、図５（ａ）に示すようにエミッタ層５２およ
びエミッタ電極５３の側壁に絶縁膜５５を形成し、ベー
ス電極金属５４を全面に蒸着した後、図５（ｂ）に示す
ように、レジスト５７をリフトオフし、続いて斜めイオ
ン・ミリング法を適用することにより、図に矢印で指示
してあるようにイオンの照射を行って、Ｔｉ／Ｐｔ／Ａ
ｕ膜のうち、ベース層５１とコンタクトしている部分及
びエミッタ電極５３とコンタクトしている部分を切り離
すことでベース電極５８を形成する方法が記載されてい
る。Therefore, for example, in Japanese Patent Application Laid-Open No. 5-275444, an insulating film 55 is formed on the side walls of the emitter layer 52 and the emitter electrode 53 as shown in FIG. After that, as shown in FIG. 5B, the resist 57 is lifted off, and then, by applying an oblique ion milling method, ion irradiation is performed as indicated by an arrow in the figure, and Ti is irradiated. / Pt / A
A method of forming a base electrode 58 by separating a portion of the u film that is in contact with the base layer 51 and a portion that is in contact with the emitter electrode 53 is described.
【０００７】しかし、この方法では、側壁絶縁膜の膜厚
が薄いために金属膜をエッチングをする際に非常に正確
なエッチングコントロールが必要であり、歩留まりを上
げることは極めて困難である。However, in this method, since the thickness of the side wall insulating film is thin, very accurate etching control is required when etching the metal film, and it is extremely difficult to increase the yield.
【０００８】[0008]
【発明が解決しようとする課題】本発明は、このような
従来の問題点に鑑みてなされたものであり、ベース電極
とエミッタ電極を近接させた高周波特性の優れたＨＢＴ
構造を、簡単な工程により歩留まり良く製造する方法を
提供することを目的とする。SUMMARY OF THE INVENTION The present invention has been made in view of such a conventional problem, and has an HBT having a high frequency characteristic in which a base electrode and an emitter electrode are arranged close to each other.
It is an object of the present invention to provide a method for manufacturing a structure by a simple process with a high yield.
【０００９】[0009]
【課題を解決するための手段】本発明は、化合物半導体
基板上に、コレクタ層、ベース層、エミッタ層を形成す
る工程と、前記エミッタ層の上に、所定形状のエミッタ
電極を形成する工程と、前記エミッタ電極をマスクとし
て前記エミッタ層をエッチングし、エミッタ電極下部以
外のベース層を露出させる工程と、所定形状にパターン
された前記エミッタ層およびエミッタ電極の側面に側壁
絶縁膜を形成する工程と、少なくともベース層上のベー
ス電極を形成する領域に開口を有するレジスト膜を形成
する工程と、前記レジスト膜の開口に露出しているベー
ス層表面にメッキによりベース電極金属を成膜してベー
ス電極を形成する工程とを有する化合物半導体トランジ
スタの製造方法である。SUMMARY OF THE INVENTION The present invention comprises a step of forming a collector layer, a base layer, and an emitter layer on a compound semiconductor substrate, and a step of forming an emitter electrode having a predetermined shape on the emitter layer. Etching the emitter layer using the emitter electrode as a mask to expose a base layer other than under the emitter electrode, and forming a sidewall insulating film on a side surface of the emitter layer and the emitter electrode patterned in a predetermined shape. Forming a resist film having an opening at least in a region where a base electrode is formed on the base layer; and forming a base electrode metal by plating on a surface of the base layer exposed at the opening of the resist film. Forming a compound semiconductor transistor.
【００１０】本発明では、このようにベース電極の形成
をメッキを用いて行うので、エミッタとベース間の距離
は、側壁絶縁膜の厚さだけで決まる。このためエミッタ
とベース間の距離を短くできると共に、複雑で微細なエ
ッチング加工を必要とせず、工程が簡略化され歩留まり
が向上する。また、エミッタ側面を側壁絶縁膜で覆って
いるのでエミッタとベース間の短絡もない。In the present invention, since the base electrode is formed by plating, the distance between the emitter and the base is determined only by the thickness of the sidewall insulating film. For this reason, the distance between the emitter and the base can be shortened, and complicated and fine etching is not required, the process is simplified, and the yield is improved. Further, since the side surface of the emitter is covered with the sidewall insulating film, there is no short circuit between the emitter and the base.
【００１１】[0011]
【発明の実施の形態】次に、図面を参照しながら本発明
を詳細に説明する。Next, the present invention will be described in detail with reference to the drawings.
【００１２】まず、図１（ａ）に示すように化合物半導
体基板１上に、コレクタ層２、ベース層３、エミッタ層
４を順次形成する。ここで、化合物半導体基板として
は、ＧａＡｓ、ＩｎＰ等の基板であり、通常半絶縁性の
基板を用いる。コレクタ層、ベース層、エミッタ層を形
成する材料は、ＧａＡｓ、ＡｌＧａＡｓ、ＩｎＧａＡ
ｓ、ＩｎＰ等から、格子整合や用途に合わせて適宜選択
して気相成長等により形成することができる。例えば、
化合物半導体基板として、半絶縁性のＧａＡｓ基板を用
いて、コレクタ層をｎ−ＧａＡｓ、ベース層をｐ−Ｇａ
Ａｓ、エミッタ層をｎ−ＡｌＧａＡｓ等で形成すること
ができる。また、化合物半導体基板とコレクタ層の間に
ｎ+−ＧａＡｓサブ・コレクタ層を設けたり、エミッタ
層の上にｎ+−ＩｎＧａＡｓサブ・エミッタ層等を設け
たり、さらに必要に応じてその他の層を設けてもよい。First, as shown in FIG. 1A, a collector layer 2, a base layer 3, and an emitter layer 4 are sequentially formed on a compound semiconductor substrate 1. Here, the compound semiconductor substrate is a substrate of GaAs, InP or the like, and usually a semi-insulating substrate is used. Materials for forming the collector layer, the base layer, and the emitter layer are GaAs, AlGaAs, and InGaAs.
s, InP or the like can be formed by vapor phase growth or the like by appropriately selecting according to lattice matching or use. For example,
A semi-insulating GaAs substrate is used as the compound semiconductor substrate, and the collector layer is n-GaAs and the base layer is p-Ga
As and the emitter layer can be formed of n-AlGaAs or the like. Further, an n + -GaAs sub-collector layer is provided between the compound semiconductor substrate and the collector layer, an n + -InGaAs sub-emitter layer is provided on the emitter layer, and other layers are provided as necessary. It may be provided.
【００１３】尚、ベース層の不純物濃度はなるべく高い
方が好ましく、１×１０19ｃｍ-3以上が特に好ましい。Incidentally, the impurity concentration of the base layer is preferably as high as possible, particularly preferably 1 × 10 19 cm -3 or more.
【００１４】次に、図１（ｂ）に示すように、エミッタ
層の上にエミッタ電極５形成する。形成方法は、どのよ
うな方法でも良いが、例えば予めエミッタ電極を形成す
る部分に開口を有するレジスト膜を形成し、その後Ｔｉ
／Ｐｔ／Ａｕの３層構造の金属膜等を成膜した後、レジ
スト膜をリフトオフすることで形成することができる。Next, as shown in FIG. 1B, an emitter electrode 5 is formed on the emitter layer. Any method may be used for forming the resist film. For example, a resist film having an opening in a portion where an emitter electrode is to be formed is formed in advance, and then a
After forming a metal film or the like having a three-layer structure of / Pt / Au, the resist film can be formed by lift-off.
【００１５】次に、図１（ｃ）に示すように、エミッタ
電極をマスクとしてエミッタ層４を、反応性イオンエッ
チング等を用いて垂直方向にエッチングすると共に、ベ
ース層３の表面を露出させる。Next, as shown in FIG. 1C, the emitter layer 4 is vertically etched using reactive ion etching or the like using the emitter electrode as a mask, and the surface of the base layer 3 is exposed.
【００１６】次に、図２（ａ）に示すように、エミッタ
層４およびエミッタ電極５の側面に側壁絶縁層６を形成
する。形成方法は、例えば、ＳｉＯＮ膜等をＣＶＤ等に
より全面に形成した後、ドライエッチングによりエッチ
バックすることで形成することができる。Next, as shown in FIG. 2A, a sidewall insulating layer 6 is formed on the side surfaces of the emitter layer 4 and the emitter electrode 5. For example, it can be formed by forming an SiON film or the like on the entire surface by CVD or the like, and then etching back by dry etching.
【００１７】次に、図２（ｂ）に示すように、レジスト
膜を塗布した後、露光・現像によりベース電極を形成す
る領域に開口を有するレジスト膜９を形成する。この開
口は、ベース層上のベース電極形成部分だけでなく側壁
絶縁膜６の部分も開口内に入るように形成するのが好ま
しく、図のようにエミッタ部分全体を開口内に入るよう
にするのが簡便で好ましい。尚、この図の紙面方向にお
けるレジストパターン形状は、素子構造によって適宜決
める。Next, as shown in FIG. 2B, after applying a resist film, a resist film 9 having an opening in a region where a base electrode is to be formed is formed by exposure and development. This opening is preferably formed so that not only the base electrode forming portion on the base layer but also the portion of the side wall insulating film 6 enters the opening. As shown in the drawing, the entire emitter portion enters the opening. Is simple and preferred. Note that the resist pattern shape in the direction of the paper of FIG.
【００１８】次に、図２（ｃ）に示すように、前記のレ
ジスト開口に、電解メッキにより、例えばＰｔ／Ａｕの
積層膜のベース電極１０を形成する。電解メッキの際に
直流電源との接続は、ベース層のどの位置でコンタクト
をとってもよく、例えば化合物半導体基板の周辺付近に
もレジストの開口を設け、この開口から露出しているベ
ース層とコンタクトをとればよい。このとき、ベース層
のコンタクト部分に例えばＡｕＺｎ、ＡｕＢｅ等のオー
ミック金属を蒸着等により形成すると、直流電源との電
気的接続を確実に行うことができる。ベース層の不純物
濃度が非常に高い場合は、オーミック金属を設ける必要
は通常はない。Next, as shown in FIG. 2C, a base electrode 10 of a laminated film of, for example, Pt / Au is formed in the resist opening by electrolytic plating. In the case of electrolytic plating, connection with a DC power supply may be made at any position on the base layer.For example, an opening of a resist is provided near the periphery of the compound semiconductor substrate, and the base layer exposed from this opening is contacted with the base layer. What should I do? At this time, when an ohmic metal such as AuZn or AuBe is formed on the contact portion of the base layer by vapor deposition or the like, electrical connection with a DC power supply can be reliably performed. If the impurity concentration of the base layer is very high, it is not usually necessary to provide an ohmic metal.
【００１９】次に、レジスト膜を剥離すると、図３に示
すようなトランジスタ構造が完成する。このように、ベ
ース電極とエミッタ層との距離は、側壁絶縁膜の厚さの
みで決まるので、レジストの形成では精度を必要としな
いことがわかる。Next, when the resist film is removed, a transistor structure as shown in FIG. 3 is completed. As described above, since the distance between the base electrode and the emitter layer is determined only by the thickness of the side wall insulating film, it can be seen that precision is not required for forming the resist.
【００２０】[0020]
【発明の効果】本発明によれば、ベース電極の形成をメ
ッキを用いて行うので、エミッタとベース間の距離は、
側壁絶縁膜の厚さだけで決まる。このためエミッタとベ
ース間の距離を短くできると共に、複雑で微細なエッチ
ング加工を必要とせず、工程が簡略化され歩留まりが向
上する。また、エミッタ側面を側壁絶縁膜で覆っている
のでエミッタとベース間の短絡もない。即ち、本発明に
よれば高周波特性の優れたＨＢＴ構造を、簡単な工程に
より歩留まり良く製造することができる。According to the present invention, since the base electrode is formed by plating, the distance between the emitter and the base is
It is determined only by the thickness of the sidewall insulating film. For this reason, the distance between the emitter and the base can be shortened, and complicated and fine etching is not required, the process is simplified, and the yield is improved. Further, since the side surface of the emitter is covered with the sidewall insulating film, there is no short circuit between the emitter and the base. That is, according to the present invention, an HBT structure having excellent high-frequency characteristics can be manufactured by a simple process with a high yield.
【図１】本発明の製造方法を模式的に示した図である。FIG. 1 is a view schematically showing a production method of the present invention.
【図２】図１に引き続き、本発明の製造方法を模式的に
示した図である。FIG. 2 is a view schematically showing the manufacturing method of the present invention, following FIG. 1;
【図３】図１、図２に引き続き、本発明の製造方法を模
式的に示した図である。FIG. 3 is a view schematically showing the manufacturing method of the present invention, following FIGS. 1 and 2;
【図４】従来の製造方法を示す図である。FIG. 4 is a view showing a conventional manufacturing method.
【図５】従来の製造方法を示す図である。FIG. 5 is a view showing a conventional manufacturing method.
１ 化合物半導体基板 ２ コレクタ層 ３ ベース層 ４ エミッタ層 ５ エミッタ電極 ６ 側壁絶縁膜 ９ レジスト膜 １０ ベース電極 DESCRIPTION OF SYMBOLS 1 Compound semiconductor substrate 2 Collector layer 3 Base layer 4 Emitter layer 5 Emitter electrode 6 Side wall insulating film 9 Resist film 10 Base electrode
Claims (2)
ース層、エミッタ層を形成する工程と、 前記エミッタ層の上に、所定形状のエミッタ電極を形成
する工程と、 前記エミッタ電極をマスクとして前記エミッタ層をエッ
チングし、エミッタ電極下部以外のベース層を露出させ
る工程と、 所定形状にパターンされた前記エミッタ層およびエミッ
タ電極の側面に側壁絶縁膜を形成する工程と、 少なくともベース層上のベース電極を形成する領域に開
口を有するレジスト膜を形成する工程と、 前記レジスト膜の開口に露出しているベース層表面にメ
ッキによりベース電極金属を成膜してベース電極を形成
する工程とを有する化合物半導体トランジスタの製造方
法。A step of forming a collector layer, a base layer, and an emitter layer on a compound semiconductor substrate; a step of forming an emitter electrode having a predetermined shape on the emitter layer; Etching the emitter layer to expose the base layer other than under the emitter electrode; forming a sidewall insulating film on the side surfaces of the emitter layer and the emitter electrode patterned in a predetermined shape; Forming a resist film having an opening in a region where a resist film is formed; and forming a base electrode by forming a base electrode metal by plating on a surface of the base layer exposed to the opening of the resist film. A method for manufacturing a semiconductor transistor.
層上のベース電極を形成する領域と側壁絶縁膜を含む開
口を有するレジスト膜を形成する工程である請求項１記
載の化合物半導体トランジスタの製造方法。2. The method of manufacturing a compound semiconductor transistor according to claim 1, wherein the step of forming a resist film is a step of forming a resist film having a region on a base layer for forming a base electrode and an opening including a sidewall insulating film. Method.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9307266A JPH11145153A (en) | 1997-11-10 | 1997-11-10 | Method for manufacturing compound semiconductor transistor |
| DE19851382A DE19851382A1 (en) | 1997-11-10 | 1998-11-07 | Producing compound semiconductor hereto-junction bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9307266A JPH11145153A (en) | 1997-11-10 | 1997-11-10 | Method for manufacturing compound semiconductor transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11145153A true JPH11145153A (en) | 1999-05-28 |
Family
ID=17967054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9307266A Withdrawn JPH11145153A (en) | 1997-11-10 | 1997-11-10 | Method for manufacturing compound semiconductor transistor |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH11145153A (en) |
| DE (1) | DE19851382A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100491089B1 (en) * | 2002-12-06 | 2005-05-24 | 한국전자통신연구원 | Heterojunction bipolar transistor and manufacturing method thereof |
| CN107895696A (en) * | 2017-11-03 | 2018-04-10 | 厦门市三安集成电路有限公司 | A kind of high-precision HBT preparation technologies |
-
1997
- 1997-11-10 JP JP9307266A patent/JPH11145153A/en not_active Withdrawn
-
1998
- 1998-11-07 DE DE19851382A patent/DE19851382A1/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100491089B1 (en) * | 2002-12-06 | 2005-05-24 | 한국전자통신연구원 | Heterojunction bipolar transistor and manufacturing method thereof |
| CN107895696A (en) * | 2017-11-03 | 2018-04-10 | 厦门市三安集成电路有限公司 | A kind of high-precision HBT preparation technologies |
Also Published As
| Publication number | Publication date |
|---|---|
| DE19851382A1 (en) | 1999-05-20 |
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| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
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