KR100290769B1 - Method for forming tungsten plug - Google Patents

Method for forming tungsten plug Download PDF

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KR100290769B1
KR100290769B1 KR1019940035698A KR19940035698A KR100290769B1 KR 100290769 B1 KR100290769 B1 KR 100290769B1 KR 1019940035698 A KR1019940035698 A KR 1019940035698A KR 19940035698 A KR19940035698 A KR 19940035698A KR 100290769 B1 KR100290769 B1 KR 100290769B1
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film
titanium
forming
layer
semiconductor device
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KR1019940035698A
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Korean (ko)
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KR960026171A (en
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박상훈
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박종섭
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a tungsten plug is provided to improve a connection among metal interconnections in a semiconductor device by selectively and easily depositing a tungsten layer after leaving a nitride layer and a titanium nitride only in a contact hole. CONSTITUTION: A diffusion area(12) is formed by implanting doped dopants in a substrate(11). Then, an insulation oxide(13) and a nitride layer(14) are sequentially formed on the entire surface of the resultant structure. A contact hole is formed by etching the insulation oxide(13) and the nitride layer(14). A titanium layer(16) and a titanium nitride layer(17) is sequentially deposited on the resultant structure by sputtering. A TEOS(Tetra Ethyl Ortho Silicate) oxide is deposited on the titanium nitride layer(17). The nitride layer(14) is exposed by etching the titanium nitride layer(17) and the titanium layer(16). A tungsten layer(19) is selectively formed on the exposed titanium nitride(17) in the contact hole.

Description

텅스텐 플러그 형성 방법How to Form Tungsten Plug

제1도는 종래의 텅스텐 플러그 형성 방법을 설명하는 단면도.1 is a cross-sectional view illustrating a conventional tungsten plug forming method.

제2(a)도 내지 제2(d)도는 본 발명에 따른 플러그 형성 방법을 순차적으로 나타내는 공정도.2 (a) to 2 (d) is a process chart sequentially showing a plug forming method according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1, 11 : 반도체 기판 2, 12 : N+영역1, 11: semiconductor substrate 2, 12: N + region

3, 13 : 절연산화막 4, 19 : 텅스텐 막3, 13: insulating oxide film 4, 19: tungsten film

14 : 질화막 15 : 콘택 홀14 nitride film 15 contact hole

16 : Ti 막 17 : TiN 막16: Ti film 17 TiN film

18 : TEOS 산화막18: TEOS oxide film

본 발명은 금속 배선 방법에 관한 것으로, 특히 금속 배선간의 연결을 위한 초미세 콘택홀을 매립하는 텅스텐 플러그를 통하여 반도체 기판에 콘택하는 금속 배선 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal wiring method, and more particularly, to a metal wiring method of contacting a semiconductor substrate through a tungsten plug which embeds an ultra-fine contact hole for connection between metal wirings.

반도체 소자가 고집적화됨에 따라 반도체 소자의 유효 채널길이가 0.3㎛ 미만으로 감소함으로 인하여 금속 배선을 연결하기 위한 콘택 홀의 크기 또한 0.5㎛ 이하로 축소하게 되었다. 또한 반도체 소자가 점점 고집적화되어 감에 따라 반도체 소자의 배선 공정에서 반도체 장치의 동작속도를 빠르게 하기 위하여 저항률이 60μΩ-cm 보다 낮은 5.5μΩ-cm 정도의 저항률을 갖는 텅스텐 막이 사용된다.As semiconductor devices have been highly integrated, the effective channel length of semiconductor devices has been reduced to less than 0.3 μm, thereby reducing the size of contact holes for connecting metal wires to 0.5 μm or less. In addition, as semiconductor devices are increasingly integrated, a tungsten film having a resistivity of about 5.5 μΩ-cm, which is lower than 60 μΩ-cm, is used to increase the operating speed of the semiconductor device in the wiring process of the semiconductor device.

그러나, 콘택 홀의 크기가 0.5㎛ 이하로 축소됨에 따라 기존의 알루미늄의 전자이동을 방지하기 위하여 구성된 Al+Si+Cu 함금막에 의한 금속 배선 형성시에 단선 불량 또는 접속불량을 일으키는 원인이 되었다.However, as the size of the contact hole is reduced to 0.5 μm or less, it causes a disconnection failure or connection failure when metal wiring is formed by the Al + Si + Cu alloy film, which is configured to prevent electron transfer of existing aluminum.

이를 해결하기 위하여, 종래에는 다음과 같은 방법을 사용하였다.In order to solve this problem, the following method was conventionally used.

우선, 제1도에 도시된 바와 같이, 반도체 기판(1)내에 불순물, 예를들면 고농도의 As 원자를 이온 주입하여 N+영역(2)을 형성한 후, 소정의 절연막(3)을 도포한다. 절연막(3)을 통상의 사진 및 식각 공정을 통하여 식각하여 콘택 홀(도시되지 아니함)을 형성하고 그 위에 화학 증착법을 이용하여 선택적인 텅스텐 막(4)을 형성한다.First, as shown in FIG. 1, impurities, for example, high concentrations of As atoms are ion-implanted into the semiconductor substrate 1 to form the N + region 2, and then a predetermined insulating film 3 is applied. . The insulating film 3 is etched through a conventional photographic and etching process to form a contact hole (not shown), and an optional tungsten film 4 is formed thereon by chemical vapor deposition.

그런데, 이와 같이 화학증착법을 이용하여 텅스텐 막을 증착시킬 경우, 반응가스로 주로 WF6-H2의 가스나 WF6-SiH4-H2반응계를 사용하고 있는데, 반응가스중 WF6가스의 환원 반응에서 발생하는 F원자들에 의해서, 실리콘, 산화막 및 산화막/실리콘 계면에서 침식이 일어나므로, 텅스텐이 산화막/실리콘 계면으로 파고 들어 가거나, 실리콘 기판내부, 즉 N+영역(2)으로 침투하여, 파괴를 일으키므로써, 누설전류가 높아지고, 전선의 단락현상이 발생하며 절연파괴 전압이 낮아지게 되는 등의 여러가지 문제점이 있었다.However, in the case of depositing a tungsten film by chemical vapor deposition as described above, a reaction gas of WF 6 -H 2 or WF 6 -SiH 4 -H 2 is mainly used as a reaction gas, and the reduction reaction of WF 6 gas in the reaction gas is performed. Since erosion up in, a silicon oxide film and the oxide film / silicon interface by the F atom generated by, tungsten go, buckling the oxide film / silicon interface, to penetrate into the silicon substrate interior, i.e., N + region 2, destruction This causes various problems such as high leakage current, short circuit of wires, and low breakdown voltage.

본 발명은 상기 문제점을 해결하기 위하여, WF6가스가 콘택 홀의 하부에 형성된 확산 영역과 직접 접촉하는 것을 배제함으로써 확산 영역의 파괴를 방지할 수 있는 금속 배선 방법을 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION In order to solve the above problem, an object of the present invention is to provide a metal wiring method capable of preventing the destruction of the diffusion region by excluding the WF 6 gas from directly contacting the diffusion region formed under the contact hole.

따라서, 본 발명은 상기 목적을 달성하기 위하여, 반도체 기판에 확산 영역 및 절연막을 형성한 후, 배선용으로 텅스텐 막을 형성하는 반도체 소자의 제조 방법에 있어서, 반도체 기판상부에 절연막을 형성한 후, 절연막을 사진 및 식각 공정으로 식각하여 콘택 홀을 형성하고나서, Ti 막 및 TiN 막을 전체 구조의 상부에 형성하고 콘택 홀의 요홈에 소정의 절연막으로 매립하고, 블랭키트 식각하여 노출하여 Ti 막 및 TiN 막을 제거하며, 요홈부위의 절연막을 제거하고나서 선택적인 텅스텐 막을 형성하는 금속 배선 방법을 제공하는 것을 특징으로 한다.Accordingly, in order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device in which a diffusion region and an insulating film are formed on a semiconductor substrate, and a tungsten film is formed for wiring, wherein the insulating film is formed on the semiconductor substrate. After etching the photolithography and etching process to form the contact hole, the Ti film and the TiN film are formed on the upper part of the entire structure, and are embedded in the grooves of the contact hole with a predetermined insulating film. And a metal wiring method of forming a selective tungsten film after removing the insulating film at the groove portion.

이하, 첨부도면에 의거하여 본 발명의 일 실시예를 상세히 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

우선, 제2(a)도에 도시된 바와 같이 반도체 기판(11)내부에 불순물, 예를 들면 소정 농도의 As 원자를 도핑시켜 확산 영역, 예를 들면 N+영역(12)을 형성한 후, 소정의 절연 산화막(13) 및 질화막(14)을 각각 형성한다. 여기서, 특히 질화막(14)의 두께는 약 300∼500Å 정도이다.First, as shown in FIG. 2A, a dopant, for example, an As atom having a predetermined concentration, is doped into the semiconductor substrate 11 to form a diffusion region, for example, an N + region 12. Predetermined insulating oxide films 13 and nitride films 14 are formed, respectively. In particular, the thickness of the nitride film 14 is about 300 to 500 kPa.

이어서, 이 절연 산화막(13) 및 질화막(14)을 사진 식각법으로 식각하여 콘택홀(15)을 형성한다.Subsequently, the insulating oxide film 13 and the nitride film 14 are etched by a photolithography method to form the contact hole 15.

그 다음, 제2(b)도에 도시된 바와 같이 콘택홀(15)의 하부 및 측벽과 질화막(14)상부에 약 300Å 정도의 Ti 막(16) 과 약 600Å 정도의 TiN 막(17)을 순차적으로 스퍼터링 법으로 적층한다. 여기서 Ti 막(16) 과 TiN 막(17)을 콘택홀(15)의 하부 및 측벽과 질화막(14)상부에 형성하는 것은 텅스텐 막이 WF6와 H2가스의 화학반응에 의하여, 노출된 반도체 기판에 형성될 때에 WF6가스의 환원 반응으로 반도체 기판에 영향을 주어 N+영역(12)의 파괴시키는 것을 방지하기 위함이다.Next, as shown in FIG. 2 (b), a Ti film 16 of about 300 mW and a TiN film 17 of about 600 mW are disposed on the lower portion and sidewall of the contact hole 15 and on the nitride film 14. Lamination | stacking is carried out by the sputtering method sequentially. In this case, the Ti film 16 and the TiN film 17 are formed on the lower portion of the contact hole 15 and on the sidewalls and the nitride film 14 by exposing the tungsten film to the semiconductor substrate exposed by the chemical reaction between WF 6 and H 2 gas. This is to prevent the breakdown of the N + region 12 by affecting the semiconductor substrate by the reduction reaction of the WF 6 gas when formed at.

그리고나서, TEOS 산화막(18)을 약 3000∼10000Å 정도의 두께로 TiN 막(17)상부에 증착시킨다.Then, the TEOS oxide film 18 is deposited on the TiN film 17 to a thickness of about 3000 to 10000 Pa.

여기서 TEOS 산화막(18)대신에 SOG 막, 폴리아미드 막 등을 사용할 수 있다.Instead of the TEOS oxide film 18, an SOG film, a polyamide film or the like can be used.

그 다음, 제2(c)도에 도시된 바와 같이, TEOS 산화막(18)을 CF4, CHF3, Ar 가스를 사용하여 비등방성 블랭킷 식각을 하여, TiN막(17)을 노출시킨 다음, 요홈부위에 헝성된 TEOS 산화막(18)을 식각 방지막으로 하여 TiN막(17) 및 Ti막(16)을 Cl2, He 가스로 블랭킷 식각하여 질화막(14)을 노출시킨다.Then, as shown in FIG. 2 (c), the TEOS oxide film 18 is anisotropic blanket etched using CF 4 , CHF 3 , and Ar gas to expose the TiN film 17, and then the recesses The nitride film 14 is exposed by blanket etching the TiN film 17 and the Ti film 16 with Cl 2 , He gas using the TEOS oxide film 18 formed on the site as an etch stop film.

이어서, 질화막(14), TiN막(17) 및 Ti 막(16)을 식각 저지 장벽으로 하여, HF 또는 HF+NH4F 용액에 의해 TEOS 산화막(18)을 제거한 다음, 노출된 TiN 막(17)상부에 WH6+ H2, WF6+SiH4, 또는 WF6+ SiH2Cl2가스를 사용하여 선택적인 텅스텐 막((19)을 형성한다. 만일, TEOS 산화막(18)을 플라즈마에 의한 건식식각법으로 제거하게 되면 질화티타늄(17)에 식각손상이 발생하여 배선의 저항이 증가하는 문제점이 생길 수 있다.(제2(d)도 참고 )Subsequently, the nitride film 14, the TiN film 17 and the Ti film 16 are used as an etch stop barrier to remove the TEOS oxide film 18 by HF or HF + NH 4 F solution, and then the exposed TiN film 17 A tungsten film 19 is formed by using WH 6 + H 2 , WF 6 + SiH 4 , or WF 6 + SiH 2 Cl 2 gas on the top. If the TEOS oxide film 18 is If it is removed by dry etching, etching damage may occur in the titanium nitride 17, which may cause a problem in that the resistance of the wiring is increased.

본 발명에 의하면, 콘택홀 내부에만 Ti 막 및 TiN 막을 남게 하여 텅스텐막을 선택적으로 용이하게 증착하므로써, 반도체 소자의 단선 불량이나, 접속 불량이 방지될 수 있다.According to the present invention, by selectively depositing the tungsten film by leaving the Ti film and the TiN film only inside the contact hole, the disconnection failure or the connection failure of the semiconductor element can be prevented.

Claims (6)

반도체 기판에 확산영역을 형성하고, 절연막을 형성한 후 텅스텐 플러그를 형성하는 반도체 장치의 제조 방법에 있어서, 반도체 기판내부에 불순물을 주입하여, 확산영역을 형성하고 절연 산화막 및 질화막을 형성하는 단계; 콘택홀을 형성하여 확산영역을 노출시키는 단계; 티타늄막, 질화티타늄막, 및 절연막을 순차적으로 형성하는 단계; 상기 절연막을 블랭킷 식각하는 단계; 상기 티타늄막 및 질화티타늄막을 블랭킷 식각하는 단계; 상기 절연막 습식으로 제거하는 단계 ;및 선택적인 텅스텐막을 형성하는 단계로 이루어지는 것을 특징으로 반도체 장치의 제조 방법.A method of manufacturing a semiconductor device, the method comprising: forming a diffusion region in a semiconductor substrate, forming an insulating film, and then forming a tungsten plug, the method comprising: implanting impurities into a semiconductor substrate to form a diffusion region and forming an insulating oxide film and a nitride film; Forming a contact hole to expose the diffusion region; Sequentially forming a titanium film, a titanium nitride film, and an insulating film; Blanket etching the insulating film; Blanket etching the titanium film and the titanium nitride film; Wet removing the insulating film; and forming an optional tungsten film. 제1항에 있어서, 상기 질화막의 두께는 300~500Å인 것을 특징으로 반도체 장치의 제조 방법.The method of manufacturing a semiconductor device according to claim 1, wherein the nitride film has a thickness of 300 to 500 kPa. 제1항 또는 제2항에 있어서, 상기 절연막은 TEOS 산화막, SOG 막 또는 폴리아미드막인 것을 특징으로 하는 반도체 장치의 제조 방법.The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the insulating film is a TEOS oxide film, an SOG film, or a polyamide film. 제1항 또는 제2항에 있어서, 상기 절연막을 블랭킷 식각할 때에 CF4, CHF3, Ar 가스를 사용하여 질화티타늄막을 노출시키는 것을 특징으로 반도체 장치의 제조 방법.The semiconductor device manufacturing method according to claim 1 or 2, wherein the titanium nitride film is exposed using CF 4 , CHF 3 , Ar gas when the insulating film is blanket-etched. 제1항 또는 제2항에 있어서, 상기 티타늄막 및 질화티타늄막을 블랭킷 식각할 때에 Cl2, He 가스를 사용하여 질화막을 노출시키는 것을 특징으로 반도체 장치의 제조 방법.The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the nitride film is exposed using Cl 2 , He gas when blanket etching the titanium film and the titanium nitride film. 제1항 또는 제2항에 있어서, 상기 선택적인 텅스텐막을 형성할 때에 WF6+ H2, WF6+SiH4, 또는 WF6+SiH2Cl2가스중 어느 하나를 사용하는 것을 특징으로 반도체 장치의 제조 방법.The semiconductor device according to claim 1 or 2, wherein any one of WF 6 + H 2 , WF 6 + SiH 4 , or WF 6 + SiH 2 Cl 2 gas is used to form the selective tungsten film. Method of preparation.
KR1019940035698A 1994-12-21 1994-12-21 Method for forming tungsten plug KR100290769B1 (en)

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KR1019940035698A KR100290769B1 (en) 1994-12-21 1994-12-21 Method for forming tungsten plug

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KR960026171A KR960026171A (en) 1996-07-22
KR100290769B1 true KR100290769B1 (en) 2001-06-01

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