KR100289098B1 - Device for integrally processing interrupt signal - Google Patents

Abstract

PURPOSE: A device for integrally processing an interrupt signal is provided to embody a miniaturization and a simplification of a system totally by integrating interrupt signals being applied from an IC(Integrated Circuit) and outputting the interrupt signals as one signal. CONSTITUTION: An interrupt generating detecting unit detects interrupt signals being applied from a plurality of ICs(10a-10n) and outputs a detection signal. If the detection signal is applied from the interrupt generating detecting unit, a flag creation unit sets a flag corresponded to the ICs(10a-10n) which generated the corresponding interrupt. If a flag clear signal is applied, the flag creation unit clears the corresponding flag. If the flag of the flag creation unit is set, an interrupt creating unit generates and outputs an interrupt signal. If the flag of the flag creation unit is cleared, the interrupt creating unit stops a generation of an interrupt signal. A CPU interface unit has flag set information of the flag creation unit and interrupt information applied from the ICs(10a-10n) and supplies information according to the ICs(10a-10n) which generated an interrupt to a processor. If the processor accesses the CPU interface unit, a reset pulse creating unit generates a flag clear signal and applies the signal to the flag creation unit.

Description

Interrupt signal processor

The present invention relates to an integrated interrupt signal processing apparatus that can realize miniaturization and simplification of the system as a whole by integrating and outputting an interrupt signal applied from ICs mounted in multiple units into a single signal.

In general, what interrupts are in the system. When an interrupt signal is applied, it stops the normal execution of the system or routine, executes the interrupt service routine corresponding to the interrupt signal, and executes again from where it was interrupted. At this time, the interrupt signal is one of the more powerful control signals that manage the input / output operation of the central computer and peripheral system, which is used to request immediate attention of the central computer. To be sent to a specific address associated with External interrupts additionally synchronize the state of the computer program and subsystem devices, and indicate an error condition that occurred in the peripheral system. An internal interrupt synchronizes the end of the input / output transfer with the computer program.

In addition, the interrupt service routine refers to a program or a special routine designed to handle an interrupt. The interrupt service routine stores a current state of a processor on a stack and performs an actual work required by an interrupt in response to an interrupt request. In addition, when the interrupt service operation is completed, the processor can restore the state stored in the processor to continue the interrupted program.

On the other hand, conventionally, as shown in the accompanying drawings, Figure 1, when n ICs are mounted in one unit, and one interrupt is generated from each IC, n interrupt signals are all sent to the processor side in one unit. Delivered.

Thus, the processor accesses the interrupted IC to check the cause of the interrupt and executes the corresponding interrupt service routine.

As described above, conventionally, when n ICs are mounted in one unit, n interrupt signals are generated, and when m units are installed in the system, all of m x n interrupt signals can be processed. Since this must be configured, the circuit of the system becomes complicated and there is a problem that maintenance is not easy.

The present invention has been drawn in view of the above-described problems, by integrating and outputting an interrupt signal applied from ICs installed in multiple units into a single signal, an interrupt capable of miniaturizing and simplifying the system as a whole. It is an object to provide a signal integrated processing device.

1 is a diagram showing generation of an interrupt signal in each conventional IC.

2 is a block diagram showing an interrupt signal integration processing scheme according to the present invention;

FIG. 3 is a detailed configuration diagram of the interrupt signal integrating apparatus shown in FIG. 2.

Explanation of symbols on the main parts of the drawings

10a ~ 10n: IC (Integrated Circuit) 20: Interrupt signal integrated processing device

21: interrupt generation detection unit 22: flag generation unit

23: interrupt generation unit 24: CPU interface unit

25: reset pulse generator

In order to achieve the above object, the present invention provides an interrupt signal integrating processing apparatus, comprising: an interrupt generation detecting unit for detecting interrupt signals applied from a plurality of ICs and outputting detection signals; A flag generator for setting a flag corresponding to the IC in which the interrupt is generated when a detection signal is applied from the interrupt generation detector, and clearing the flag when a flag clear signal is applied; An interrupt generator for generating and outputting an interrupt signal when a flag of the flag generator is set, and stopping generation of an interrupt signal when a flag of the flag generator is cleared; A CPU interface unit having flag set information of the flag generation unit and interrupt information applied from the respective ICs, and providing information on the IC on which an interrupt has been generated to a processor side; And a reset pulse generation unit for generating a flag clear signal and applying the flag clear signal to the flag generation unit when the processor accesses the CPU interface unit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Interrupt signal integration processing scheme according to the present invention is as shown in Figure 2 attached. That is, the interrupt signal integrated processing device 20 is configured to receive the interrupt signals from the plurality of ICs 10a to 10n and process the integrated signals.

Meanwhile, as shown in FIG. 3, the interrupt signal integrated processing device 20 includes an interrupt generation detector 21, a flag generator 22, an interrupt generator 23, and a CPU interface 24. And a reset pulse generator 25.

The interrupt generation detection unit 21 detects whether an interrupt signal is applied from a plurality of ICs 10a to 10n, and outputs a detection signal to the flag generation unit 22 when an interrupt signal is detected. When a detection signal is applied from the interrupt generation detection unit 21, the flag generation unit 22 sets a flag corresponding to the ICs 10a to 10n where the interrupt is generated, and sets the flag from the reset pulse generation unit 25. If a clear signal is applied, the flag is cleared.

The interrupt generator 23 generates and outputs an interrupt signal when the flag is set from the flag generator 22, and stops generating the interrupt signal when the flag is cleared. The CPU interface unit 24 has flag set information of the flag generation unit 22 and interrupt information supplied from each of the ICs 10a to 10n, and information on the ICs 10a to 10n where an interrupt has been generated to the processor. To provide. When the processor accesses the CPU interface unit 24, the reset pulse generation unit 25 generates a flag clear signal and applies it to the flag generation unit 22 side.

The operation of the present invention configured as described above will be described in detail with reference to the accompanying drawings.

For example, when an interrupt occurs in IC1 10a, the interrupt signal is input to the interrupt signal integrated processing device 20. The interrupt generation detection unit 21 in the interrupt signal integrated processing unit 20 checks whether an interrupt signal is applied. Since the interrupt signal is applied from the IC1 10a, the detection signal is transmitted to the flag generation unit 22. The flag generator 22 sets the flag. Thereafter, the flag generator 22 applies the set flag information to the interrupt generator 23 so that the interrupt generator 23 generates an interrupt signal and applies it to the processor. At this time, the processor recognizes that the interrupt has occurred in the ICs 10a to 10n due to the interrupt signal being applied from the interrupt generator 23, and then accesses the CPU interface unit 24 to which IC 10a to 10n. The CPU interface unit 24 is checked to detect whether an interrupt has occurred. At this time, the CPU interface unit 24 has the flag generation information and the current information of the interrupt. The processor recognizes that the interrupt is generated in the IC1 10a by accessing the CPU interface unit 24, and the corresponding IC1. The interrupt service routine for (10a) is executed. At this time, when the processor outputs a read signal to access the CPU interface unit 24, the reset pulse generation unit 25 monitors the read signal output from the processor, thereby allowing the process to execute the corresponding CPU interface unit. Recognizing that 24 is accessed, a flag clear signal is generated and applied to the flag generator 22 side. Thus, by clearing the flag, the interrupt generator 23 no longer generates an interrupt signal.

In other words, if any interrupt signal is generated from a plurality of ICs 10a to 10n mounted inside any unit, the corresponding flag in the flag generation section 22 is set and is interrupted by the interrupt generation section 23. An interrupt signal is generated. In response, the processor recognizes that an interrupt has occurred, and accesses the CPU interface unit 24 to check the ICs 10a to 10n where the interrupt has occurred. Thereafter, when the processor accesses the CPU interface unit 24, the flag is automatically cleared by the reset pulse generation unit 25.

As described above, the present invention integrates a plurality of interrupt signals applied from ICs mounted in a plurality of units to form a single signal, thereby realizing miniaturization and simplicity of the system as a whole.

Claims (1)

An interrupt signal integrating process for processing interrupts, comprising: an interrupt generation detector (21) for detecting interrupt signals applied from a plurality of ICs (10a to 10n) and outputting detection signals; A flag generator for setting a flag corresponding to the ICs 10a to 10n where the interrupt is generated when a detection signal is applied from the interrupt generating and discharging unit 21, and clearing the flag when a flag clear signal is applied ( 22); An interrupt generator (23) which generates and outputs an interrupt signal when the flag of the flag generator (22) is set, and stops the generation of the interrupt signal when the flag of the flag generator (22) is cleared; CPU which has flag set information of the flag generation section 22 and interrupt information applied from each of the ICs 10a to 10n and provides information on the ICs 10a to 10n where an interrupt has been generated to a processor side. An interface unit 24; And a reset pulse generator (25) for generating a flag clear signal and applying it to the flag generator (22) when the processor accesses the CPU interface (24).

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