KR0128714Y1 - Keyboard connection device - Google Patents

Abstract

According to the present invention, in the keyboard connecting device, when the keyboard is connected to the main board, the keyboard cannot be connected to the main board when the component arrangement area of the main board is so small that the keyboard connection processor cannot be used. When only the key data applied from the keyboard is detected and transferred to the CPU side, there is a problem that the processor for keyboard connection becomes unnecessary.

The present invention can be connected to the keyboard even if the keyboard is not provided in the main board for connecting the keyboard, it can be effectively applied to a variety of systems that need to connect the keyboard.

Description

Keyboard interface

1 is a view for explaining a conventional keyboard connection method.

2 is a block diagram of a keyboard connection device according to the present invention.

Figure 3 is a waveform diagram for explaining the operation of the keyboard connection device according to the present invention.

* Explanation of symbols for main parts of the drawings

30: keyboard connection device 31: data detection unit

32: data enable part 33: shift register

34: CPU connection part 35: parity error detection part

36: frame error detection unit 37: overflow detection unit

38: interrupt unit 39: OR gate

The present invention relates to a keyboard connection device, and more particularly, to a keyboard connection device for connecting a keyboard even without a keyboard connection processor for processing and outputting serial data applied from the keyboard.

Conventionally, when the keyboard is connected to a predetermined main board, the keyboard is configured as shown in FIG. The main board 10 includes an interrupt controller 11, an I / O port 12, and a processor 13, and the keyboard 20 includes a processor 21 and a ROM 22. The processor 21 of the keyboard 20 retrieves the corresponding key data KBDAT from the ROM 22 in response to a key input and outputs it to the motherboard 10 side. The processor 13 of the motherboard 10 receives the key data DBDAT and the clock KBCLK from the keyboard 20. When the key data KBDAT is applied from the keyboard 20, the interrupt controller 11 receives the key data KBDAT. At the same time, a control signal is output to the side, and key data (KBDAT) is processed and output to the I / O port 12 side in parallel. At this time, the interrupt control unit 11 outputs an interrupt signal to the CPU in the main board 10 according to a control signal applied from the processor 13 to notify the CPU that data has been input from the keyboard 20. The / O port 12 displays on the monitor a letter or number corresponding to the data applied in parallel from the processor 13.

When the keyboard 20 is connected to the motherboard 10 in the conventional manner, processors 13 and 21 must be provided on both the keyboard 20 and the motherboard 10. Using the conventional method, there is a problem that the keyboard 20 cannot be connected to the motherboard 10 when the component placement area on the motherboard 10 is so small that the processor 13 cannot be used. In the case where only key data applied from 20) is detected and transferred to the CPU side, the processor 13 becomes unnecessary.

The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a keyboard connecting device that enables a keyboard to be connected even if a keyboard for connecting the keyboard is not provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a configuration diagram of a keyboard connection device according to the present invention, Figure 3 is a waveform diagram for explaining the operation of the keyboard connection device according to the present invention.

Keyboard connection device 30 according to the present invention is a data detection unit 31, a data enable unit 32, a shift register 33, a CPU connection unit 34, a parity error detection unit 35 as shown in FIG. ), A frame error detector 36, an overflow detector 37, an interrupter 38, and an OR gate 39. The data detector 31 detects the data KBDAT and the clock KBCLK applied from the keyboard, outputs the data to the shift register 33, and outputs the clock to the data enable unit 32 and the OR gate ( To 39). The data enable unit 32 operates in accordance with the applied clock CLK1 and the clock received from the data detector 31, so that the data load clock DLCK (DataCK) is applied to the parity detector 35 and the frame error detector 36. At the same time as outputting the load clock, the data input signal DTI is outputted to the overflow detector 37 side, and the clock enable signal CLKEN is outputted to the OR gate 39 side. The shift register 33 outputs data applied from the data detection unit 31 to the CPU connection unit 34 in parallel with the clock from the OR gate 39, and outputs parity bits PAB in the data. It outputs to the error detection part 35 side, and outputs the stop bit which shows the end of the frame of the said data to the frame error detection part 36 side. The CPU connection section 34 outputs data applied in parallel from the shift register 33 to the corresponding CPU side in accordance with the chip select signal CS from the CPU (not shown in the figure). When the data load clock DLCLK is applied from the data enable unit 32, the parity error detection unit 35 receives the parity bit PAB and data from the shift register 33 and checks the parity to generate a parity error. Notify the CPU. The frame error detection unit 36 checks whether or not a frame error has occurred according to the data load clock DLCLK from the data enable unit 32 and the stop bit STB from the shift register 33, and checks the corresponding signal for CPU. Output to the side. The overflow detection unit 37 checks whether or not the data overflows according to the data input signal DTI from the data enable unit 32 and the chip select signal CS from the CPU, and sends the corresponding signal to the CPU side. Output The interrupt unit 38 outputs an interrupt signal for notifying that the data has been input in accordance with the data input signal DTI from the data enable unit 32 and the chip select signal CS from the CPU. The OR gate 39 logically combines the clock applied from the data detection unit 31 with the clock enable signal CLKEN applied from the data enable unit 32 and supplies it as a clock to the shift register 33 side.

Such a keyboard connection device 30 of the present invention operates as follows.

When the clock KBCLK and data (KBDA data detection unit 31) of the form shown in FIG. 3 are applied from the keyboard, the data detection unit 31 detects the corresponding clock and data and transfers the data to the shift register 33. And outputs the clock to the data enable unit 32 and the OR gate 39. At this time, the data enable unit 32 provides a low level clock enable signal to the OR gate 39 side. (CLKEN) is output, and the OR gate 39 generates a clock obtained by ORing the low level clock enable signal CLKEN applied from the data enable unit 32 and the clock from the data detector 31. The shift register 33 receives 11-bit data serially applied from the data detector 31 in accordance with the clock from the OR gate 39. The shift register 33 receives 8-bit data. Converted in parallel and outputted to the CPU connection part 34 side, an error Parity bits for the size (PAB) is the stop bit (STB) represents the output to a parity error detector (35) side, and the frame end is outputted to the frame error detector 36 side.

The above operation is performed when the interrupt unit 38 outputs an interrupt to the CPU side. The interrupt unit 38 is configured such that the data input signal DTI applied from the data enable unit 32 is low level to high level. By outputting an interrupt signal to the CPU side at the time of changing to (i.e., when all 11 bits of data have been input), the CPU outputs a chip select signal CS to the CPU connection portion 34, from the CPU connection portion 34. Read data from. The data enable unit 32 receives the clocks from the clock CLK1 and the data detector 31 so that the data input signal DTI and the data load clock DLCLK when the data and the clock of one frame are inputted. The parity error detector 35, the frame error detector 36, and the overflow detector 37 perform an error check operation by converting the output from the low level to the high level. The parity error detection unit 35 receives a data load clock DLCLK (change from low level to high level) applied from the data enable unit 32 when data input of one frame is finished, and then the shift register 33 By checking data and parity bit (PAB) from), it checks the error by checking odd parity and reports the error check result to CPU side.If an error occurs, a high level parity error signal is sent to CPU side. Output The frame error detection unit 35 uses the fact that the stop bit (STB) at the end of the one-frame data applied from the keyboard is always at a high level so that the data load clock DLCLK from the data enable unit 32 is low. When the stop bit (STB) is read from the shift register 33 when it changes from the level to the high level, if the corresponding stop bit (STB) is high level, it is determined to be normal and the corresponding stop bit (STB) is low. In the case of a level, a frame error signal is output to the CPU side. In addition, the overflow detection unit 37 checks whether the data overflows when the data input signal DTI applied from the data enable unit 32 is changed from the low level to the high level, and reports it to the CPU side. do.

When the keyboard connection device 30 of the present invention is installed on the main board to which the keyboard is connected, the data applied from the keyboard can be transferred to the CPU side of the main board.

As described above, the present invention can be connected to the keyboard even if the keyboard is not provided in the main board for connecting the keyboard, it can be effectively applied to various systems that need to connect the keyboard.

Claims (1)

In the keyboard connecting apparatus, the data detection unit 31 for detecting and outputting a data and a clock applied from a keyboard, the data input signal DTI in accordance with the applied clock CLK1 and the clock from the data detection unit 31. A data enable unit 32 for outputting a data load clock DLCLK and a clock enable signal CLKEN, a clock from the data detector 31 and a clock in from the data enable unit 32; OR gate 39 for outputting a clock obtained by ORing the enable signal CLKEN, and shift register 33 for receiving and outputting data from the data detection unit 31 according to the clock from the OR gate 39. ), The CPU connection part 34 which outputs the data applied from the shift register 33 to the CPU side according to the chip select signal CS from the CPU, and the data from the data enable part 32. Depending on the load clock (DLCLK) Parity detection unit 35 and data enable unit 32 which receive data and a parity bit from the shift register 33 and check whether a parity error has occurred and output a check result signal to the SPU. The frame error detection unit 36 which checks whether a frame error has occurred according to the data load clock DLCLK and the stop bit STB from the shift register 33, and outputs a check result signal to the CPU; An overflow detection unit for checking whether the data overflows according to the data input signal DTI from the enable unit 32 and the chip select signal CS from the CPU, and outputting a check result signal to the CPU side ( 37) an interrupt unit 3 for generating an interrupt signal according to the data input signal DTI from the data enable unit 32 and the chip select signal CS from the CPU and outputting the interrupt signal to the CPU side 3; Keyboard connection device comprising a).