KR100285311B1 - Initial Clock Stabilization Supply - Google Patents

Abstract

end. FIELD OF THE INVENTION The invention described in the claims can be used in an exchanger having a plurality of central processing units.

I. SUMMARY OF THE INVENTION An object of the present invention is to provide an initial clock stabilization supply capable of supplying a stabilized clock to a slave mode control unit that sets any central processing unit among a plurality of central processing units as a slave central processing unit.

All. Summary of the Invention Solution of the Invention: A clock generator for generating a clock having a first frequency, a clock generator for generating a clock having a first frequency, a buffer for buffering and outputting the clock, and Buffer control unit for generating and outputting a control signal for enabling and disabling the buffer, and slave mode for setting and outputting a slave mode bit for setting a slave CPU according to a counting result of a clock input through the buffer. Characterized in that it consists of a control unit.

la. Important use of the invention: Can be used in private exchanger.

Description

Initial Clock Stabilization Supply

The present invention relates to a system having a plurality of CPUs, such as a private exchanger, and more particularly, to an initial clock stabilization supply device for stabilizing and supplying a clock required for setting a slave CPU during system initial operation.

When configuring a system using a plurality of processors such as a private exchange, a plurality of provided CPUs should be divided into a master and a slave. In this case, there is a condition for distinguishing the master CPU and the slave CPU, which will be described with reference to FIG. 1 as follows.

First, FIG. 1 illustrates a system configuration diagram illustrating a master / slave CPU setting process in a system having a plurality of CPUs. In FIG. 1, the clock generator 100 generates and outputs a clock having a predetermined frequency. This clock is supplied to the first CPU 200 and the second CPU 300 as a main clock and used to provide synchronous timing for system operation. The main clock may be input to the slave mode control unit 500. The slave mode controller 500 sets the second CPU 300 as a slave CPU by counting an input main clock and setting a slave mode bit when the counting value satisfies a preset condition. In this case, the first CPU 200 becomes a master CPU.

Hereinafter, when the slave mode controller 500 sets the slave mode bit according to a preset condition, the slave mode controller 500 resets the reset signal input from the power on reset circuit 400 to " Keep the slave mode bit in ″ high ″ state for more than 32 clocks while remaining low. In order to set the second CPU 300 as the slave CPU, the slave mode bit in the ″ high ″ state must be set to the ″ low ″ state at least before 512 clocks. However, it takes 10 to 20 msec for the main clock to stabilize after power is turned on. In this way, the main clock is supplied to the slave mode control unit 500 before the main clock is stabilized. There is a problem that the mode bit cannot be set normally.

Accordingly, an object of the present invention is to provide an initial clock stabilization supply device that can normally set a slave central processing unit (CPU) at the initial operation of a system having a plurality of central processing units (CPU).

Another object of the present invention is to stabilize the initial clock that can supply a stabilized clock to the slave mode control unit for setting any of the CPUs of the plurality of CPUs to the slave CPU (CPU) In providing a supply device.

The present invention for achieving the above object is in the initial clock stabilized supply of a system having a plurality of central processing units (CPU),

A clock generator for generating a clock having a first frequency;

A buffer for buffering and outputting the clock;

A buffer control unit for generating and outputting a control signal for enabling and disabling the buffer;

According to the counting result of the clock input through the buffer characterized in that the slave mode control unit for setting and outputting the slave mode bit for setting the slave CPU.

1 is a system configuration diagram illustrating a master / slave CPU setting process in a system having a plurality of central processing units (CPUs).

Figure 2 is a block diagram of the initial clock stabilized supply according to an embodiment of the present invention.

Hereinafter, an operation according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Figure 2 shows the configuration of the initial clock stabilization supply apparatus according to an embodiment of the present invention. Referring to FIG. 1, the clock generator 100 first generates and outputs a main clock having a first frequency. In this case, the first frequency is a value that can vary according to system specifications. The buffer 600 connected to the output terminal of the clock generator 100 is enabled and disabled according to the logic state of the enable signal output from the power-on detection and buffer control unit 700. Delays the output of the main clock. The first CPU 200 and the second CPU 300 control various operations of the system by outputting various control commands synchronized with the input main clock. The second CPU 300 is set to the slave CPU according to whether the slave mode bit is set. The power-on reset circuit 400 initializes each part of the system by outputting a reset signal in response to the reset command input. The slave mode control unit 500 counts the main clock input through the buffer 600 and sets the slave mode bit for setting the slave CPU to a low state according to the counting result. The power on detection and buffer control unit 700 generates and outputs a control signal for enabling and disabling the buffer 600. For example, the power-on detection and buffer control unit 700 maintains the buffer 600 enable signal in a ″ high ″ state for a predetermined time immediately after the power-on and outputs the ″ low ″ state. For the predetermined time, the time required for stabilizing the main clock output from the clock generator 100 may be set to a value (defined as 100 msce in the following description).

Hereinafter, the operation of the initial clock stabilization supply having the above-described configuration will be described. First, when the power of the system having the configuration of FIG. 2 is ″ ON ″, the clock generator 100 generates and starts outputting the main clock necessary for driving the system. do. The power-on detection and buffer control unit 700 maintains the buffer enable signal in the high state for a preset time (100 msec) upon outputting the power on, and outputs the low-low state. Accordingly, in the buffer 600, the stabilized main clock is output from the buffer enable signal being input in the ″ low ″ state. As such, the main clock whose output is delayed for a predetermined time is then inputted to the first CPU 200, the second CPU 300, and the slave mode controller 500, and the slave mode controller 500 counts the input main clock. The second CPU 300 can be set as a slave CPU by setting and outputting a slave mode bit in a ″ low ″ state according to the counting result.

As described above, according to the present invention, a more stable clock can be supplied to each part of the system by supplying the main clock outputted from the clock generator after a delay for a predetermined time at the time of system initial start-up, whereby the slave CPU can be stably achieved. There is an advantage.

Claims (2)

In the initial clock stabilized supply of a system comprising a plurality of CPUs, A clock generator for generating a clock having a first frequency; A buffer for buffering and outputting the clock; A buffer control unit for generating and outputting a control signal for enabling and disabling the buffer; And a slave mode control unit configured to set and output a slave mode bit for setting a slave CPU according to a counting result of a clock input through the buffer. The initial clock stabilization supply apparatus according to claim 1, wherein the buffer control unit enables the buffer for a predetermined time after the initial driving of the system.