KR19990039628A - Semiconductor Memory Device with High Frequency Clock Generator for Delayed Lock Loop Circuit Test - Google Patents

Abstract

Disclosed are a semiconductor memory device capable of testing a delayed lock loop circuit even with test equipment having a low operating frequency. The semiconductor memory device may include a delay lock loop circuit for removing skew between data and a control signal for selecting one of a system clock and a high frequency clock in response to a wafer test enable signal to control the delay lock loop circuit. And a high frequency clock generator configured to receive the system clock and generate the high frequency clock in response to the wafer test enable signal. In particular, the controller selects the high frequency clock when the wafer test enable signal is activated and outputs it as a control signal for controlling the delay lock loop circuit.

Description

Semiconductor memory device with high frequency clock generator for delay lock loop circuit test

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor memory device capable of testing a delayed lock loop (DLL) even with test equipment having a low operating frequency.

In semiconductor memory devices, new products continue to be developed due to the demand for low power and high speed of PCs or workstations. Therefore, unlike conventional DRAM, a new concept of Synchronous DRAM (SDRAM), which operates in synchronization with the system clock, has emerged.

Double Data Rate (DDR) synchronous DRAM was developed to realize a faster operating frequency in synchronous DRAM. It is able to input and output two data during one clock, and has an operating frequency more than twice that of the conventional synchronous DRAM. In particular, in order to smoothly input and output two data in one clock in a DDR synchronous DRAM, it is preferable to remove skew between data, and a DLL is used to solve this problem. However, in order to test a semiconductor device using a DDR synchronous DRAM or other DLL, the test equipment must have a minimum frequency at which the DLL is operated. In general, the current test equipment cannot test the DLL due to the limitation of the operating frequency of the equipment. it's difficult.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of testing a DLL even with test equipment having a low operating frequency.

1 is a block diagram of a synchronous DRAM according to an embodiment of the present invention.

2 is a circuit diagram of the controller shown in FIG.

3 is a block diagram of the high frequency clock generator shown in FIG.

4 is an operation timing diagram of the high frequency clock generator shown in FIG.

In accordance with another aspect of the present invention, a semiconductor memory device includes a delay lock loop circuit for removing skew between data, and one of a system clock and a high frequency clock in response to a wafer test enable signal. And a high frequency clock generator configured to output the high frequency clock in response to the system clock in response to the wafer test enable signal.

The controller selects the high frequency clock when the wafer test enable signal is activated and outputs it as a control signal for controlling the delay lock loop circuit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a synchronous DRAM according to an embodiment of the present invention. Only the circuits associated with the DLL test are shown here.

Referring to FIG. 1, the synchronous DRAM includes a DLL unit 11, a controller 13, and a high frequency clock generator 15.

The DLL unit 11 is for removing skew between data in order to smoothly input and output two data in one clock in the synchronous DRAM, and is controlled by a control signal CTL. The controller 13 selects one of the system clock CLK and the high frequency clock HF in response to the wafer test enable signal WT and outputs the control signal CTL. The high frequency clock generator 15 receives the system clock CLK and generates the high frequency clock HF in response to the wafer test enable signal WT.

FIG. 2 is a circuit diagram of the controller shown in FIG. 1.

Referring to FIG. 2, the controller may include a noah gate 21 that receives the system clock CLK and the wafer test enable signal WT, an output of the noah gate 21, and the high frequency clock HF. NARGATE 23 as an input, an inverter 25 for inverting the output of the NOAG 23, and an inverter 27 for inverting the output of the inverter 25 and outputting the control signal CTL. It is composed of

In the normal operation of the synchronous DRAM, the wafer test enable signal WT becomes a logic " low " so that the system clock CLK is output as the control signal CTL. In the wafer test operation of the synchronous DRAM, the wafer test enable signal WT becomes a logic " high " and the high frequency clock HF is output as the control signal CLT.

3 is a block diagram of the high frequency clock generator shown in FIG.

Referring to FIG. 3, the high frequency clock generator includes delay elements 31 to 34 and multiplexers 35, 36, and 37. That is, the high frequency clock generator is configured to combine the signals F1 to F4 delayed by the delay elements 31 to 34 by the multiplexers 35, 36, and 37 with the system clock CLK. Generate clock (HF). For reference, FIG. 4 illustrates an operation timing diagram of the high frequency clock generator illustrated in FIG. 3.

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

Therefore, the semiconductor memory device according to the present invention as described above has an advantage that the DLL test can be performed even with a test equipment having a low operating frequency by providing a high frequency clock generator for the DLL test.

Claims (2)

A delayed lock loop circuit for removing skew between data; A controller which selects one of a system clock and a high frequency clock in response to a wafer test enable signal and outputs the control signal to control the delay lock loop circuit; And And a high frequency clock generator configured to receive the system clock and generate the high frequency clock in response to the wafer test enable signal. The semiconductor memory device of claim 1, wherein the controller selects the high frequency clock and outputs the control signal to control the delay lock loop circuit when the wafer test enable signal is activated.