KR100738579B1 - Semiconductor memory deivce - Google Patents

Abstract

The present invention provides a semiconductor memory device which does not generate an error in an internal operation when entering or exiting a power-down mode. To this end, the present invention receives a clock signal, buffers a clock, and outputs the clock signal to a first internal clock. buffer; A power down mode detection unit for outputting a power down detection signal using a clock enable signal; An error prevention unit which is activated in response to the activation of the power down detection signal and outputs a power down control signal which is deactivated in synchronization with the transition of the first internal clock after the power down detection signal is deactivated; An internal clock generator configured to provide a second internal clock buffering the first internal clock in an activation period of the power down control signal; An input buffer unit configured to receive and transmit a command signal input from the outside in response to the power down control signal; An instruction latch unit for latching an instruction signal transmitted by the input buffer unit in response to the second internal clock; And a decoder unit for interpreting an instruction signal latched by the instruction latch unit and outputting a control signal for performing an internal operation.

 Semiconductor, Memory, Synchronous, Clock Enable Buffer, Decoder.

Description

Semiconductor memory device {SEMICONDUCTOR MEMORY DEIVCE}

1 is a block diagram of a semiconductor memory device according to the prior art;

FIG. 2 is a circuit diagram showing an input buffer shown in FIG.

FIG. 3 is a waveform diagram showing the operation of the semiconductor memory device shown in FIG.

4 is a block diagram of a semiconductor memory device according to a preferred embodiment of the present invention.

5 is a circuit diagram showing an input buffer shown in FIG.

FIG. 6 is a waveform diagram showing the operation of the semiconductor memory device shown in FIG.

Explanation of symbols on the main parts of the drawings

110 ~ 150: Input buffer

210 to 240: delay

310 ~ 340: Latch

400: power down mode detection unit

500: internal clock generator

600: decoder

700: error protection unit

The present invention relates to a semiconductor integrated circuit, and more particularly, to a signal input unit of a semiconductor memory device.

The semiconductor memory device has been continuously improved for the purpose of increasing the integration speed and increasing the operation speed thereof. In order to improve the operating speed, a so-called synchronous memory device capable of operating in synchronization with a clock given from a memory chip has been introduced.

The first proposal is a so-called single data rate (SDR) synchronous memory device that inputs and outputs one data over one period of the clock at one data pin in synchronization with a rising edge of the clock from the outside of the memory device.

However, an SDR synchronous memory device is also insufficient to satisfy the speed of a system requiring high-speed operation. Accordingly, a double data rate (DDR) synchronous memory device, which processes two data in one clock cycle, has been proposed.

Each data entry / exit pin of the digital synchronous memory device continuously inputs and outputs two data in synchronization with a rising edge and a falling edge of an externally input clock. Compared to the SDR synchronous memory device, at least twice as much bandwidth can be realized, so that high-speed operation can be realized.

A semiconductor device operating in synchronization with a clock may operate according to an internal clock buffering an input clock signal.

1 is a block diagram of a conventional semiconductor memory device.

Referring to FIG. 1, a semiconductor memory device according to the related art is configured to output an input buffer 10 for receiving and transmitting a clock enable signal CKE and a delayed time for a clock enable signal iCKE. The delay unit 20, the latch unit 30 for latching and outputting the signal output from the delay 20 in response to the internal clock signal iCLK_CKE, and the signal iCKE2 latched by the latch unit 30 Power down mode detection unit 40 to detect and output a power down detection signal (PDB), and an input buffer for receiving each command (RASB, CASB, WEB, CSB) signal in response to the power down detection signal (PDB) ( 11 to 14, delays 21 to 24 for delaying the signals input by the respective input buffers 11 to 14, and signals delayed by the delays 21 to 24 to the second internal clock signal iCLK_CMD. A latch unit 31 to 34 for latching and outputting the signal, an input buffer 15 for receiving a clock signal, Receives and decodes the internal clock generator 50 for outputting the internal clock signal iCLK_CMD using the internal clock signal iCLK_CKE buffered by the input buffer 15 and each internal command signal output from each latch unit. And a decoder 60 for outputting control signals iAcitve, iPrecharge, iRead, iWrite, iMRS to control each operation of the memory device.

FIG. 2 is a circuit diagram illustrating an input buffer shown in FIG. 1.

Referring to FIG. 2, the input buffer 11 is turned on to the power-down detection signal PDB and receives one of the command signals RASB, CASB, WEB, and CSB in response to the reference signal VREF. It is configured to output the command signal iCMD.

FIG. 3 is a waveform diagram illustrating an operation of the semiconductor memory device shown in FIG. 1. Hereinafter, an operation of the semiconductor memory device will be described with reference to FIGS. 1 to 3.

The clock enable signal input buffer 10 is always in the power down mode state or the non-sleep mode state, which is insulated mode, and is always activated. In contrast, the input buffers 11 to 15 receiving the command signal are disabled in the power down mode. Becomes The signal for controlling this is the power down detection signal PDB output from the power down mode detecting unit 40.

In the power down mode, the power down detection signal PDB goes low level, otherwise goes high.

Each input buffer shown in FIG. 1 serves to convert an external command into an internal command of a digital signal level, and the internal command is synchronized by the internal clock ICLK_CMD in the latch units 31 to 34 after a predetermined time delay circuit. do.

At this time, the delay units 21 to 24 are circuits used by the latch units 31 to 34 to satisfy the setup time and hold time between the external command and the clock.

The decoder 60 finally decodes the internal command signals iRASB2, iCAB2, iWEB2, and iCSB2 synchronized to the internal clock ICLK_CMD in each latch unit 31 to 34 to perform necessary operations in the memory device. Various control signals (iAcitve, iPrecharge, iRead, iWrite, iMRS) are output.

The clock enable latch unit 30 and the latch units 31 to 34 for latching internal commands are operated by different internal clocks iCLK_CKE and iCLK_CMD. The internal clock iCLK_CKE is always activated regardless of the power mode. The internal clock iCLK_CMD is output from the internal clock generator 50 that receives the power down detection signal PDB. Deactivation and activation are determined.

3 is a timing diagram related to a general power-down mode entry and launch operation. When the MRS (Mode Register Set) command is input from the first clock, the internal command signals iRASB2, iCASB2, iWEB2, and iCSB2 are all low level and the corresponding decoder outputs the corresponding internal MRS command (iMRS).

Then, the mode register stores values of clock latency (CL) and burst length (BL). When the power down detection signal is input at the eighth time after the precharge all command is input at the third clock, the semiconductor device enters the precharge power down state, that is, the IDD2P.

At this time, since the power-down detection signal PDB transitions from the high level to the low level, the internal clock iCLK_CMD does not occur, so the command decoder maintains the previous state and consumes a minimum of current. If the power down mode escape command is received at the n th clock, the power down detection signal PDB transitions from the low level to the high level, and the internal clock iCLK_CMD is activated to decode the newly input command signal.

At this time, when a section in which the power down detection signal PDB and the internal clock iCLK_CKE overlap in timing occurs, an unwanted glitch occurs in the internal clock iCLK_CMD at the nth clock. When the internal commands (iRASB1, iCASB1, iWEB1, iCSB1) are at a low level, latches are latched at each latch unit. Therefore, the internal commands (iRASB2, iCASB2, iWEB2, iCSB2) are at a low level, and the command decoder 60 is abnormal. By outputting the internal MRS command (iMRS) (see abnormal iMRS in FIG. 3), the values of CL and BL stored in the mode register are changed initially, causing a malfunction in the write / read operation of the semiconductor memory device.

For example, as soon as the semiconductor memory device operates with CL = 3, BL = 4 and exits the power-down mode, the mode register values such as CL = 2, BL = 4 or CL = 3, BL = 8 are changed. After that, it will not work properly.

Such defects frequently occur particularly at the mounting level, which greatly reduces the reliability of the memory device.

The present invention has been proposed to solve the above-described problem, and an object of the present invention is to provide a semiconductor memory device in which an error does not occur in an internal operation when entering or exiting a power-down mode.

The present invention provides a clock buffer for receiving a clock signal and outputting the buffered signal to a first internal clock; A power down mode detection unit for outputting a power down detection signal using a clock enable signal; An error prevention unit which is activated in response to the activation of the power down detection signal and outputs a power down control signal which is deactivated in synchronization with the transition of the first internal clock after the power down detection signal is deactivated; An internal clock generator configured to provide a second internal clock buffering the first internal clock in an activation period of the power down control signal; An input buffer unit configured to receive and transmit a command signal input from the outside in response to the power down control signal; An instruction latch unit for latching an instruction signal transmitted by the input buffer unit in response to the second internal clock; And a decoder unit for interpreting an instruction signal latched by the instruction latch unit and outputting a control signal for performing an internal operation.

In the present invention, in order to prevent the internal command from having a low level corresponding to the MRS command combination in the power down mode, the output of the command input buffer is lowered and the power down detection signal PDB is synchronized with the polling edge of the external clock. By making the transition, the glitch generated in the internal clock signal for latching the latch portion which essentially latches the internal command is eliminated.

Therefore, even if the memory device exits the power-down mode at any point in time, the decoder that decodes the instructions does not cause abnormal internal commands to occur so that the operation is stable.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

4 is a block diagram illustrating a semiconductor memory device in accordance with a preferred embodiment of the present invention.

Referring to FIG. 4, the semiconductor memory device according to the present invention outputs an input buffer 100 that receives and transmits a clock enable signal CKE and a delayed time of the transferred clock enable signal iCKE. Delay 200, the latch unit 300 for latching and outputting the signal output from the delay 200 in response to the internal clock signal (iCLK_CKE), and the signal (iCKE2) latched by the latch unit 300 The power down mode detection unit 400 detects and outputs the power down detection signal PDB, and the power down mode detection signal PDB is immediately activated at a low level when the power down mode detection signal PDB is activated. At the timing of deactivation of the internal clock signal iCLK_CKE in response to the error prevention unit 700 outputting a power down control signal PDB_NEW which is deactivated to a high level after the falling edge of the internal clock signal iCLK_CKE, Each command (RASB, Input buffers 110 to 150 for receiving CASB, WEB, and CSB signals, delays 210 to 240 for delaying signals input by the respective input buffers 110 to 140, and delays 210 to 240 Latches 310 to 340 for latching and outputting the delayed signal in response to the second internal clock signal iCLK_CMD, an input buffer 150 for receiving a clock signal, and an input buffer 150. The internal clock generator 500 for outputting the second internal clock signal iCLK_CMD using the buffered internal clock signal iCLK_CKE, and the respective internal command signals output from each latch unit are received and decoded. The decoder 600 outputs control signals iAcitve, iPrecharge, iRead, iWrite, and iMRS for controlling the operation.

The error prevention unit 700 receives and outputs a power down detection signal PDB and a power up signal PWRUP to the input terminal D and the reset terminal in synchronization with the internal clock signal iCLK_CKE. 710, NAND gates and inverters 720 and 730 for ending and outputting the output of the flip-flop 710 and the power down detection signal PDB.

FIG. 5 is a circuit diagram illustrating an input buffer shown in FIG. 4.

Referring to FIG. 5, the input buffer 110 is activated in response to the power down detection signal PDB and outputs a command signal CMD corresponding to the reference signal VREF, and a power down detection. The output unit 112 is activated in response to the signal PDB to output an internal command signal by buffering the command signal iCMD delivered by the input unit 111.

FIG. 6 is a waveform diagram illustrating an operation of the semiconductor memory device shown in FIG. 4. Hereinafter, operations of a semiconductor memory device according to the present embodiment will be described with reference to FIGS. 4 to 6.

The clock enable signal input buffer 100 is always in the power down mode state or the non-sleep mode state, which is insulated mode, and is always activated, whereas the input buffers 110 to 140 receiving the command signal are disabled in the power down mode. Becomes The signal for controlling this is a power down detection signal PDB output from the power down mode detecting unit 400.

In the power down mode, the power down detection signal PDB goes low level, otherwise goes high.

The error prevention unit 700 receives the power down detection signal PDB, generates a signal PDB_F which is synchronized with the falling edge of the internal clock iCLK_CKE using the flip-flop 710, and then powers down the signal and the power down signal. The AND logic combination of the detection signal PDB causes the power down control signal PDB_NEW to be immediately activated from the high level to the low level when entering the power down mode, and after the falling edge of the internal clock signal iCLK_CLK when exiting the power down mode. The transition from low level to high level prevents glitches from occurring in the internal clock signal iCLK_CMD.

As shown in FIG. 4, each input buffer shown in FIG. 4 serves to convert an external command into an internal command of a digital signal level, and the internal command passes through a predetermined time delay circuit, and then internal clock (ICLK_CMD) in the latch units 310 to 340. Motivated by).

At this time, the delay units 210 to 240 are circuits used by the latch units 310 to 340 to satisfy the setup time and hold time between the external command and the clock.

The decoder 600 finally decodes the internal command signals iRASB2, iCAB2, iWEB2, and iCSB2 synchronized to the internal clock ICLK_CMD in each latch unit 310 to 340 to perform necessary operations in the memory device. Various control signals (iAcitve, iPrecharge, iRead, iWrite, iMRS) are output.

The clock enable latch unit 300 and the latch units 310 to 340 for latching internal commands are operated by different internal clocks iCLK_CKE and iCLK_CMD. The internal clock iCLK_CKE is always activated regardless of the power mode. The internal clock iCLK_CMD is output from the internal clock generator 50 that receives the power-down control signal PDB_NEW. The deactivation and activation are therefore determined.

Therefore, even if the power-down mode exits at any point in time, the command decoder does not generate a control signal that causes an abnormal detail command.

As shown in Fig. 6, when the power-down mode enters, it enters the same timing as before, and when exiting, it always exits after the falling edge of the internal clock iCLK_CKE. The section in which the internal clock iCLK_CKE overlaps in timing does not occur.

In addition, in order to prevent the input buffer from having the same logic value as that of the MRS command in the power-down mode (iRAS, iCAS, iWEB, and iCSB are all low level), the power-down detection signal PDB at the output 112 of the input buffer. The circuit is configured so that can only be activated after is deactivated to a high level.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The input buffer control method and the circuit of the semiconductor memory device according to the present invention fundamentally solved a malfunction caused by the timing problem of the internal command and the internal clock when the next command is executed after exiting the power down mode.

Therefore, it is possible to improve the operational reliability of the product by eliminating the malfunction caused by the power mode of the memory device to prevent defects during mounting applications.

Claims (8)

A clock buffer which receives the clock signal and buffers the clock signal and outputs the buffered clock signal to the first internal clock; A power down mode detection unit for outputting a power down detection signal using a clock enable signal; An error prevention unit which is activated in response to the activation of the power down detection signal and outputs a power down control signal which is deactivated in synchronization with the transition of the first internal clock after the power down detection signal is deactivated; An internal clock generator configured to provide a second internal clock buffering the first internal clock in an activation period of the power down control signal; An input buffer unit configured to receive and transmit a command signal input from the outside in response to the power down control signal; An instruction latch unit for latching an instruction signal transmitted by the input buffer unit in response to the second internal clock; And A decoder unit for interpreting the command signal latched by the command latch unit to output a control signal for performing the internal operation A semiconductor memory device having a. The method of claim 1, The error prevention unit A flip-flop for outputting the power down detection signal in synchronization with transition timing to the first internal clock after the power down detection signal is inactivated; And And an AND gate for performing an AND operation on the output of the flip-flop and the power down detection signal to output the power down control signal. The method of claim 2, The flip-flop is a reset terminal And a flip-flop receiving a power-up signal that is initially activated when a power supply voltage is supplied to the semiconductor memory device. The method of claim 1 And a clock enable latch for latching the clock enable signal in response to the first internal clock and outputting the clock enable signal to the power down mode detection unit. The method of claim 4, wherein And a clock enable input buffer for buffering a clock enable signal input from an external source and transferring the clock enable signal to the clock enable latch. The method of claim 5, The clock enable signal transmitted from the clock enable input buffer is delayed by a predetermined time to secure the setup and hold timing between the clock enable signal transmitted from the outside and the clock signal transmitted from the outside. And a delay for providing the enable latch. The method of claim 1, In order to secure setup and hold timing between the input timing of the clock enable signal transmitted externally and the clock signal transmitted externally, delaying a command signal transmitted from the input buffer unit for a predetermined time to provide the command latch unit to the command latch unit. And a delay for the semiconductor memory device. The method of claim 1, The input buffer unit An input unit activated in response to the power down detection signal and receiving and outputting a command signal; And And an output unit which is activated in response to the power down detection signal and outputs the buffered command signal transmitted by the input unit to the command latch unit.

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