KR100668517B1 - Output control device with test device - Google Patents

Abstract

An output control apparatus having a test device is provided to prevent data from being erroneously outputted by controlling an activation timing of an output enable signal according to a test signal. An output control apparatus includes an initial synchronization unit(300), plural synchronization units(400), and a test device(500). The initial synchronization unit outputs a first output enable signal, when a read CAS(Column Address Strobe) signal is activated. The synchronization units are series-connected to each other. The synchronization unit outputs an output signal from the preceding synchronization unit as an output enable signal, synchronously with a corresponding driving clock, where the first synchronization unit receives the first output enable signal as an input. The test device adjusts the delay amount of an input clock according to a test signal and outputs the result to the driving clock.

Description

Output control device with test device {OUTPUT CONTROL DEVICE WITH TEST DEVICE}

1 is a block diagram of an output control apparatus according to the prior art.

Fig. 2A is an operational waveform diagram of an output control device at low frequency.

2B is a diagram showing a problem in driving an output control apparatus at high frequency.

3 is a block diagram of an output control apparatus having a test apparatus according to the present invention.

4 is an internal circuit diagram of a test unit of FIG. 3 according to a first embodiment of the present disclosure.

5 is an internal circuit diagram of a delay amount adjusting unit of FIG. 4.

6 is an internal circuit diagram of a selector of FIG. 3.

7 is an internal circuit diagram of the initial synchronization unit of FIG. 3.

8 is an internal circuit diagram of the synchronizer of FIG. 3.

9 is an internal circuit diagram of a test unit of FIG. 3 according to a second embodiment of the present disclosure.

FIG. 10 is an internal circuit diagram of a delay amount adjusting unit of FIG. 9. FIG.

* Explanation of symbols for the main parts of the drawings

500: test unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to an output control device for controlling a data output time point of a semiconductor memory device, and more particularly, to an output control device having a test device.

The semiconductor memory device has been continuously improved for the purpose of increasing the integration speed and increasing the operation speed thereof. In order to improve the operation speed, so-called synchronous memory devices that can operate in synchronization with a clock given from outside the memory chip have been introduced.

The first proposal is a so-called single data rate (SDR) synchronous memory device that inputs and outputs one data over one period of the clock at one data pin in synchronization with a rising edge of the clock from the outside of the memory device.

However, an SDR synchronous memory device is also insufficient to satisfy the speed of a system requiring high-speed operation. Accordingly, a double data rate (DDR) synchronous memory device, which processes two data in one clock cycle, has been proposed.

Each data entry / exit pin of the digital synchronous memory device continuously inputs and outputs two data in synchronization with a rising edge and a falling edge of an externally input clock. At least twice as much bandwidth as the SDR synchronous memory device can realize high-speed operation.

However, since the DL memory device needs to export or receive two data in one clock cycle, the data access method used in the conventional synchronous memory device cannot be used to effectively perform this.

If the clock cycle is about 10 nsec, subtracting the rise and fall time (approximately 0.5 × 4 = 2) and the time to meet other specifications, etc., the two data continuously for about 6 nsec or less. Since this processing is not sufficient to be performed inside the memory device, the memory device inputs and outputs data at the rising edge and the falling edge of the clock only when the data is sent to or received from the outside. It will process two pieces of data synchronized to one edge of the.

Therefore, a new data access method is required to receive data from the memory device and transfer the data to the internal core area or to output data transmitted from the core area to the outside.

Synchronous memory devices, on the other hand, use several different concepts from previous asynchronous memory devices, one of which is CAS LATENCY (CL). The cascade latency refers to the number of clocks after the read command is input until the data is output from the memory device. For example, CL = 3 means that data is stored after three clock cycles after the read command is input to the memory device. It means output to the outside. Therefore, the cascading mode value determines the timing of outputting data, and the memory device detects the CL value set during initial operation and uses the data to access and output the data.

Therefore, the memory device generates a data output enable signal in response to the read command and delays the period of the operation clock by the set cascade time, and the data output enable signal is activated when the data output enable signal is activated. The data will be output to the outside.

In this case, the operation clock used is a DLL clock in which a clock signal input from the outside is fixed by a predetermined time, and the DLL clock is generated and output in a delay lock loop. The memory device must output the data in synchronization with the rising edge and the falling edge of the clock inputted from the outside, and the rising edge and polling of the external clock inputted from the external clock due to the delay time of the clock signal inevitably generated during internal processing. The data cannot be output in synchronization with the edge.

The clock signal generated to compensate for this is the DLL clock output from the delay lock loop of the memory device. If the data is output to the outside in synchronization with the DLL clock, the data can be output in synchronization with the rising edge and the falling edge of the external clock.

1 is a block diagram of an output control apparatus according to the prior art.

Referring to FIG. 1, an output control apparatus according to the related art delays an applied rising-DLL clock RCLK_DLL and a falling-DLL clock FCLK_DLL by a predetermined time in response to the corresponding cascade latency information signals CL3 to CL5. To select the clock delay unit 10 and the signal corresponding to the cascade latency information signals CL3 to CL5 among the output signals of the clock delay unit 10 to output to the plurality of driving clocks RCLK_OE10 to RCLK_OE35, respectively. The selector 20 and the initial synchronization unit 30 for outputting the output enable signal OE00 upon activation of the read casing signal CASP6_RD are connected in series to synchronize the preceding output signal with the corresponding drive clock and DLL clock. And a synchronization unit 40 for outputting the corresponding output enable signals OE10 to OE45.

For reference, the read cascade signal CASP6_RD is a signal for generating a substantial read operation in the semiconductor memory device when the read command RD is applied, and the cascade latency information signals CL3 to 5 are set as a plurality of signals. Only the signal corresponding to (CL) is activated.

Although not shown in the drawing, the output enable signals OE00 to OE45 are signals having information on the delay time from the activation time of the read cascade signal CASP6_RD and are used to provide information on the cascade latency CL. Is the signal that is generated. In other words, the output drive signals ROUTEN and FOUTEN that control the output time point of the data can be satisfied so that the data output from the memory core block by the read command is satisfied when the data is output to the outside through the data pad. Output enable signals OE00 to OE45 are used during generation.

Meanwhile, the operation of the general output control apparatus without the clock delay unit 10 and the clock selector 20 shown in FIG. 1 will be described according to frequency.

2A is an operation waveform diagram of a general output control device at low frequency.

Referring to FIG. 2A, when a read command RD is applied in synchronization with an external clock CLK, a read cascade signal CASP6_RD corresponding to the read command RD is activated.

Subsequently, the initial synchronization unit 30 activates the output enable signal OE00 in response to the activation of the read casing signal CASP6_RD. The first synchronization unit outputs the output enable signal OE10 in synchronization with the rising edge of the first rising-DLL clock RCLK_DLL from the activation of the output enable signal OE00.

Although not shown in the drawing, the second synchronizer synchronizes the output enable signal OE10 of the first synchronizer with the polling-DLL clock FCLK_DLL to activate the output enable signal OE15, and the third synchronizer outputs the output signal ( OE15) is synchronized with the rising-DLL clock (RCLK_DLL) to activate the output enable signal OE20.

Through this process, the plurality of output enable signals OE00 to OE45 synchronized with the rising edge of the rising-DLL clock RCLK_DLL and the falling-DLL clock FCLK_DLL are activated from the activation of the read casing signal CASP6_RD.

However, as shown in FIG. 2B, when the output control apparatus is driven at a high frequency, the output enable signal OE10 synchronized with the first rising-DLL clock RCLK_DLL cannot be activated from the activation of the read casing signal CASP6_RD. This happens.

Since the output controller is driven at a high frequency, the edge of the first rising-DLL clock RCLK_DLL is ahead of the activation time of the output enable signal OE00 activated by the initial synchronization unit 30. Therefore, the first synchronization unit outputs the output enable signal OE10 in synchronization with the second rising-DLL clock.

That is, since the activation time of the output enable signal generated by the output control device is delayed by one clock, the data that is output in synchronization with the generated output drive signal does not satisfy the set cascade latency, causing data to fail. do.

In order to solve such a problem, the output control apparatus according to the prior art further includes a clock delay unit for delaying and outputting the rising-DLL clock and the falling-DLL clock according to the cascading time, and driving the corresponding clock among them according to the cascading time. It further includes a selection unit for outputting.

On the other hand, the output control device according to the prior art is provided with a clock delay unit and a selector to adjust the rising time of the DLL clock according to the frequency in order to prevent the data rise due to the first rising-DLL clock is activated before the read-cas signal However, this has a problem that it is not possible to control according to the PVT fluctuation in the actual chip because it has a fixed delay amount.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide an output control apparatus having a test apparatus capable of testing an appropriate delay amount according to an operating frequency in a real situation.

According to an aspect of the present invention, there is provided an output control apparatus comprising: initial synchronization means for outputting a first output enable signal upon activation of a read cas signal; Serially connected to output an output enable signal in synchronization with a corresponding drive clock, the first output means comprising: a plurality of synchronization means having the first output enable signal as an input; And test means for adjusting the delay amount of the input clock according to the test signal and outputting the delayed signal to the driving clock.

According to another aspect of the present invention, an output control apparatus includes: initial synchronization means for outputting a first output enable signal upon activation of a read casing signal; Serially connected to output an output enable signal in synchronization with a corresponding drive clock, the first output means comprising: a plurality of synchronization means having the first output enable signal as an input; And test means for controlling the delay amount of the selected signal among the input clocks in response to the plurality of test off signals to output the plurality of driving clocks according to the test-delay amount control signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3 is a block diagram of an output control apparatus having a test apparatus according to the present invention.

Referring to FIG. 3, the output control apparatus according to the present invention is connected in series with an initial synchronization unit 300 for outputting the output enable signal OE00 when the read casing signal CASP6_RD is activated, and drives the corresponding output signal. A plurality of synchronization units 400 for outputting the corresponding output enable signals OE00 to OE45 in synchronization with the clocks RLCK_OE10 to RCLK_0E30, FCLK_OE15 to FCLK_OE35 and the DLL clocks RCLK_DLL and FCLK_DLL, and the test signals NO_TM and TM_DEC And a test unit 500 for outputting the driving clocks RLCK_OE10 to RCLK_0E30, FCLK_OE15 to FCLK_OE35 by adjusting the delay amount of the input clocks RDLL_OE10CL, FDLL_OE15CL to RDLL_OE30CL, and FDLL_OE35CL according to TM_INC.

The output control device includes a clock delay unit 100 for delaying and outputting the applied rising-DLL clock RCLK_DLL and the falling-DLL clock FCLK_DLL in response to the corresponding cascade latency information signals CL3 to CL5. And a selector 200 for selecting and outputting signals corresponding to the cascade latency information signals CL3 to CL5 among the output signals of the clock delay unit 100.

As described above, the above-described output control apparatus includes a test unit 500 capable of adding a delay to the driving clocks RLCK_OE10 to RCLK_0E30 and FCLK_OE15 to FCLK_OE35 of the synchronization unit 400 for generating the output enable signals OE00 to OE45. Since it further includes, it is possible to test the amount of delay required according to the frequency in the situation of the actual implemented chip.

Next, each block of the output control apparatus will be described in detail with reference to the accompanying drawings.

4 is an internal circuit diagram of the test unit 500 of FIG. 3 according to the first embodiment of the present invention.

Referring to FIG. 4, the test unit 500 according to the first embodiment has a delay of each input signal according to the test-delay increase signal TM_INC, the delay decrease signal TM_DEC, and the delay basic signal NO_TM, respectively. The first to sixth delay amount adjusting units 510, 520, 530, 540, 550, and 560 for adjusting the amount and outputting the amount to the driving clocks RCLK_OE10, FCLK_OE15, RCLK_OE30, and FCLK_OE35 are respectively provided.

5 is an internal circuit diagram of the first delay amount adjusting unit 510 of FIG. 4, and the first to sixth delay amount adjusting units 510, 520, 530, 540, 550, and 560 have the same circuit implementation. The first delay amount adjusting unit 510 will be described as an example.

Referring to FIG. 5, the first delay amount adjusting unit 510 is connected in series to test and delay the first and second delay elements 512 and 514 and the input clock RDLL_OE10CL to delay the input signal. In response to the TM_DEC, the first transfer gate TG1 and the output signal of the first delay element 512 are transferred to the driving clock RCLK_OE10 in response to the test-delay basic signal NO_TM. The second transfer gate TG2 for transmitting the second transfer gate TG2 and the third transfer gate for transmitting the output signal of the second delay element 514 to the driving clock RCLK_OE10 in response to the test delay delay increasing signal TM_INC. TG3).

The delay amount adjusting unit 510 outputs the signal delayed by the first delay unit 512 to the driving clock RCLK_OE10 when the test-basic delay signal NO_TM is activated, and the test-delay increase signal TM_INC. When is activated, the signals delayed by the first and second delay units 512 and 514 are output to the driving clock RCLK_OE10. When the test-delay reduction signal TM_DEC is activated, the test-delay reduction signal TM_DEC is output to the driving clock RCLK_OE10 without delaying the input clock RDLL_OE10CL.

6 is an internal circuit diagram of the selector 200 of FIG. 3.

Referring to FIG. 6, the selector 200 selects one of the corresponding clocks among the plurality of clocks of the first to third clock delay units 120, 140, and 160 in response to the cascade latency information signal. To sixth selectors 210, 220, 230, 240, 250, and 260.

Since the first to sixth selectors 210, 220, 230, 240, 250, and 260 have the same circuit implementation, the first selector 210 will be described as an example.

The first selector 210 transmits the first clock RDLL_OE10DL3 of the plurality of clocks of the first clock delay unit 120 when the cascade latency information signal CL3 is activated, and the second clock. A second transfer gate TG5 for transferring the first clock RDLL_OE10DL4 of the plurality of clocks of the delay unit 140 when the cascade latency information signal CL4 is activated, and the first clock RDLL_OE10DL5 of the plurality of clocks of the third clock delay unit; Is applied to the third transfer gate TG6 and the common output node of the first to third transfer gates TG4, TG5, and TG6 to transfer the cas latency information signal CL5 upon activation. An inverter I1 for outputting to the clock RDLL_OE10CL is included.

That is, the selector 100 selects a plurality of delay clocks RDLL_OE10DL3, FDLL_OE15DL3, ˜ RDLL_OE30DL3, and FDLL_OE35DL3 of the first clock delay unit 120 when the latency information signal CL3 is activated. RDLL_OE30CL, FDLL_OE35CL), or the plurality of delay clocks RDLL_OE10DL4, FDLL_OE15DL4, FDLL_OE15DL4,-RDLL_OE30DL4, FDLL_OE35DL4 of the second clock delay unit 140 when the CAS latency information signal CL4 is activated. RDLL_OE30CL, FDLL_OE35CL). When the CAS latency information signal CL5 is activated, the plurality of delay clocks RDLL_OE10DL5, FDLL_OE15DL5,-RDLL_OE30DL5, and FDLL_OE35DL5 of the third clock delay unit 160 are transferred to the cas-delay clocks RDLL_OE10CL, FDLL_OE15CL, and RDLL_OE30CL, FDLL_OE35). .

FIG. 7 is an internal circuit diagram of the initial synchronization unit 300 of FIG. 3.

Referring to FIG. 7, the initial synchronization unit 300 receives a column command YBST and an internal clock CLKP4 to generate a deactivation control signal, a read cascade signal CASP6_RD, and a deactivation. A driver 340 for driving the output node in response to the control signal, a latch 360 for inverting and latching the voltage applied to the output node and outputting the output enable signal OE00, a power-up signal PWRUP, and writing An initialization unit 380 is provided to initialize the output node in response to the read flag WT_RDB.

In addition, the deactivation control unit 320 reads the inverter I2 for inverting the bus-transform information signal BL2, the NAND gate ND1 having the output signal of the inverter I2 and the column-based command YBST as input, and An inverter I3 for inverting the cas signal CASP6_RD, a NAND gate ND2 having an output signal of the NAND gate ND1 and an output signal of the internal clock CLKP4 and the inverter I3, and a NAND gate as inputs. An inverter I4 for inverting the output signal of ND2 and a NAND gate ND3 for outputting an inactive control signal by taking output signals of the inverters I3 and I4 as inputs.

The initialization unit 380 receives the write read flag WT_RDB and the power-up signal PWRUP, and an initialization signal generator 382 for generating an initialization signal, and an initialization signal as a gate input, and has an internal power supply voltage VDD. A PMOS transistor (PM1) having a source-drain path between the supply terminal and the output node.

Next, the operation of the initial synchronization unit 300 will be briefly described. First, when the read cascade signal CASP6_RD is activated to the logic level 'H', the driver pulls down the output node to the logic level 'L' in response to the latch. 360) inverts the voltage applied to the output node and outputs the output enable signal OE00 at a logic level 'H'.

In addition, when the read casing signal CASP6_RD is not applied and the column-based command YBST is at the logic level 'L' or the bus-transform information signal BL2 has the logic level 'H', the initialization unit 300 The driver 340 pulls up the output node by generating a deactivation control signal at a logic level 'H' of the internal clock CLKP4. Therefore, the output node transitions to the logic level 'H', and the latch outputs the inverted signal, thereby deactivating the output enable signal OE00.

Also, if the power supply signal PWRUP is not activated because the level of the internal power supply is not stabilized during the initial driving of the device, or if the write read flag WT_RDB has the logic level 'H' due to the application of the write command WT, the initialization is performed. Since the unit 380 pulls up the output node, the output enable signal OE00 is deactivated regardless of the input signal.

FIG. 8 is an internal circuit diagram of the first synchronization unit 410 of FIG. 3. Since the first to sixth synchronization units 410 to 480 have the same circuit implementation, the first synchronization unit 410 will be described as an example. do.

Referring to FIG. 8, the first synchronization unit 410 may include an input unit 412 for receiving the output enable signal OE00 in synchronization with the rising edge of the driving clock RCLK_OE10, and first and second terminals of the input unit 412. The driver 414 for driving the output node in response to the outputs D2B and D2, the latch 416 for latching a signal applied to the output node of the driver 414, and the output when the reset signal OE_RSTB is deactivated. An output control unit 418 is provided for inverting the signal applied to the node and outputting the signal as an output enable signal OE10.

Briefly referring to the operation of the first synchronization unit 410, when the reset signal OE_RSTB is activated to the logic level 'L', the output enable signal OE10 is deactivated to the logic level 'L' regardless of the input signal. When the input signal OE00 is activated during the deactivation of the reset signal OE_RSTB, the input signal OE00 is synchronized with the rising edge of the driving clock RCLK_OE10 and output as the output enable signal OE10.

Meanwhile, the operation of the output control apparatus including the test unit 500 according to the first embodiment shown in FIGS. 3 to 8 will be briefly described.

First, the first to third clock delay units 120, 140, and 160 respectively delay the applied clock by a fixed delay amount and output the delayed clocks as a plurality of delay clocks. The selector 200 selects one of the first to third clock delay units 120, 140, and 160 according to the cascade latency information signals CL3 to CL5, and selects a plurality of delay clocks from the plurality of cas-delay clocks. Will print

The test unit 300 is a cas-delay clock (RDLL_OE10CL, FDLL_OE15CL, ~ RDLL_OE30CL, FDLL_OE35CL) applied according to the test delay delay signal (NO_TM), the test delay delay increase signal (TM_INC), and the test delay delay signal (TM_DEC). The additional delay is added to the delay of or) and output to the plurality of driving clocks RCLK_OE10, FCLK_OE15, ~ RCLK_OE30, FCLK_OE35 without any additional delay.

In addition, when the read cascade signal CASP6_RD is activated due to the application of the read command, the initial synchronization unit 300 activates the output enable signal OE00 in response thereto.

Subsequently, the first synchronization unit 410 synchronizes the output signal OE00 of the initial synchronization unit 300 with the first driving clock RCLK_OE10 and outputs the output enable signal OE10. The second synchronizer 420 synchronizes the output signal OE10 of the first synchronizer 410 with the second drive clock FCLK_OE15 to output the output enable signal OE15, and the third synchronizer 430 outputs the second signal. The output signal OE15 of the synchronization unit 420 is synchronized with the third driving clock RCLK_OE20 and output as the output enable signal OE20.

Therefore, the output control device according to the present invention generates a plurality of output enable signals OE00 to OE45 that are activated at intervals of about half a clock from the activation time of the read casing signal CASP6_RD.

At this time, the activation time of the output enable signals OE00 to OE45 is controlled by the test signals NO_TM, TM_INC, TM_DEC. In other words, the activation time is controlled by adjusting the delay amount of the driving clock applied to the synchronization unit 400 through the test signals NO_TM, TM_INC, and TM_DEC.

The output control apparatus according to the present invention can determine the amount of delay required to prevent the data from failing according to the frequency by adjusting the driving clock delay amount that controls the timing of activating the output enable signal through the test signal. . That is, even though the delay amount is given through the conventional clock delay unit, the problem that the PVT variation of the actual chip cannot be reflected is solved.

9 is an internal circuit diagram of the test unit 500 of FIG. 3 according to the second embodiment of the present invention.

Referring to FIG. 9, the test unit 500 according to the second embodiment of the present disclosure inputs the test delay delay signal TM_INC, the test delay delay signal NO_TM, and the test delay delay signal TM_DEC. In addition to different clock delays, a plurality of delay control units 570, 580, 590, 592, 594, and 596 may be used to select whether to use a test for each input clock through the test off signals TM_OE10 to TM_OE30. Equipped.

FIG. 10 is an internal circuit diagram of the first delay amount adjuster 570 of FIG. 9, and the first to sixth delay amount adjusters 580, 590, 592, 594, and 596 have the same circuit implementation, and thus may be the first circuit. Only the delay amount adjusting unit 570 will be described as an example.

Referring to FIG. 10, the first delay amount adjusting unit 570 is connected in series to first and second delay elements 571 and 572 for delaying the input clock RDLL_OE10CL, and the first and second delay elements ( First to third transfer gates TG7, TG8 and TG9 for transmitting the input signals and the output signals of the 571 and 572 to the first driving clock RCLK_OE10 when the control signal is activated, and the first test off signal TM_OE10. ) And a first control unit 573 for controlling driving of the first transfer gate TG7 with the test-delay reduction signal TM_DEC as an input, a first test-off signal TM_OE10 and a test-delay basic signal ( A second control unit 574 for controlling the driving of the second transfer gate TG8 with NO_TM as an input, a first test off signal TM_OE10 and a test delay delay signal TM_INCC as inputs; A third control unit 575 for controlling the driving of the transfer gate TG9 is included.

Since the first to third controllers 573, 574, and 575 have the same circuit implementation except for only input signals, the first controller 573 will be described as an example.

The first control unit 573 inverts the NAND gate ND5 having the first test off signal TMOE10 and the test-delay reduction signal TM_DEC as input, and the output signal of the NAND gate ND5 by inverting the first control signal. Inverter I7 for outputting is provided.

As such, the operation of the test unit 500 according to the second exemplary embodiment illustrated in FIGS. 9 and 10 will be briefly described. In the test unit according to the second embodiment, the plurality of driving clocks do not all adjust the delay amount according to the test-delay reduction signal TM_DEC, the test-delay basic signal NO_TM, and the test-delay increase signal TM_INC. It is possible to select whether to test for each clock through the test off signals TM_OE10 to TM_OE30.

That is, the test unit according to the second embodiment has an advantage that the test can be performed for each drive clock compared to the test unit according to the first embodiment.

Therefore, the above-described output control apparatus according to the present invention controls the activation time of the output enable signal through a test signal, so that it is possible to know the delay amount necessary to prevent the data from failing according to the driving frequency and the PVT variation of the device. have.

Meanwhile, in the above-described present invention, an output control apparatus for controlling the output time point of the data by the read command is exemplified. However, the present invention can be applied to a block in which a plurality of signals are activated at regular intervals when a flag signal is applied, such as a read casing signal. Do. That is, when generating a plurality of signals from the flag signal at regular intervals, if the activation time is controlled through the test signal, the required delay amount can be known according to the frequency, thereby achieving the same purpose as the present invention.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, the present invention controls the activation time of the output enable signal through the test signal, so that the amount of delay necessary for failing to fail data can be known.

Claims (30)

Initial synchronization means for outputting a first output enable signal upon activation of a read cas signal; Serially connected to output an output enable signal in synchronization with a corresponding drive clock, the first output means comprising: a plurality of synchronization means having the first output enable signal as an input; And Test means for outputting to the drive clock by adjusting the delay amount of the input clock according to the test signal Output control device including. The method of claim 1, The test means, And a plurality of delay amount adjusting units for increasing or decreasing the delay amount of each of the input clocks according to the test-delay increase signal, the test-delay decrease signal, and the test-delay base signal, and output the driving delay signal to the driving clock. that Output control device characterized in that. The method of claim 2, The delay amount adjusting unit, When the test-base delay signal is activated, a basic delay is added to the corresponding input clock and output to the driving clock. When the test-delay increase signal is activated, a delay longer than the basic delay is added and output to the driving clock. And outputting the corresponding input clock to the driving clock as it is when the test delay signal is activated. The method of claim 3, The delay amount adjusting unit, A first delay element for delaying the input clock; A second delay element for delaying the output signal of the first delay element; A first transfer gate for transferring the input clock to the driving clock in response to the test-delay reduction signal; A second transfer gate for transmitting the output signal of the first delay element to the driving clock in response to the test-delay basic signal; A third transfer gate for transmitting an output signal of the second delay element to the driving clock in response to the test delay delay signal; Output control device comprising a. The method of claim 4, wherein The first and second delay elements, Output control device characterized in that the plurality of inverters are connected in series. The method according to any one of claims 1 to 5, Clock delay means for delaying and outputting the rising-DLL clock and the falling-DLL clock with a delay amount determined according to the corresponding cascade latency information signal; Selecting means for selecting a signal corresponding to the cascade latency information signal among the output signals of the clock delay means and applying it to an input clock of the test means; Output control device characterized in that. The method of claim 6, The clock delay means, A first clock delay unit for delaying the rising-DLL clock and the falling-DLL clock to output the plurality of first delay clocks according to the first cascade latency information signal; A second clock delay unit for delaying the rising-DLL clock and the falling-DLL clock to output a plurality of second delay clocks according to a second cascade latency information signal; A third clock delay unit configured to delay the rising-DLL clock and the falling-DLL clock and output the plurality of third delay clocks according to the third cascade latency information signal; And the delay amounts of the first to third clock delay units are different from each other. The method of claim 7, wherein The selection means, Outputting the plurality of first delay clocks to the plurality of input clocks when the first cascade latency information signal is activated, or outputting the plurality of second delay clocks to the input clocks when the second cascade latency information signal is activated Or outputting the plurality of third delay clocks to the input clock when the third cascade latency information signal is activated. The method of claim 8, The selection means, A first through a second clock corresponding to one of the plurality of first delay clocks, a second delay clock, and a third delay clock, and outputting one clock to a corresponding driving clock in response to the cascade latency information signal; Output control device comprising a six selector. The method of claim 9, The first selection unit, A fourth transfer gate for transferring a first clock of the plurality of first delay clocks upon activation of the first cascade latency information signal; A fifth transfer gate configured to transfer a first clock of the plurality of second delay clocks when the second cascade latency information signal is activated; A sixth transfer gate configured to transfer a first one of the plurality of third delayed clocks when the third cascade latency information signal is activated; And a first inverter for inverting a voltage across a common output node of the fourth to sixth transfer gates and outputting the voltage to the first driving clock. Output control device characterized in that. The method of claim 10, The initial synchronization unit, A deactivation controller for generating a deactivation control signal by receiving a column command and the internal clock; A first driver for driving an output node in response to the read cascade signal and the deactivation control signal; A first latch for inverting and latching a voltage applied to the output node and outputting the first output enable signal; And an initialization unit for initializing the output node during the power-up signal and the write drive. Initial synchronization means for outputting a first output enable signal upon activation of a read cas signal; Serially connected to output an output enable signal in synchronization with a corresponding drive clock, the first output means comprising: a plurality of synchronization means having the first output enable signal as an input; And Test means for outputting to the plurality of drive clocks by adjusting the delay amount of the selected signal of the input clock in response to a plurality of test off signal according to the test-delay amount control signal Output control device comprising a. The method of claim 12, The test means, When the corresponding signal among the plurality of test off signals is activated, the input clock is output as it is to the driving clock, When the corresponding test off signal is inactivated, the delay amount of each of the input clocks is increased or decreased according to a test-delay increase signal, a test-delay decrease signal, and a test-delay base signal to output to the driving clock. 1st to 6th delay amount adjusting unit Output control device comprising a. The method of claim 13, The first delay amount adjusting unit, A first delay element for delaying the driving clock; A second delay element for delaying the output signal of the first delay element; A first transfer gate for transferring the input clock to the driving clock in response to a first control signal; A second transfer gate for transferring an output signal of the first delay element to the driving clock in response to a second delay signal; A third transfer gate for transmitting an output signal of the second delay element to the driving clock in response to a third delay signal; A first controller configured to generate a first delay signal by receiving a first test off signal and the test delay delay signal as inputs; A second controller configured to generate a second delay signal by receiving a first test off signal and the test delay delay signal as inputs; And a third controller configured to generate a third delay signal by receiving a first test off signal and the test delay delay increasing signal as inputs. Output control device characterized in that. The method of claim 14, The first control unit may include a first NAND gate having the first test off signal and the test delay delay signal as an input, and a first signal for inverting an output signal of the first NAND gate to output the first control signal. With an inverter, The second control unit may include a second NAND gate having a first test off signal and the test delay delay signal as an input, and a second inverter for inverting an output signal of the second NAND gate to output the second control signal. Equipped with The third controller may include a third NAND gate having a first test off signal and the test delay delay signal as an input, and a third inverter for inverting an output signal of the third NAND gate to output the third control signal. Output control apparatus comprising a. The method of claim 15, The first and second delay elements, Output control device characterized in that the plurality of inverters are connected in series. The method according to any one of claims 12 to 16, Clock delay means for delaying and outputting the rising-DLL clock and the falling-DLL clock with a delay amount determined according to the corresponding cascade latency information signal; Selecting means for selecting a signal corresponding to the cascade latency information signal among the output signals of the clock delay means and applying it to an input clock of the test means; Output control device characterized in that. The method of claim 17, The clock delay means, A first clock delay unit for delaying the rising-DLL clock and the falling-DLL clock to output the plurality of first delay clocks according to the first cascade latency information signal; A second clock delay unit for delaying the rising-DLL clock and the falling-DLL clock to output a plurality of second delay clocks according to a second cascade latency information signal; A third clock delay unit configured to delay the rising-DLL clock and the falling-DLL clock and output the plurality of third delay clocks according to the third cascade latency information signal; And the delay amounts of the first to third clock delay units are different from each other. The method of claim 18, The selection means, Outputting the plurality of first delay clocks to the plurality of input clocks when the first cascade latency information signal is activated, or outputting the plurality of second delay clocks to the input clocks when the second cascade latency information signal is activated Or outputting the plurality of third delay clocks to the input clock when the third cascade latency information signal is activated. The method of claim 19, The selection means, A first through a second clock corresponding to one of the plurality of first delay clocks, a second delay clock, and a third delay clock, and outputting one clock to a corresponding driving clock in response to the cascade latency information signal; Output control device comprising a six selector. The method of claim 20, The first selection unit, A fourth transfer gate for transferring a first clock of the plurality of first delay clocks upon activation of the first cascade latency information signal; A fifth transfer gate configured to transfer a first clock of the plurality of second delay clocks when the second cascade latency information signal is activated; A sixth transfer gate configured to transfer a first one of the plurality of third delayed clocks when the third cascade latency information signal is activated; And a fourth inverter for inverting the voltage across the common output node of the fourth to sixth transfer gates and outputting the inverted voltage to the first driving clock. Output control device characterized in that. The method of claim 21, The initial synchronization unit, A deactivation controller for generating a deactivation control signal by receiving a column command and the internal clock; A driver for driving an output node in response to the read cascade signal and the deactivation control signal; A latch for inverting and latching a voltage applied to the output node to output the first output enable signal; And an initialization unit for initializing the output node during the power-up signal and the write drive. Serially connected and outputting a plurality of interval signals by synchronizing the output signal of the preceding stage with a corresponding drive clock, the first synchronization means comprising: a plurality of synchronization means having a flag signal as an input; And Test means for outputting to the drive clock by adjusting the delay amount of the input clock according to the test signal Output control device comprising a. The method of claim 23, wherein The test means, And a plurality of delay amount adjusting units for increasing or decreasing the delay amount of each of the input clocks according to the test-delay increase signal, the test-delay decrease signal, and the test-delay base signal, and output the driving delay signal to the driving clock. that Output control device characterized in that. The method of claim 24, The delay amount adjusting unit, When the test-base delay signal is activated, a basic delay is added to the corresponding input clock and output to the driving clock. When the test-delay increase signal is activated, a delay longer than the basic delay is added and output to the driving clock. And outputting the corresponding input clock to the driving clock as it is when the test delay signal is activated. The method of claim 25, The delay amount adjusting unit, A first delay element for delaying the input clock; A second delay element for delaying the output signal of the first delay element; A first transfer gate for transferring the input clock to the driving clock in response to the test-delay reduction signal; A second transfer gate for transmitting the output signal of the first delay element to the driving clock in response to the test-delay basic signal; A third transfer gate for transmitting an output signal of the second delay element to the driving clock in response to the test delay delay signal; Output control device comprising a. Serially connected and outputting a plurality of interval signals by synchronizing the output signal of the preceding stage with a corresponding drive clock, the first synchronization means comprising: a plurality of synchronization means having a flag signal as an input; And Test means for outputting to the plurality of drive clocks by adjusting only the delay amount of the selected signal of the input clock in response to a plurality of test off signal according to the test-delay amount control signal Output control device comprising a. The method of claim 27, The test means, When the corresponding signal among the plurality of test off signals is activated, the input clock is output as it is to the driving clock, When the corresponding test off signal is inactivated, the delay amount of each of the input clocks is increased or decreased according to a test-delay increase signal, a test-delay decrease signal, and a test-delay base signal to output to the driving clock. 1st to 6th delay amount adjusting unit Output control device comprising a. The method of claim 28, The first delay amount adjusting unit, A first delay element for delaying the driving clock; A second delay element for delaying the output signal of the first delay element; A first transfer gate for transferring the input clock to the driving clock in response to a first control signal; A second transfer gate for transferring an output signal of the first delay element to the driving clock in response to a second delay signal; A third transfer gate for transmitting an output signal of the second delay element to the driving clock in response to a third delay signal; A first controller configured to generate a first delay signal by receiving a first test off signal and the test delay delay signal as inputs; A second controller configured to generate a second delay signal by receiving a first test off signal and the test delay delay signal as inputs; And a third controller configured to generate a third delay signal by receiving a first test off signal and the test delay delay increasing signal as inputs. Output control device characterized in that. The method of claim 29, The first control unit may include a first NAND gate having the first test off signal and the test delay delay signal as an input, and a first signal for inverting an output signal of the first NAND gate to output the first control signal. With an inverter, The second control unit may include a second NAND gate having a first test off signal and the test delay delay signal as an input, and a second inverter for inverting an output signal of the second NAND gate to output the second control signal. Equipped with The third controller may include a third NAND gate having a first test off signal and the test delay delay signal as an input, and a third inverter for inverting an output signal of the third NAND gate to output the third control signal. Output control apparatus comprising a.

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