JP4751441B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that operates in synchronization with a clock signal.

  In recent years, semiconductor devices are required to perform processing at higher signal frequencies. For example, in a semiconductor memory device, an SDRAM (Synchronous Dynamic RAM), a DDR-SDRAM (Double Data Rate SDRAM), and the like operate in synchronization with an external clock signal as a CPU (Central Processing Unit) increases in speed. To achieve faster operation. Therefore, an input circuit of a semiconductor device to which a data signal or a clock signal is supplied from the outside is required to have a high speed and high accuracy as the clock signal speed increases.

  Hereinafter, an input circuit of a conventional semiconductor device will be described. Here, the operation of the input circuit of the DDR-SDRAM that realizes high speed by inputting / outputting the data signal in synchronization with the rising edge and falling edge of the clock signal will be described.

  FIG. 1 shows a configuration diagram of an example of an input circuit. The input circuit of FIG. 1 includes chip pads 12 and 14, input buffer circuits 16 and 18, and a latch circuit 20. The input buffer circuit 16 receives a clock signal having a constant period via the chip pad 12. The input buffer circuit 18 receives a data signal synchronized with the clock signal via the chip pad 14.

  The input buffer circuit 16 amplifies the input clock signal and supplies the clock signal to the latch circuit 20. The input buffer circuit 18 amplifies the input data signal and supplies the data signal to the latch circuit 20. The latch circuit 20 latches the data signal in synchronization with the rising edge of the supplied clock signal.

  Next, the operation of the input circuit will be described with reference to FIG. FIG. 2 shows a configuration diagram of an example of the input circuit. The input circuit of FIG. 2 includes chip pads 22 and 24, input buffer circuits 26 and 28, and latch circuits 30 and 32. The input buffer circuit 28 receives a clock signal having a fixed period via the chip pad 24. The input buffer circuit 26 receives a data signal synchronized with the clock signal via the chip pad 22.

  The input buffer circuit 28 branches the input clock signal into a clock signal DS0 output via the inverter two stages and a clock signal DS180 output via the inverter one stage. The input buffer circuit 28 supplies the clock signal DS0 to the latch circuit 30 and supplies the clock signal DS180 to the latch circuit 32. The input buffer circuit 26 amplifies the input data signal, branches the data, and supplies it to the latch circuits 30 and 32.

  The latch circuit 30 latches the data signal in synchronization with the rising edge of the supplied clock signal DS0. The latch circuit 32 latches the data signal in synchronization with the rising edge of the supplied clock signal DS180.

  However, it is inevitable that some process variations occur at the stage of manufacturing the semiconductor device. Further, in the input circuit of FIG. 2, when the clock signal is branched to generate the clock signals DS0 and DS180, a timing shift of one inverter stage occurs. Further, as will be described later, there is a case where a decoder configured by a logic circuit is provided in the latch circuit, and a timing shift corresponding to the logic circuit configuring the decoder occurs.

  Conventionally, this level of timing shift does not affect the operation of the input circuit and has no problem. However, by performing processing at a higher signal frequency, the allowable timing shift range is reduced. Therefore, timing deviations due to process variations and circuit configuration differences become a problem.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device capable of adjusting a timing difference between a clock signal and a data signal in an input circuit.

To solve the above problems, a semiconductor device of the present invention includes a first output circuit for force out I follow a data signal supplied is branched by the input buffer to the clock signal is supplied is branched by the input buffer A decoding circuit for decoding at least one data signal including a data signal, a second output circuit for outputting the decoded signal in accordance with a clock signal, and a first output circuit provided in front of the first output circuit. And a first delay circuit for delaying the supplied data signal.

  As described above, by including the first delay circuit, the first delay circuit can adjust the timing of the data signal that is not delayed by the decode circuit and the data signal that is delayed by the decode circuit. The first delay circuit can be realized by various configurations such as increasing the wiring length.

According to another aspect of the present invention, there is provided a semiconductor device including : a first output circuit that outputs a data signal branched and supplied from an input buffer according to a clock signal; and at least one data including a data signal branched and supplied from the input buffer. A decoding circuit for decoding a signal; a second output circuit for outputting the decoded signal according to a clock signal; a first delay circuit for delaying a clock signal supplied to the first output circuit; and the second output circuit. And a second delay circuit for delaying the supplied clock signal .

As described above, by including the first and second delay circuits, the clock signal can be delayed in consideration of the delay caused by the decoding process of the data signal. Therefore, it is possible to adjust the timing difference between the clock signal and the data signal due to the difference in circuit configuration.

According to another aspect of the present invention, there is provided a semiconductor device including : a first output circuit that outputs a data signal branched and supplied from an input buffer according to a clock signal; and at least one data including a data signal branched and supplied from the input buffer. characterized in that it comprises a decoding circuit for decoding a signal, a second output circuit for outputting the decoded signal in accordance with the clock signal, a first delay circuit Ru delays the clock signal supplied to the second output circuit And

Thus, by having a first delay circuit, it is possible to delay the clock signal in consideration of the delay caused by the decoding processing of the data signal. The first delay circuit is for delaying the clock signal supplied to the second output circuit. Therefore, it is possible to adjust the timing difference between the clock signal and the data signal due to the difference in circuit configuration.

According to another aspect of the present invention, there is provided a semiconductor device including : a first output circuit that outputs a data signal branched and supplied from an input buffer according to a clock signal; and at least one data including a data signal branched and supplied from the input buffer. A decoding circuit that decodes a signal; a second output circuit that outputs the decoded signal in accordance with a clock signal; and a data signal that is provided before the first output circuit and is supplied to the first output circuit. And a dummy decode circuit that delays the delay time based on the delay time .

  As described above, by including the dummy decoding circuit, the delay amount by the decoding circuit and the delay amount by the dummy decoding circuit can be adjusted. Therefore, it is possible to adjust the timing difference between the clock signal and the data signal due to the difference in circuit configuration.

  As described above, according to the present invention, by having the first delay circuit, the first delay circuit adjusts the timing of the data signal that is not delayed by the decode circuit and the data signal that is delayed by the decode circuit. Is possible. The first delay circuit can be realized by various configurations such as increasing the wiring length.

In addition, according to the present invention, the first and second delay circuits are provided, so that the clock signal can be delayed in consideration of the delay caused by the decoding process of the data signal. Therefore, it is possible to adjust the timing difference between the clock signal and the data signal due to the difference in circuit configuration.

Further, according to the present invention, by having a first delay circuit, it is possible to delay the clock signal in consideration of the delay caused by the decoding processing of the data signal. The first delay circuit is for delaying the clock signal supplied to the second output circuit. Therefore, it is possible to adjust the timing difference between the clock signal and the data signal due to the difference in circuit configuration.

  Further, according to the present invention, by including the dummy decoding circuit, the delay amount by the decoding circuit and the delay amount by the dummy decoding circuit can be adjusted. Therefore, it is possible to adjust the timing difference between the clock signal and the data signal due to the difference in circuit configuration.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, although SDRAM and DDR-SDRAM are demonstrated as an Example of this invention, it is not restricted to this.

  First, the entire configuration of the semiconductor device of the present invention will be described with reference to FIG. FIG. 3 shows a configuration diagram of an example of the semiconductor device of the present invention. 3 includes a clock buffer 40, a command decoder 42, an address buffer 44, a data input buffer circuit 46, a control signal latch circuit 48, a mode register 50, a column address counter 52, and a DLL (Delay Locked Loop) circuit 54. , And a core circuit 56.

  The function of each part constituting the semiconductor device will be briefly described. The clock buffer 40 receives an external clock signal CLK, an inverted clock signal / CLK, and the like, and supplies the clock signal CLK to each part.

  The command decoder 42 receives external commands such as a chip select signal / CS, a write command signal / WE, a signal / RAS, a signal / CAS, etc., and decodes the signals to control a control signal latch circuit 48 and a later-described signal. This is supplied to the data input buffer circuit 46.

  The address buffer 44 receives external address signals A0 to A12 and supplies the address signals to the control signal latch circuit 48, the mode register 50, the column address counter 52, and the core circuit 56. The data input buffer circuit 46 receives data signals DQ0 to DQ15 and the like from the outside, supplies data signals to the core circuit 56, receives data signals from the core circuit 56, and outputs data signals DQ0 to DQ15 to the outside. The data input buffer circuit 46 operates in synchronization with the clock signal supplied from the DLL circuit 54.

  The core circuit 56 follows the signals RAS, CAS, and WE supplied from the control signal latch circuit 48, the row address signal supplied from the address buffer 44, and the column address signal supplied from the column address counter 52. Data signals are read and written. The mode register 50 generates burst length information and supplies it to the column address counter 52.

The present invention particularly relates to an input circuit included in the data input buffer circuit 46, and will be described below.
[Adjustment of timing deviation due to process variation]
FIG. 4 shows a block diagram of a first embodiment of the input circuit included in the semiconductor device of the present invention. The input circuit of FIG. 4 is different from the input circuit of FIG. The test circuit 60 supplies a test signal to the input buffer circuits 16 and 18 and the latch circuit 20, and adjusts the timing difference between the clock signal and the data signal according to a procedure described later.

  In the example of FIG. 4, the input buffer circuit 18 to which the data signal is input is one example. However, when there are a plurality of input buffer circuits 18 to which the data signal is input, a plurality of input buffers are provided as shown in FIG. Different test signals may be supplied to the circuits 18-1 and 18-2, or a common test signal may be supplied to the plurality of input buffer circuits 18-1 and 18-2 as shown in FIG. .

  Next, the input buffer circuit 16 will be described with reference to FIG. FIG. 7 shows a configuration diagram of an embodiment of the input buffer circuit 16. The input buffer circuit 18 has the same configuration as that of the input buffer circuit 16, and a description thereof will be omitted.

  The input buffer circuit 16 in FIG. 7 includes a front stage unit 62 and a rear stage unit 64. The pre-stage unit 62 includes a current mirror circuit, and adjusts the reference current amount by turning on / off the switches mpsc1 to 3 and mnsc1 to 3, thereby adjusting the output current amount of the current mirror circuit.

  When the switches mpsc1 to 3 and mnsc1 to 3 are sequentially turned on, the output current amount increases, and the rising timing at the node N1 is advanced. On the other hand, when the switches mpsc1 to 3 and mnsc1 to 3 are sequentially turned off, the amount of output current decreases and the rising timing at the node N1 is delayed.

  The rear stage portion 64 is provided with an inverter in parallel, and one of the inverters is provided with a correction circuit. By providing the inverters in parallel as described above, it is possible to reduce the speed deterioration due to the provision of the correction circuit. The correction circuit is composed of two PMOS transistors and two NMOS transistors, and test signals ps1, 2 and ns1, 2 are connected to the gates of the respective transistors.

  When the correction circuit sequentially turns on each transistor using the test signals ps1, 2 and ns1, 2, the timing of the output signal is accelerated. On the other hand, when each transistor is turned off sequentially, the timing of the output signal is delayed. Since the PMOS and NMOS transistors can be controlled independently using the test signals ps1, 2 and ns1, 2, the output signal rise and fall can be adjusted independently. .

  Next, another modification of the front stage unit 62 of the input buffer circuit 16 of FIG. 7 will be described. 8 and 9 show configuration diagrams of other modified examples of the front stage portion 62. 8 and 9 adjusts a reference current amount by using a PMOS transistor and an NMOS transistor which are turned on / off by a test signal instead of the switches mpsc1 to 3 and mnsc1 to 3 in FIG. Adjust the output current of the circuit.

  Note that the test signal is supplied to the gates of the PMOS transistor and the NMOS transistor to perform ON / OFF control. 8 and 9 are different in the positions of PMOS transistors and NMOS transistors provided in place of the switches mpsc1 to 3 and mnsc1 to 3 in FIG.

  Next, another modification of the rear stage portion 64 of the input buffer circuit 16 in FIG. 7 will be described. Here, before describing another modification of the rear stage portion 64, the principle of another modification will be briefly described. FIG. 10 is a diagram illustrating an example of the principle of the rear stage portion 64.

  FIG. 10A is a configuration diagram of an example of a CR delay using an NMOS transistor and a PMOS transistor, and changing the High / Low duty ratio at the node by changing the capacitance of the NMOS transistor and the PMOS transistor. Is possible.

  This is because when the potential of the node exceeds Vthn (the threshold voltage of the NMOS transistor) in FIG. 10B, the NMOS transistor is turned on and has a capacity, and falls below VCC−Vthp (the threshold voltage of the PMOS transistor). This utilizes the characteristic that the PMOS transistor is turned on and has a capacitance. FIG. 10B is a waveform diagram of an example when the capacity of the PMOS transistor and the capacity of the NMOS transistor are the same.

  When the capacity of the NMOS transistor is increased from the state of FIG. 10B to reduce the capacity of the PMOS transistor (thick line in FIG. 10C), the capacity of the PMOS transistor is increased by reducing the capacity of the NMOS transistor. FIG. 10C shows an example waveform diagram of the case (dotted line in FIG. 10C).

  In the case of a thick line in FIG. 10C, the capacitance of the PMOS transistor is small and the NMOS transistor is not turned on at the time of rising, so that the speed is close to Vthn. At the time of falling, the capacity of the NMOS transistor is large, so it is slow to near VCC-Vthp.

  On the other hand, in the case of the dotted line in FIG. 10C, the NMOS transistor is OFF at the time of rising, but is slow to near Vthn because the capacity of the PMOS transistor is large. At the time of falling, the capacity of the NMOS transistor is small, so it is fast up to near VCC-Vthp.

  Therefore, when the signal in FIG. 10 is a thick line, the signal rises quickly to Vthn, so that the signal becomes high, and the signal that falls slowly to VCC-Vthp is slow. Also, in the case of the dotted line, since it rises slowly to Vthn, it becomes slow to become high, and it is fast to fall to VCC-Vthp, so it becomes fast to become low.

  As described above, it is possible to change the High / Low duty ratio at the node by changing the capacitances of the NMOS transistor and the PMOS transistor. FIG. 11 and FIG. A modification will be shown.

  Next, the latch circuit 20 will be described with reference to FIG. FIG. 13 shows a configuration diagram of an embodiment of the latch circuit 20. The latch circuit 20 in FIG. 13 includes a front stage unit 70 and a rear stage unit 72. The pre-stage unit 70 includes a CR delay using the NMOS transistor and the PMOS transistor described with reference to FIG. Another embodiment of the front stage 70 is shown in FIG. 14B and 14C show an embodiment for adjusting the resistance value R. FIG. Therefore, the pre-stage unit 70 can adjust the timing of the output signal by changing the capacitance of the NMOS transistor and the PMOS transistor.

  The rear stage unit 72 is supplied with a clock signal DS and a data signal DQ. Here, processing of each part of the rear stage unit 72 will be described using the timing chart of FIG. FIG. 15 is a timing chart of an example of the rear stage unit 72. FIG. 15A shows the clock signal DS input to the post-stage unit 72, FIG. 15B shows the input data signal DQ, and FIG. 15C shows the signal obtained by inverting the data signal DQ by the inverter. is there.

  Initially, when the clock signal DS in FIG. 15A is Low, the output signal in FIG. 15H remains Low. When the clock signal DS in FIG. 15A rises from Low to High, the data signal DQ in FIG. 15B is High, so that the node n02 is Low, the node n03 is High, the node n04 is High, and the node n05 becomes Low and the output signal becomes High.

  When the clock signal DS in FIG. 15A next rises from Low to High, the data signal DQ in FIG. 15B is Low, so that the node n02 is High, the node n03 is Low, and the node n04 is Low. , Node n05 becomes High, and the output signal becomes Low.

  As described above, in the latch circuit 20, the timing of the output signal can be adjusted by changing the capacitances of the NMOS transistor and the PMOS transistor in the front stage 70.

  Next, the operation of the test circuit 60 will be briefly described. The test circuit 60 can enter a special test mode (hereinafter simply referred to as a test mode) by inputting a command, and then can output a test signal. An example of a command to be entered in the test mode is shown in FIG.

  The command to enter the test mode in FIG. 16 indicates that entering the test mode by entering the command to enter the test mode after inputting MRS (mode register set) three times (each with a different code). It is preventing.

  Hereinafter, the test mode will be briefly described with reference to FIG. FIG. 17 shows an example illustrating the test mode. FIG. 17 simply shows the configuration necessary for the description of the test mode.

  The test circuit 60 of FIG. 7 includes a test decoder 81, a test decoder 82, and a test generator 83. The test generator 83 receives a MRS as shown in FIG. 16 and supplies a high signal to the test decoder 82.

  The test decoder 82 is composed of a plurality, and is selected according to the address A signal. The selected test decoder 82 latches the address B signal and outputs it to the test decoder 81. The test decoder 81 decodes the signal supplied from the address decoder 82 to generate each test signal, and supplies the test signal to the input buffer circuits 16 and 18 and the latch circuit 20.

  Each test signal can also be set by cutting a fuse (FUSE). The fuse is cut by cutting the fuse of the fuse cell 76, and the information is supplied from the fuse cell 76 to the test decoder 81. Therefore, the test signal is generated based on either the information of the fuse cell 76 or the address of the external input. Note that the test decoder 81 selects which of the information of the fuse cell 76 or the address of the external input is used to generate the test signal.

  The test decoders 81 and 82 and the test generator 83 will be further described with reference to FIGS. FIG. 18 shows a configuration diagram of an example of the test generator 83. FIG. 19 shows a configuration diagram of an example of the test decoder 82. FIG. 20 is a block diagram showing an example of the test decoder 81.

  In the test generator 20 of FIG. 18, when the commands for entering the test mode shown in FIG. 16 are sequentially input, the levels of the nodes 90, 91, 92, and 93 are sequentially High, and the High signal is supplied to the test decoder 82. . The signal mrs is a signal that becomes High when the MRS is input, the signal slt is a signal that becomes High when the power is turned on, the signal pre is a signal that becomes High when the PRE command is input, and the signal ref Is a signal that becomes High when a REF command is input. Also, z attached to the address signal indicates that it is in phase with the input signal, and x indicates that it is in phase with the input signal.

  The test decoder 82 of FIG. 19 is selected according to the address signals A1z to A5z and the signal supplied from the test generator 83. The selected test decoder 82 latches and outputs the address signals B1z and B2z. The signal preall is a reset signal.

  The test decoder 81 in FIG. 20 is supplied with signals F1 to F11 supplied from the fuse cell 76 and signals T0 to T11 supplied from the test decoder 82, and selects one of the signals according to the signal T0. Use. Therefore, the test signals P1 to P7 and N1 to P7 output from the test decoder 81 can be controlled by either the fuse cell 76 or an external input address.

  Next, a case where a buffer circuit is provided between the input buffer circuits 16 and 18 and the latch circuit 20 in FIG. 4 will be described with reference to FIG. FIG. 21 shows a block diagram of a second embodiment of the input circuit included in the semiconductor device of the present invention.

The input circuit of FIG. 21 is different from the input circuit of FIG. 4 in that it includes buffer circuits 95 and 96. The buffer circuits 95 and 96 are supplied with test signals, respectively, and can adjust the timing difference between the clock signal and the data signal by the technique described above.
[Adjustment of timing deviation due to difference in circuit configuration]
FIG. 22 is a block diagram showing a third embodiment of the input circuit included in the semiconductor device of the present invention. The input circuit of FIG. 22 includes an input buffer circuit 26 and latch circuits 30 and 32. Note that the latch circuit 32 is provided with a decoder 104 formed of a logic circuit.

  The input buffer circuit 26 has a current mirror circuit in the previous stage and is supplied with the data signal CMD1. The data signal CMD1 output from the current mirror circuit in the preceding stage is branched through the first inverter stage, one is further supplied to the latch circuit 30 through the third inverter stage, and the other is further latched through the second inverter stage. This is supplied to the circuit 32.

  The data signal CMD1 supplied to the latch circuit 32 is supplied via an inverter that is one stage lower than the data signal CMD1 supplied to the latch circuit 30. This is because the logic circuit that constitutes the decoder 104 provided in the latch circuit 32 is considered. Further, a pattern for increasing the wiring length is provided as the delay means 101 between the input buffer circuit 26 and the latch circuit 30.

  With the above configuration, the input circuit in FIG. 22 can adjust the timing of the signal at the node 102 of the latch circuit 30 and the timing at the node 103 of the latch circuit 32.

  Therefore, the latch circuits 30 and 32 can latch the signal at the rising timing of the capture signal clkmz generated from the clock signal, and the timing shift due to the difference in circuit configuration can be adjusted.

  23 to 24 show a configuration diagram of another embodiment of the input circuit of FIG. In FIG. 23A, delay means 105 and 106 are provided before the capture signal clkmz is supplied to the latch circuits 30 and 32. The input circuit of FIG. 23A can delay the fetch signal clkmz by providing the delay means 105 and 106, and can reliably latch after the decoding process.

  In FIG. 23B, the delay means 107 is provided before the latch signal 32 is supplied with the capture signal clkmz. The input circuit of FIG. 23B can delay the capture signal clkmz by providing the delay means 107, and can reliably latch after the decoding process.

  FIG. 23C shows a delay means 108 having a pattern in which the wiring length is increased before the latch signal 32 is supplied with the capture signal clkmz. Note that in the input circuit in FIG. 23C, the wiring is branched immediately after the driver to which the capture signal clkmz is supplied. Therefore, the input circuit of FIG. 23C can delay the capture signal clkmz by providing the delay means 108 and can reliably latch after the decoding process.

  FIG. 24A is different from the input circuit of FIG. 23C in that the wiring is not branched immediately after the driver to which the capture signal clkmz is supplied. Therefore, the input circuit of FIG. 24A can delay the capture signal clkmz by providing the delay means 108, and can reliably latch after the decoding process.

  The input circuit in FIG. 24B has a dummy decoder 109 in the latch circuit 30. By adjusting the delay by the dummy decoder 109 and the delay by the decoder 104, the timing of the output signal can be adjusted.

  FIG. 25 is a block diagram showing a fourth embodiment of the input circuit included in the semiconductor device of the present invention. The input circuit of FIG. 25 is different from the input circuit of FIG. 2 in that it has a delay means 110 constituted by an inverter.

  In the input circuit of FIG. 25, when the clock signal is branched and the clock signals DS0 and DS180 are generated, a timing shift corresponding to one stage of the inverter occurs. Therefore, the data signal supplied to the latch circuit 30 among the data signals output from the input buffer circuit 26 is delayed by the delay means 110.

  Therefore, it is possible to adjust the timing shift between the clock signal and the data signal in the latch circuits 30 and 32 by causing the data signal to generate a timing shift corresponding to one stage of the inverter included in the clock signals DS0 and DS180. It becomes.

  FIG. 26 shows another embodiment of the input circuit of FIG. The other embodiments of FIG. 26 are different in the supply method of the clock signals DS0 and DS180, but the effect is the same as that of the input circuit of FIG.

  FIG. 27 shows a configuration diagram of a fifth embodiment of the input circuit included in the semiconductor device of the invention. In the input circuit of FIG. 27, the clock signal having the same phase output from the input buffer circuit 28 is supplied to the latch circuits 30 and 120. The latch circuit 120 is characterized in that the logic is inverted from the logic of the latch circuit 30.

  Therefore, it is not necessary to create the clock signals DS0 and DS180 by an inverter, and the problem of timing deviation of the clock signals that has occurred when the clock signals DS0 and DS180 are created is eliminated.

  Note that the latch circuit 120 whose logic is inverted will be described with reference to FIG. FIG. 28 is a diagram illustrating an example of a latch circuit whose logic is inverted. FIG. 28 includes a latch circuit 30 located in the upper stage and a latch circuit 120 located in the lower stage.

  The logic of the latch circuit 120 is inverted from that of the latch circuit 30. Therefore, even if clock signals having the same phase are supplied, the operations of the latch circuit 30 and the latch circuit 120 are the same as when the clock signals DS0 and DS180 are supplied.

  As described above, according to the present invention, the problem of timing deviation of the clock signal that has occurred when the clock signals DS0 and DS180 are generated is eliminated. Therefore, it is possible to reduce the timing difference between the clock signal and the data signal in the input circuit.

  The clock buffer circuit described in the claims corresponds to the input buffer circuit 16, the data buffer circuit corresponds to the input data circuit 18, the output circuit corresponds to the latch circuit 20, and the control circuit corresponds to the test circuit 60. The buffer circuit corresponds to the buffer circuits 95 and 96, the first output circuit corresponds to the latch circuit 30, the decode circuit corresponds to the decoder 104, the second output circuit corresponds to the latch circuit 32, The delay circuit corresponds to the delay means 101, the second delay means corresponds to the delay means 105, 106, the third delay means corresponds to the delay means 107, the dummy decode circuit corresponds to the dummy decoder 109, The buffer circuit corresponds to the input buffer circuit 28, the third output circuit corresponds to the latch circuit 30, the first inversion means corresponds to the delay means 110, and the fourth output. Road corresponds to the latch circuit 30, the fifth output circuit corresponds to latch circuit 120.

It is a block diagram of an example of an input circuit. It is a block diagram of an example of an input circuit. It is a block diagram of an example of the semiconductor device of this invention. It is a block diagram of 1st Example of the input circuit contained in the semiconductor device of this invention. It is a figure of an example explaining the supply path | route of a test signal. It is a figure of an example explaining the supply path | route of a test signal. It is a block diagram of one Example of an input buffer circuit. It is a block diagram of the other modification of a front | former part. It is a block diagram of the other modification of a front | former part. It is a figure of an example explaining the principle of a back | latter stage part. It is a block diagram of the other modification of a back | latter stage part. It is a block diagram of the other modification of a back | latter stage part. It is a block diagram of one Example of a latch circuit. It is a block diagram of the other modification of a front | former part. It is a timing chart of an example of the latter part. It is a figure of an example of the command which enters into test mode. It is a figure of an example explaining test mode. It is a block diagram of an example of a test generator. It is a block diagram of an example of a test decoder. It is a block diagram of an example of a test decoder. It is a block diagram of 2nd Example of the input circuit contained in the semiconductor device of this invention. It is a block diagram of 3rd Example of the input circuit contained in the semiconductor device of this invention. It is a block diagram of the other Example of the input circuit of FIG. It is a block diagram of the other Example of the input circuit of FIG. It is a block diagram of 4th Example of the input circuit contained in the semiconductor device of this invention. FIG. 26 is a configuration diagram of another embodiment of the input circuit of FIG. 25. It is a block diagram of 5th Example of the input circuit contained in the semiconductor device of this invention. It is an example illustrating a latch circuit whose logic is inverted.

Explanation of symbols

12, 14 Chip pad 16, 18, 26, 28 Input buffer circuit 20, 30, 32, 120 Latch circuit 40 Clock buffer 42 Command decoder 44 Address buffer 46 Data input buffer 48 Control signal latch circuit 50 Mode register 52 Column address counter 54 DLL circuit 56 Core circuit 60 Test circuit 62, 70 Previous stage 64, 72 Rear stage 76 Fuse cell 81, 82 Test decoder 83 Test generator 95, 96 Buffer circuit 101 Delay means 104 Decoders 105-108, 110 Delay means 109 Dummy decoder

Claims (4)

A first output circuit for force out I follow the clock signal to the data signal supplied is branched by the input buffer,
A decoding circuit for decoding the at least one data signal comprising a data signal supplied is branched by the input buffer,
A second output circuit for outputting the decoded signal according to a clock signal;
A semiconductor device comprising: a first delay circuit provided before the first output circuit and delaying a data signal supplied to the first output circuit .   A first output circuit that outputs a data signal branched and supplied by an input buffer according to a clock signal;
  A decoding circuit for decoding at least one data signal including a data signal supplied by being branched by the input buffer;
  A second output circuit for outputting the decoded signal according to a clock signal;
  A first delay circuit for delaying a clock signal supplied to the first output circuit;
  A second delay circuit for delaying a clock signal supplied to the second output circuit;
A semiconductor device comprising: A first output circuit that outputs a data signal branched and supplied by an input buffer according to a clock signal;
A decoding circuit for decoding at least one data signal including a data signal supplied by being branched by the input buffer;
A second output circuit for outputting the decoded signal according to a clock signal;
A first delay circuit Ru delays the clock signal supplied to the second output circuit
A semiconductor device comprising: A first output circuit that outputs a data signal branched and supplied by an input buffer according to a clock signal;
A decoding circuit for decoding at least one data signal including a data signal supplied by being branched by the input buffer;
A second output circuit for outputting the decoded signal according to a clock signal;
A dummy decode circuit provided in front of the first output circuit and delaying a data signal supplied to the first output circuit by a delay time based on a delay time of the decode circuit;
A semiconductor device comprising:

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