KR100282230B1 - Manufacturing Method for Interconnection of Semiconductor Devices - Google Patents
Manufacturing Method for Interconnection of Semiconductor Devices Download PDFInfo
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- KR100282230B1 KR100282230B1 KR1019990004239A KR19990004239A KR100282230B1 KR 100282230 B1 KR100282230 B1 KR 100282230B1 KR 1019990004239 A KR1019990004239 A KR 1019990004239A KR 19990004239 A KR19990004239 A KR 19990004239A KR 100282230 B1 KR100282230 B1 KR 100282230B1
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- wiring
- copper
- opening
- forming
- insulating layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000010949 copper Substances 0.000 claims abstract description 88
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052802 copper Inorganic materials 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 34
- 230000004888 barrier function Effects 0.000 claims abstract description 21
- GCSJLQSCSDMKTP-UHFFFAOYSA-N ethenyl(trimethyl)silane Chemical compound C[Si](C)(C)C=C GCSJLQSCSDMKTP-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000009832 plasma treatment Methods 0.000 claims abstract description 7
- 239000005749 Copper compound Substances 0.000 claims abstract description 3
- 150000001880 copper compounds Chemical class 0.000 claims abstract description 3
- 229910004166 TaN Inorganic materials 0.000 claims description 3
- 229910004200 TaSiN Inorganic materials 0.000 claims description 3
- 229910008482 TiSiN Inorganic materials 0.000 claims description 3
- 229910008599 TiW Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 abstract description 16
- 239000005751 Copper oxide Substances 0.000 abstract description 3
- 229910000431 copper oxide Inorganic materials 0.000 abstract description 3
- 230000009931 harmful effect Effects 0.000 abstract description 3
- 238000001465 metallisation Methods 0.000 abstract description 2
- 238000005530 etching Methods 0.000 description 11
- 238000001020 plasma etching Methods 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000007789 gas Substances 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- IBXNCJKFFQIKKY-UHFFFAOYSA-N 1-pentyne Chemical compound CCCC#C IBXNCJKFFQIKKY-UHFFFAOYSA-N 0.000 description 2
- XNMQEEKYCVKGBD-UHFFFAOYSA-N 2-butyne Chemical compound CC#CC XNMQEEKYCVKGBD-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- QAMFBRUWYYMMGJ-UHFFFAOYSA-N hexafluoroacetylacetone Chemical compound FC(F)(F)C(=O)CC(=O)C(F)(F)F QAMFBRUWYYMMGJ-UHFFFAOYSA-N 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 125000005594 diketone group Chemical group 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- -1 for example Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- CWMFRHBXRUITQE-UHFFFAOYSA-N trimethylsilylacetylene Chemical group C[Si](C)(C)C#C CWMFRHBXRUITQE-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Abstract
본 발명은 반도체 장치의 배선 제조 방법에 관한 것으로서, 반도체 기판상에 제 1 절연층을 형성하는 공정과, 상기 제 1 절연층 내에 제 1 개구를 형성하는 공정과, 상기 제 1 개구에 배리아층으로 둘러싸인 제 1 배선을 다마신방법으로 형성하는 공정과, 상기 제 1 배선상에 적어도 1개 이상의 에치정지층을 포함하는 제 2 절연층을 형성하는 공정과, 상기 제 2 절연층 내에 제 2 개구를 형성하는 공정과, H2플라즈마 처리로 상기 제 2 개구의 측벽에 증착된 상기 제 1 배선의 산화막을 환원하여 상기 제 1 배선의 금속막을 형성하는 공정과, Cu(hfac)2와 TMVS(Trimethylvinylsilane)의 혼합가스를 이용하여 상기 제 1 배선의 금속막을 제거하는 공정과, 상기 제 2 개구에 상기 배리아층으로 둘러싸인 제 2 배선을 다마신방법으로 형성하는 공정을 구비한다. 따라서, 본 발명은 구리(Copper) 다마신 (Damascene)공정으로 형성된 배선과 비아(Via)를 포함하는 다층 구조의 메탈라이제이션에서 비아부의 구리화합물을 H2플라즈마처리방법으로 구리산화물로 환원시키고, Cu(hfac)2와 TMVS(Trimethylvinylsilane)의 혼합가스로 구리를 제거함으로 비아 저항을 낮춤과 동시에 비아 측벽의 구리(Cu)원자를 제거하여 구리의 해로운 효과를 방지할 수 있는 잇점이 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a wiring of a semiconductor device, the method comprising: forming a first insulating layer on a semiconductor substrate; forming a first opening in the first insulating layer; and a barrier layer in the first opening. Forming a first wiring enclosed by the damascene method, forming a second insulating layer including at least one etch stop layer on the first wiring, and a second opening in the second insulating layer. Forming a metal film of the first wiring by reducing an oxide film of the first wiring deposited on the sidewall of the second opening by H 2 plasma treatment; and forming Cu (hfac) 2 and TMVS (Trimethylvinylsilane). Removing the metal film of the first wiring by using a mixed gas; and forming a second wiring surrounded by the barrier layer in the second opening by a damascene method. Accordingly, the present invention is to reduce the copper compound of the via portion to the copper oxide by H 2 plasma treatment method in the metallization of the multilayer structure including the wiring (Via) and the wiring formed by the copper damascene process, By removing copper with a mixed gas of Cu (hfac) 2 and trimethylvinylsilane (TMVS), the via resistance is lowered and copper (Cu) atoms on the sidewalls of the via are removed to prevent harmful effects of copper.
Description
본 발명은 반도체 장치의 배선 제조 방법에 관한 것으로서, 특히, 구리(Copper) 다마신 (Damascene)공정으로 형성된 배선과 비아(Via)를 포함하는 반도체 장치의 배선 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring manufacturing method of a semiconductor device, and more particularly, to a wiring manufacturing method of a semiconductor device including wiring and vias formed by a copper damascene process.
반도체 장치의 제조공정에서 다층배선 구조는 소자의 설계 룰(Design Rule)이 1.0㎛ 이하로 축소됨에 따라 회로를 고밀도로 레이아웃 또는 배치하는 데 널리 채택하고 있다. 따라서, 집적회로의 제조공정에서 배선의 역할은 반도체 칩 레벨의 고밀도화 및 칩 크기의 증가화의 경향에 따라 더욱 더 중요하다. 실리콘 반도체의 금속 배선에 널리 사용되는 금속은 알루미늄이다. 알루미늄은 다른 금속 배선과 비교컨대 상대적으로 저 비용이며, 저 저항값을 가지며, 또한 에치(Etching)공정등 제조하기가 쉽다. 그러나 배선구조의 크기가 서브 마이크론(Sub-Micron)으로 작아짐에 따라, 배선의 선폭이 작아지며 상기 배선에서 전류밀도는 증가된다. 배선의 축소화 및 전류 밀도가 증가함에 따라, 알루미늄 배선의 전자이동(Electromigration) 수명은 열악해 진다. 반도체 다층 배선구조에서 유망한 금속인 구리는 알루미늄에 비하여 많은 장점을 갖고 있다. 예를 들면, 구리는 저 저항값, 높은 내 전자이동(Electromigration)특성을 갖고 있다. 구리를 증착하는 방법으로는 물리적 증착법(Physical Vapor Deposition, 이하 PVD 이라 칭함), 엘렉트로플레이팅(Electro-Plating)방법, 엘렉트로리스(Electroless)증착 방법등이 있다. 한편, 구리를 배선으로 사용할 때의 단점으로는 실리콘(Silicon)내에서 구리(Cu)의 빠른 확산 이동 및 실리콘산화막 절연층에서 드리프트(Drift)등으로 반도체 소자를 열악하게 한다. 그러므로 확산 방지층(Diffusion Barrier)을 사용하는 것이 매우 바람직하며, 필요하다.In the manufacturing process of a semiconductor device, a multilayer wiring structure is widely adopted for laying out or arranging a circuit at high density as a design rule of a device is reduced to 1.0 μm or less. Therefore, the role of the wiring in the manufacturing process of the integrated circuit is even more important according to the tendency of increasing the density of the semiconductor chip level and increasing the chip size. The metal widely used for metal wiring of a silicon semiconductor is aluminum. Aluminum has a relatively low cost, low resistance, and is easy to manufacture, for example, an etching process, compared to other metal wires. However, as the size of the wiring structure is reduced to sub-micron, the line width of the wiring is reduced and the current density in the wiring is increased. As wiring shrinks and current density increases, the electromigration life of aluminum wiring becomes poor. Copper, a promising metal in semiconductor multilayer interconnection structures, has many advantages over aluminum. For example, copper has a low resistance value and high electromigration characteristics. Methods of depositing copper include physical vapor deposition (hereinafter referred to as PVD), electro-plating, and electroless deposition. On the other hand, the disadvantages of using copper as a wiring make the semiconductor device poor due to the rapid diffusion movement of copper (Cu) in silicon and the drift in the silicon oxide insulating layer. Therefore, it is highly desirable and necessary to use a diffusion barrier.
도 1a 내지 도 1d는 종래 기술에 따른 반도체 장치의 배선의 제조 공정도이다.1A to 1D are manufacturing process diagrams of wirings of a semiconductor device according to the prior art.
도 1a를 참조하면, 반도체기판(11)에 제 1 절연층(13)을 증착 형성하고, 이어서 제 1 절연층의 소정부를 식각한 후 구리(Cu) 다마신(Damascene)방법으로 제 1 배선(Interconnection Wiring)(17)을 형성한다. 이어서 제 2 및 제 3 및 제 4 절연층 (21)(23)(25)을 반도체 기판 전체 표면에 증착 형성한다. 제 1 포토레지스트(Photo Resist)마스크(101)가 제 4 절연층(25)상에 형성된다. 제 1 RIE (Reactive Ion Etching, 이하 RIE 이라 칭함)이방성 에칭으로 제 1 개구(Opening)가 제 4 절연층(25)내에 형성되며, 상기 제 1 RIE 에칭으로 에치정지층(Etching Stop Layer)인 제 3 절연층은 식각되지 않는다. 제 1 개구의 크기는 비아(Via)의 크기와 같은 정도이다.Referring to FIG. 1A, a first insulating layer 13 is deposited on a semiconductor substrate 11, and then a predetermined portion of the first insulating layer is etched, followed by first wiring by a copper (Cu) damascene method. (Interconnection Wiring) 17 is formed. Subsequently, second and third and fourth insulating layers 21, 23 and 25 are deposited on the entire surface of the semiconductor substrate. A first photoresist mask 101 is formed on the fourth insulating layer 25. A first opening is formed in the fourth insulating layer 25 by a first reactive ion etching (RIE) anisotropic etching, and the first stop is an etching stop layer by the first RIE etching. 3 The insulating layer is not etched. The size of the first opening is about the same as the size of the via.
상기에서 제 1 배선(17)의 하부 및 측부 및 상부는 실리콘산화막 및 실리콘내로 구리의 확산을 방지하는 배리어층(Barrier Layer)(도시 안 함)으로 둘러싸여 있다(Encapsulate). 상기 배리어층으로는 Ta, W, Mo, TiN, TiW, TaN, TiSiN, WN,TaSiN, 등을 포함한다. 제 1 및 제 2 및 제 4 절연층(13)(21)(25)은 실리콘산화막(SiO2)이며, 제 3 절연층(23)은 실리콘질화막(Si3N4) 또는 실리콘산화질화막(SiOXNY)또는 다결정실리콘(Polycrystalline Silicon)으로 에칭정지층(Etching Stop Layer)으로 사용된다.In the above, the lower part, the side part and the upper part of the first wiring 17 are encapsulated by a barrier layer (not shown) which prevents diffusion of copper into the silicon oxide film and the silicon. The barrier layer includes Ta, W, Mo, TiN, TiW, TaN, TiSiN, WN, TaSiN, and the like. The first, second and fourth insulating layers 13, 21 and 25 are silicon oxide films (SiO 2 ), and the third insulating layer 23 is silicon nitride films (Si 3 N 4 ) or silicon oxynitride films (SiO). X N Y ) or polycrystalline silicon is used as an etching stop layer.
도 1b를 참조하면, 제 1 포토레지스트(Photo Resist)마스크(101)를 제거한 후 제 2 포토레지스트(Photo Resist)마스크(102)가 제 4 절연층(25)상에 형성된다. 제 2 RIE 에칭으로 제 1 개구를 포함하는 트렌치(Trench)가 제 4 절연층(25)내에 형성되며, 허선에서 보인 것과 같이 상기 제 1 개구는 제 3 및 제 2 절연층내로 연장된다.Referring to FIG. 1B, after removing the first photoresist mask 101, a second photoresist mask 102 is formed on the fourth insulating layer 25. A trench including a first opening is formed in the fourth insulating layer 25 by a second RIE etch, and the first opening extends into the third and second insulating layers as shown in dashed lines.
도 1c를 참조하면, 트렌치가 제 4 절연층(25)내에 형성되며, 동시에 상기 제 1 개구는 에칭정지층인 제 3 절연층(23) 및 제 2 절연층(21)내로 연장된다. 이어서 PVD 방법으로 배리어층(Barrier Layer)과 구리(Cu)를 연속적으로 증착하기 전에 제 1 배선(17)인 구리(Cu)표면에 생긴 산화물(예, Cu2O, CuO)을 상기 PVD 장치의 아르곤(Ar)스퍼터 에치(Sputter Etch)공정 스텝(Step)에서 구리 산화물을 제거한다. 상기 스퍼터 에치공정으로 인하여 구리표면의 산화물 CuOX및 Cu (27) 가 동시에 트렌치 및 제 1 개구의 측벽(Sidewall)에 증착된다.Referring to FIG. 1C, a trench is formed in the fourth insulating layer 25 and at the same time the first opening extends into the third insulating layer 23 and the second insulating layer 21, which are etch stop layers. Subsequently, oxides (eg, Cu 2 O, CuO) formed on the surface of the copper (Cu), which is the first wiring 17, are deposited before successively depositing a barrier layer and copper (Cu) by the PVD method. In the argon (Ar) sputter etch process step, the copper oxide is removed. Due to the sputter etch process, oxides CuO X and Cu 27 on the copper surface are simultaneously deposited on the trench and sidewalls of the first opening.
상기에서 구리(Cu)는 다른 배선 금속의 산화 예를 들면 알루미늄의 산화와는 달리 200℃미만의 낮은 온도에서도 쉽게 Cu2O, CuO 의 산화물로 형성되며, 구리의 추가 산화를 방지할 어떤 자기보호(Self-Protective) 산화막도 형성 할 수 없다.In the above, copper (Cu) is easily formed as an oxide of Cu 2 O, CuO even at the low temperature of less than 200 ℃ unlike oxidation of other wiring metals, for example, aluminum, any self-protection to prevent further oxidation of copper (Self-Protective) Oxide can not be formed.
도 1d를 참조하면, 상기 PVD 장치에서 배리어층(Barrier Layer)(29)과 구리(Cu)(31)를 인-시튜(In-Situ)방법으로 연속 증착한다. 이어서 배리어층(Barrier Layer)(29)과 구리(Cu)(31)층의 과잉 부분(Excess Portion)을 CMP(Chemical Mechanical Polishing, 이하 CMP 이라 칭함)방법으로 제거한다. 이때 제 4 절연층(25)은 에치/폴리시(Etch/ Polish) 정지층으로 사용된다. 이어서 제 2 배선인 구리(31)의 상부를 씌울(Cap) 배리어층(31)을 증착 형성한다. 이어서 패시베이션 층 (Passivation Layer)(도시 안 함)을 증착 형성한다.Referring to FIG. 1D, a barrier layer 29 and a copper 31 are continuously deposited in an in-situ method in the PVD apparatus. Subsequently, excess portions of the barrier layer 29 and the copper (Cu) 31 layer are removed by a chemical mechanical polishing (CMP) method. In this case, the fourth insulating layer 25 is used as an etch / polish stop layer. Subsequently, a cap barrier layer 31 covering the upper portion of the copper 31, which is the second wiring, is deposited. Subsequently, a passivation layer (not shown) is deposited.
상기에서 아르곤(Ar) 스퍼터 에치(Sputter Etch)공정시 트렌치 및 제 1개구의 측벽에 증착된 CuOX및 Cu (27)는 배리어층(29)의 바깥(Outside) 즉, 실리콘산화막내에 존재하게 됨으로 이후 열처리 공정(Subsequent Thermal Processing)시 소자특성에 해로운 불순물인 구리(Cu)원자는 실리콘산화막 및 실리콘 내로 확산 이동되어 소자의 신뢰성을 악화시킨다.In the argon (Sp) sputter etch process, CuO X and Cu 27 deposited on the sidewalls of the trench and the first opening are located outside of the barrier layer 29, that is, in the silicon oxide film. Subsequent thermal processing (Cu) atoms, which are impurities that are detrimental to device characteristics, are diffused and transferred into the silicon oxide film and silicon, thereby deteriorating the reliability of the device.
상술한 종래 기술에 따른 구리 배선 및 비아(Via)를 포함하는 배선의 제조공정에서 구리배선상의 산화막 제거 방법으로 사용되는 아르곤 가스를 이용한 스퍼터링 에칭 스텝은 비아 및 트렌치 측벽에 CuOX및 Cu를 증착시키고, 이후 열처리 공정(Subsequent Thermal Processing)시 소자특성에 해로운 불순물인 구리(Cu)원자는 실리콘산화막 및 실리콘 내로 확산 이동되어 소자의 신뢰성을 악화시키는 문제점이 있었다.The sputtering etching step using argon gas, which is used as a method of removing an oxide film on a copper wiring, in the manufacturing process of the wiring including the copper wiring and the via according to the related art, deposits CuO X and Cu on the via and trench sidewalls. In the subsequent thermal processing, copper (Cu) atoms, which are impurities that are harmful to device characteristics, are diffused into the silicon oxide film and silicon, thereby deteriorating the reliability of the device.
따라서, 본 발명의 목적은 신뢰성 있는 구리(Copper) 다마신(Damascene)공정으로 형성된 배선과 비아(Via)를 포함하는 반도체 장치의 배선의 제조 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a wiring of a semiconductor device including wiring and vias formed by a reliable copper damascene process.
상기 목적을 달성하기 위한 본 발명에 따른 반도체 장치의 배선의 제조방법은 반도체 기판상에 제 1 절연층을 형성하는 공정과, 상기 제 1 절연층 내에 제 1 개구를 형성하는 공정과, 상기 제 1 개구에 배리아층으로 둘러싸인 제 1 배선을 다마신방법으로 형성하는 공정과, 상기 제 1 배선상에 적어도 1개 이상의 에치정지층을 포함하는 제 2 절연층을 형성하는 공정과, 상기 제 2 절연층 내에 제 2 개구를 형성하는 공정과, H2플라즈마 처리로 상기 제 2 개구의 측벽에 증착된 상기 제 1 배선의 산화막을 환원하여 상기 제 1 배선의 금속막을 형성하는 공정과, Cu(hfac)2와 TMVS(Trimethylvinylsilane)의 혼합가스를 이용하여 상기 제 1 배선의 금속막을 제거하는 공정과, 상기 제 2 개구에 상기 배리아층으로 둘러싸인 제 2 배선을 다마신방법으로 형성하는 공정을 구비한다.According to an aspect of the present invention, there is provided a method of manufacturing a wiring for a semiconductor device, the method comprising: forming a first insulating layer on a semiconductor substrate; forming a first opening in the first insulating layer; Forming a first wiring surrounded by a barrier layer in the opening by a damascene method, forming a second insulating layer including at least one or more etch stop layers on the first wiring, and the second insulation Forming a second opening in the layer, reducing an oxide film of the first wiring deposited on the sidewall of the second opening by H 2 plasma treatment, and forming a metal film of the first wiring; Cu (hfac) using a gas mixture of 2 and TMVS (Trimethylvinylsilane) and the step of removing the metal film of the first wiring line, comprising a step of forming the second opening in a damascene method for the second wiring layer is surrounded by the ship Ria .
도 1a 내지 도 1d는 종래 기술에 따른 반도체 장치의 배선의 제조 공정도이다.1A to 1D are manufacturing process diagrams of wirings of a semiconductor device according to the prior art.
도 2a 내지 도 2d는 본 발명에 따른 반도체 장치의 배선의 제조 공정도이다.2A to 2D are manufacturing process diagrams of wirings of the semiconductor device according to the present invention.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 반도체 장치의 배선의 제조 공정도이다.2A to 2E are manufacturing process diagrams of wirings of the semiconductor device according to the present invention.
도 2a를 참조하면, 반도체기판(61)에 제 1 절연층(63)을 증착 형성하고, 이어서 제 1 절연층의 소정부를 식각한 후 구리(Cu) 다마신(Damascene)방법으로 제 1 배선(Interconnection Wiring)(67)을 형성한다. 이어서 제 2 및 제 3 및 제 4 절연층 (71)(73)(75)을 반도체 기판 전체 표면에 증착 형성한다. 제 1 포토레지스트(Photo Resist)마스크(201)가 제 4 절연층(75)상에 형성된다. 제 1 RIE (Reactive Ion Etching, 이하 RIE 이라 칭함)이방성 에칭으로 제 1 개구(Opening)가 제 4 절연층(75)내에 형성되며, 상기 제 1 RIE 에칭으로 에치정지층(Etching Stop Layer)인 제 3 절연층은 식각되지 않는다. 제 1 개구의 크기는 비아(Via)의 크기와 같은 정도이다.Referring to FIG. 2A, a first insulating layer 63 is deposited on a semiconductor substrate 61, and then a predetermined portion of the first insulating layer is etched, and then the first wiring is formed by a copper damascene method. (Interconnection Wiring) 67 is formed. Subsequently, second and third and fourth insulating layers 71, 73 and 75 are deposited on the entire surface of the semiconductor substrate. A first photoresist mask 201 is formed on the fourth insulating layer 75. A first opening is formed in the fourth insulating layer 75 by a first reactive ion etching (RIE) anisotropic etching, and the first stop is an etching stop layer by the first RIE etching. 3 The insulating layer is not etched. The size of the first opening is about the same as the size of the via.
상기에서 제 1 배선(67)의 하부 및 측부 및 상부는 실리콘산화막 및 실리콘내로 구리의 확산을 방지하는 배리어층(Barrier Layer)(도시 안 함)으로 둘러싸여 있다(Encapsulate). 상기 배리어층으로는 Ta, W, Mo, TiN, TiW, TaN, TiSiN, WN,TaSiN, Si3N4.,CoWP 등을 포함한다. 제 1 및 제 2 및 제 4 절연층(63)(71)(75)은 실리콘산화막(SiO2)이며, 제 3 절연층(73)은 실리콘질화막(Si3N4) 또는 실리콘산화질화막(SiOXNY)또는 다결정실리콘(Polycrystalline Silicon)으로 에칭정지층(Etching Stop Layer)으로 사용된다.In the above, the lower part, the side part, and the upper part of the first wiring 67 are encapsulated by a barrier layer (not shown) which prevents diffusion of copper into the silicon oxide film and the silicon. The barrier layer includes Ta, W, Mo, TiN, TiW, TaN, TiSiN, WN, TaSiN, Si 3 N 4, CoWP and the like. The first, second and fourth insulating layers 63, 71 and 75 are silicon oxide films (SiO 2 ), and the third insulating layer 73 is silicon nitride films (Si 3 N 4 ) or silicon oxynitride films (SiO). X N Y ) or polycrystalline silicon is used as an etching stop layer.
도 2b를 참조하면, 제 1 포토레지스트(Photo Resist)마스크(201)를 제거한 후 제 2 포토레지스트(Photo Resist)마스크(202)가 제 4 절연층(75)상에 형성된다. 제 2 RIE 에칭으로 제 1 개구를 포함하는 트렌치(Trench)가 제 4 절연층(75)내에 형성되며, 허선에서 보인 것과 같이 상기 제 1 개구는 제 3 및 제 2 절연층내로 연장된다.Referring to FIG. 2B, after removing the first photoresist mask 201, a second photoresist mask 202 is formed on the fourth insulating layer 75. A trench including a first opening is formed in the fourth insulating layer 75 by a second RIE etch, and the first opening extends into the third and second insulating layers as shown in dashed lines.
도 2c를 참조하면, 트렌치가 제 4 절연층(75)내에 형성되며, 동시에 상기 제 1 개구는 에칭정지층인 제 3 절연층(73) 및 제 2 절연층(71)내로 연장된다. 상기 RIE 에칭으로 제 1 배선(67)인 구리(Cu) 표면은 앰비언트(Ambient)에 노출 산화되어 산화막 CuOx층(72)으로 형성된다. 동시에 트렌치 및 제 1 개구의 측벽에 있는 구리(Cu)도 산화막 CuOx층(72)으로 형성된다Referring to FIG. 2C, a trench is formed in the fourth insulating layer 75, and at the same time the first opening extends into the third insulating layer 73 and the second insulating layer 71, which are etch stop layers. By the RIE etching, the surface of the copper (Cu), which is the first wiring 67, is exposed and oxidized to an ambient to form an oxide film CuO x layer 72. At the same time, copper (Cu) on the sidewalls of the trench and the first opening is also formed of an oxide film CuO x layer 72.
이어서 H2플라즈마(Plasma) 처리방법으로 상기 CuOx층을 환원시켜 Cu를 형성한다. 산화물 CuO, Cu2O 과 H2와의 반응식은 아래와 같다.Subsequently, the CuO x layer is reduced by H 2 plasma treatment to form Cu. The reaction formula of the oxides CuO, Cu 2 O and H 2 is as follows.
CuO(s)＋ H2(g)→ Cu(s)＋ H2O(g),ΔG ＜ 0CuO (s) + H 2 (g) → Cu (s) + H 2 O (g) , ΔG <0
Cu2O(s)＋ H2(g)→ 2Cu(s)＋ H2O(g),ΔG ＜ 0 이다.Cu 2 O (s) + H 2 (g) → 2Cu (s) + H 2 O (g), ΔG <0.
상기 반응은 발열반응으로 열역학적으로 자발적인 반응이다.The reaction is exothermic and is thermodynamically spontaneous.
이어서 Cu+2(hfac)2와 루이스(Lewis)기(Base) 인 TMVS(Trimethylvinylsilane)의 혼합가스를 이용하여 제 1 배선인 구리표면 및 트렌치 및 제 1 개구의 측벽에 있는 구리(Cu)를 제거한다. 상기 반응식은 아래와 같다.Subsequently, a mixed gas of Cu +2 (hfac) 2 and a Lewis group (TMVS) trimethylvinylsilane (TMVS) is used to remove copper (Cu) at the first wiring, the copper surface and the trench, and the sidewalls of the first opening. do. The reaction scheme is as follows.
Cu(hfac)2(g)＋ 2 L(g)＋ Cu(s)→ 2 Cu(hfac)L(g) Cu (hfac) 2 (g) + 2 L (g) + Cu (s) → 2 Cu (hfac) L (g)
여기서, L 은 중성 루이스 기(Neutral Lewis Base)이다.Where L is a Neutral Lewis Base.
상기 반응으로 고체상태의 구리(Cu)는 Cu(hfac)L 형태의 기체(Gas)로 제거된다.The reaction removes solid copper (Cu) with a gas (Gas) in the form of Cu (hfac) L.
상기에서 제 1 배선물질인 구리(Cu)는 다른 금속의 산화 예를 들면 알루미늄의 산화와는 달리 200℃미만의 낮은 온도에서 쉽게 Cu2O, CuO 의 산화물로 형성되며, 구리의 추가 산화를 방지할 어떤 자기보호(Self-Protective) 산화막도 형성 할 수 없다. CuO 및/또는 Cu2O 환원공정은 수소(H2)어닐링 처리방법으로 형성 할 수 있다.Copper (Cu), the first wiring material, is easily formed of oxides of Cu 2 O and CuO at a temperature lower than 200 ° C, unlike oxidation of other metals, for example, oxidation of aluminum, and prevents further oxidation of copper. No self-protective oxide can be formed. CuO and / or Cu 2 O reduction process may be formed by a hydrogen (H 2 ) annealing treatment method.
Cu+2(hfac)2는 베타-다이케톤(Beta Diketone)계열의 가스 hfac(Hexafluoroacetylacetone)를 Cu 산화물과 반응하여 얻을 수 있다.Cu +2 (hfac) 2 can be obtained by reacting beta-diketone series gas hfac (Hexafluoroacetylacetone) with Cu oxide.
hfac(Hexafluoroacetylacetone)와 Cu 산화물과의 반응식은 아래와 같다.The reaction between hfac (Hexafluoroacetylacetone) and Cu oxide is shown below.
CuO(s)＋ 2hfac(g)→ Cu(hfac)2(g)＋ H2O(g) CuO (s) + 2hfac (g) → Cu (hfac) 2 (g) + H 2 O (g)
Cu2O(s)＋ 2hfac(g)→ Cu(hfac)2(g)＋ Cu(s)＋ H2O(g) Cu 2 O (s) + 2 hfac (g) → Cu (hfac) 2 (g) + Cu (s) + H 2 O (g)
Cu+2(hfac)2와 루이스(Lewis)기(Base) 인 TMVS(Trimethylvinylsilane)의 상세한 내용은 미국특허 5,094,701 과 1991년 VMIC(VLSI and Multilevel Interconnectioin)콘퍼런스(Conference) 123p. 에 설명되어 있다. 그리고 베타-다이케톤(Beta Diketone)의 상세한 설명은 미국특허 5,094,701에 개시되어 있다.For details of Cu +2 (hfac) 2 and Lewis group-based trimethylvinylsilane (TMVS), see US Pat. No. 5,094,701 and 1991 VML (VLSI and Multilevel Interconnectioin) Conference 123p. Described in And a detailed description of Beta Diketone is disclosed in US Pat. No. 5,094,701.
중성 루이스 기(Neutral Lewis Base)인 L 에는 TMVS를 포함하여 2-butyne, pentyne, bis(Trimethylsilylacetylene) 등이 있다.Neutral Lewis Base L contains 2-butyne, pentyne, bis (Trimethylsilylacetylene), including TMVS.
도 2d를 참조하면, PVD 장치에서 배리어층(Barrier Layer)(79)과 구리(Cu)(81)를 연속적으로 증착한다. 이어서 배리어층(Barrier Layer)(79)과 구리(Cu)(81)층의 과잉 부분을 CMP(Chemical Mechanical Polishing, 이하 CMP 이라 칭함)방법으로 제거한다. 제 4 절연층(75)은 에치/폴리시(Etch/ Polish) 정지층으로 사용된다. 이어서 제 2 배선인 구리(81)의 상부를 씌울(Cap) 배리어층(81)을 증착 형성한다. 이어서 패시베이션 층 (Passivation Layer)(도시 안 함)을 증착 형성한다.Referring to FIG. 2D, a barrier layer 79 and copper 81 are successively deposited in a PVD device. Subsequently, excess portions of the barrier layer 79 and the copper (Cu) 81 layer are removed by a chemical mechanical polishing (CMP) method. The fourth insulating layer 75 is used as an etch / polish stop layer. Subsequently, a cap barrier layer 81 covering the upper portion of the copper 81, which is the second wiring, is deposited. Subsequently, a passivation layer (not shown) is deposited.
상술한 바와 같이 본 발명에 따른 반도체 장치의 배선의 제조 방법은 반도체 기판상에 제 1 절연층을 형성하며, 상기 제 1 절연층 내에 제 1 개구를 형성하며, 상기 제 1 개구에 배리아층으로 둘러싸인 제 1 배선을 다마신방법으로 형성하며, 상기 제 1 배선상에 적어도 1개 이상의 에치정지층을 포함하는 제 2 절연층을 형성하며, 상기 제 2 절연층 내에 제 2 개구를 형성하며, H2플라즈마 처리로 상기 제 2 개구의 측벽에 증착된 상기 제 1 배선의 산화막을 환원하여 상기 제 1 배선의 금속막을 형성하며, Cu(hfac)2와 TMVS(Trimethylvinylsilane)의 혼합가스를 이용하여 상기 제 1 배선의 금속막을 제거하며, 상기 제 2 개구에 상기 배리아층으로 둘러싸인 제 2 배선을 다마신방법으로 형성한다.As described above, in the method for manufacturing a wiring of a semiconductor device according to the present invention, a first insulating layer is formed on a semiconductor substrate, a first opening is formed in the first insulating layer, and a barrier layer is formed in the first opening. Forming an enclosed first wiring by a damascene method, forming a second insulating layer including at least one etch stop layer on the first wiring, forming a second opening in the second insulating layer, and H 2 plasma treatment reduces the oxide film of the first wiring deposited on the sidewall of the second opening to form a metal film of the first wiring, and uses the mixed gas of Cu (hfac) 2 and TMVS (Trimethylvinylsilane). The metal film of one wiring is removed, and the second wiring surrounded by the barrier layer is formed in the second opening by a damascene method.
따라서, 본 발명은 구리(Copper) 다마신 (Damascene)공정으로 형성된 배선과 비아(Via)를 포함하는 다층 구조의 메탈라이제이션에서 비아부의 구리화합물을 H2플라즈마처리방법으로 구리산화물로 환원시키고, Cu(hfac)2와 TMVS(Trimethylvinylsilane)의 혼합가스로 구리를 제거함으로 비아 저항을 낮춤과 동시에 비아 측벽의 구리(Cu)원자를 제거하여 구리의 해로운 효과를 방지할 수 있는 잇점이 있다.Accordingly, the present invention is to reduce the copper compound of the via portion to the copper oxide by H 2 plasma treatment method in the metallization of the multilayer structure including the wiring (Via) and the wiring formed by the copper damascene process, By removing copper with a mixed gas of Cu (hfac) 2 and trimethylvinylsilane (TMVS), the via resistance is lowered and copper (Cu) atoms on the sidewalls of the via are removed to prevent harmful effects of copper.
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