KR20020043464A - The method of fabrication of metal line structure - Google Patents
The method of fabrication of metal line structure Download PDFInfo
- Publication number
- KR20020043464A KR20020043464A KR1020020015499A KR20020015499A KR20020043464A KR 20020043464 A KR20020043464 A KR 20020043464A KR 1020020015499 A KR1020020015499 A KR 1020020015499A KR 20020015499 A KR20020015499 A KR 20020015499A KR 20020043464 A KR20020043464 A KR 20020043464A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- copper
- film
- copper oxide
- oxide film
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 금속배선 형성 방법에 관한 것으로, 특히 구리(Cu) 배선 형성방법에 관한 것이다. 구리는 Al이나 Al-Si-Cu 합금보다 낮은 비저항을 갖는다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring of a semiconductor device, and more particularly to a method for forming copper (Cu) wiring. Copper has a lower resistivity than Al or Al-Si-Cu alloys.
이러한 이유로 구리는 테플론(Teflon)과 같은 폴리머 기판위에 배선 물질로사용되고 있으며, 이는 프린트기판 제조분야에서는 기초가 되는 공정이다. 구리는 집적회로에서 사용되는 다른 재료와의 상호작용 가능성(이는 구리의 Si나 SiO₂에 대한 확산계수가 매우 높기 때문이다)이 있음으로 해서 고집적회로 제조에서는 배제되어 왔다. 따라서 Cu를 소자에 성공적으로 적용하기 위해서는 구리와 Si나 SiO₂ 사이에 확산방지층으로 배리어층(barrier layer)을 설치할 필요가 있다. 최근에 집적도 증가와 확산배리어기술의 진보가 계속됨에 따라 구리는 점차 향후 IC제조 공정에서 적용될 수 있을 것으로 판단되고 있다. 구리의 확산배리어층 물질로는 TiN, TaN, 그리고 WN등이 있다. 그리고 고집적 IC소자에서는 빠른 응답속도, 높은 집적도를 얻기 위한 다층배선구조가 필수적인데, 이러한 다층배선구조가 높은 신뢰성을 갖기 위해서는 배선재료의 컨포멀(conformal)한 형성이 대단히 중요하다.For this reason, copper is used as a wiring material on polymer substrates such as Teflon, which is a basic process in printed board manufacturing. Copper has been ruled out in the manufacture of highly integrated circuits because of its potential for interaction with other materials used in integrated circuits (because copper has a very high diffusion coefficient for Si or SiO2). Therefore, in order to successfully apply Cu to a device, it is necessary to provide a barrier layer as a diffusion barrier layer between copper and Si or SiO 2. With the recent increase in integration and progress in diffusion barrier technology, copper is expected to be gradually applied in future IC manufacturing processes. Copper diffusion barrier layer materials include TiN, TaN, and WN. In a highly integrated IC device, a multilayer wiring structure is essential for obtaining a high response speed and a high degree of integration. In order to have high reliability, a conformal formation of wiring material is very important.
따라서 종래의 반도체 구리배선 형성방법은 기판(10)상에 절연막(11)을 형성하고, 이 절연막을 부분 식각하여 트랜치(trench)나 접속구멍(contact hole)(12)을 형성하고, 이 절연연막과 트랜치나 접속 구멍에 금속제의 콘포멀한 배리어 층(barrier layer)(13)을 증착시킨 후, 이 배리어 층위에 구리막을(15) 증착, 구리배선 구조를 형성하여 왔다. 그리고 반도체 구리배선 형성을 위한 구리증착법들은 화학증착법(chemical vapor deposition), 애톰층 증착법(atomic layer deposition), 그리고 전기화학증착법인 무전해도금법(electroless deposition)이나 전기도금법(electroplating)등이 사용되고 있다. 그러나, 구리배선을 형성하기 위해서 배리어층(13)을 형성하고 나서, 그 위에 구리증착막을 형성하기 전에 배리어 층이 대기나 적은양의 산소가 존재하는 공간에 노출될 때 자연산화막(nativeoxide)이 형성되게 된다. 그런데 이 자연구리산화막은 도 1에 설명된것과 같이 화학증착법이나 원자층 증착법 또는 도금법에 의해 구리막을 증착시킬 때 균일한 핵생성을 방해하고, 구멍이나 트랜치 접촉창내부를 균일하게 도포하지 못하게 하여 접촉창내의 공동(16)을 형성하게 하며, 증착구리막(15)의 표면을 거칠게 하는 근본적인 이유가 될 뿐 아니라, 증착 구리막과 배리어층간의 접촉력(adhesion)을 좋지 않게 하는 문제점이 있다.Therefore, in the conventional method for forming a semiconductor copper wiring, an insulating film 11 is formed on the substrate 10, the insulating film is partially etched to form trenches or contact holes 12, and the insulating lead film is formed. After depositing a conformal barrier layer 13 made of metal in the trenches and connection holes, a copper film 15 is deposited on the barrier layer to form a copper wiring structure. In addition, copper deposition methods for forming semiconductor copper wirings include chemical vapor deposition, atomic layer deposition, and electrochemical deposition, such as electroless deposition and electroplating. However, after forming the barrier layer 13 to form a copper wiring, and before forming the copper deposition film thereon, a native oxide is formed when the barrier layer is exposed to air or a space in which a small amount of oxygen is present. Will be. However, this natural copper oxide film prevents uniform nucleation when depositing a copper film by chemical vapor deposition, atomic layer deposition, or plating, as described in FIG. 1, and prevents uniform coating of holes and trench contact windows. It is not only a fundamental reason for forming the cavity 16 in the window and roughening the surface of the deposited copper film 15, but also a problem of poor contact force between the deposited copper film and the barrier layer.
상기의 문제점들을 해결하기 위해서 종래에는 배리어층 표면특성 의존성(기판 의존성)이 없는 스퍼터링(sputtering)과 같은 물리증착법(physical vapor deposition)을 이용하여 배리어층 위에 얇고 연속적인 제1의 구리 씨앗층(seed layer)을 만든 후에, 상기의 구리증착법을 이용하여 제2의 구리박막을 형성하여, 반도체 소자 구리배선구조를 형성하여 왔다. 상기와 같이 물리증착법으로 구리 씨앗층을 증착한후, 그 위에 구리를 증착하는 종래의 반도체소자 구리배선 구조 형성방법을 도시한 도2a 내지 도2e를 참조하여 설명하면 다음과 같다.In order to solve the above problems, a thin, continuous first copper seed layer on the barrier layer is conventionally used by physical vapor deposition such as sputtering without barrier layer surface characteristic dependence (substrate dependence). After the layer was formed, a second copper thin film was formed using the above copper deposition method to form a semiconductor device copper wiring structure. Referring to Figures 2a to 2e illustrating a conventional semiconductor device copper wiring structure formation method of depositing a copper seed layer by physical vapor deposition, and then depositing copper on it as follows.
기판(10)상에 절연막(11)을 형성하는 단계와(도2a), 이 절연막(11)을 식각하여 접속 트랜치(trench)나 접속구멍(hole)을 형성하는 단계와(도2b), 상기 절연막(11)과 접속구멍(12)에 금속제의 배리어층(barrier layer)(13)을 증착시키는 단계와(도2c). 상기 배리어층위에(13)에 물리증착법(physical vapor deposition)을 이용하여 구리씨앗층(seed layer)(14)을 증착시키는 단계와(도2d), 상기 구리씨앗층(14)위에 화학기상증착법(chemica; vapor deposition), 원자층증착법(atomic layer deposition), 또는 도금법(plating)을 이용하여 구리를(15) 증착시키는단계(도2e)고 구성되어 있다.Forming an insulating film 11 on the substrate 10 (FIG. 2A), etching the insulating film 11 to form a connection trench or a connection hole (FIG. 2B); Depositing a metal barrier layer 13 on the insulating film 11 and the connection hole 12 (FIG. 2C). Depositing a copper seed layer 14 on the barrier layer 13 using physical vapor deposition (FIG. 2d), and chemical vapor deposition on the copper seed layer 14 and depositing copper (15) using chemica (vapor deposition), atomic layer deposition, or plating (FIG. 2E).
그러나 물리증착법의 경우 기판 특성에 의존하지 않고 증착막의 형성이 가능하다는 잇점이 있으나 층덮임(step coverage)특성이 좋지 않아, 콘포멀하게 고단차를 갖는 기판이나 종횡비가 큰 접속구멍(12) 내부를 균일한 두께로 증착할수 없는 문제점이 있다. 따라서 상기와 같이 배리어층위에(13) 물리증착법(physical vapor deposition)을 이용하여 구리씨앗층(14)을 형성되는 경우는, 콘포멀하지 않은 구리씨앗층이 얻어지게 된다.(도2d) 그리고 콘포멀하지 않은 구리씨앗층(14)위에 콘포멀한 증착 방법인 화학증착법이나 도금법을 사용하여 구리(15)를 증착하는 경우라도 고단차를 갖는 기판이나 종횡비가 큰 트랜치나 접속 구멍에 공동(void)이 형성되는 것을 피할수 없다는 문제점이 있다.(도2e) 따라서, 본 발명은 상기의 문제점을 해결하기 위하여 안출한 것으로서, 확산 배리어층 위에 연속적이며, 층덮임 특성이 우수하고 콘포멀한 얇은 구리 씨앗층(seed layer)을 형성하는 방법을 이용하여, 고단차를 갖는 기판이나 종횡비가 큰 트랜치나 접속 구멍에 공동이 없는 구리 증착막을 형성하게 하여, 반도체 배선 형성방법을 제공하는데 그 목적이 있다.However, the physical vapor deposition method has the advantage that the deposition film can be formed without depending on the substrate characteristics, but the step coverage characteristics are not good, so that the substrate having the high step and the aspect ratio having a high aspect ratio can be used. There is a problem that cannot be deposited to a uniform thickness. Therefore, when the copper seed layer 14 is formed on the barrier layer by using physical vapor deposition 13 as described above, a non-conformal copper seed layer is obtained (Fig. 2d). Even when copper 15 is deposited using a conformal deposition method, a chemical vapor deposition method or a plating method, on a non-formal copper seed layer 14, it is voided in a substrate having a high step, a trench having a high aspect ratio, or a connection hole. Therefore, the present invention has been devised to solve the above problems. The present invention is a continuous thin copper seed on a diffusion barrier layer, and has excellent layer covering properties. By using a method of forming a layer, a copper deposition film without a cavity is formed in a substrate having a high step, a trench having a high aspect ratio, or a connection hole, thereby forming a semiconductor wiring method. It is an object to the ball.
도 1은 종래 기술에 의한 구리 증착시의 문제점을 나타내는 도면.BRIEF DESCRIPTION OF THE DRAWINGS The figure which shows the problem at the time of copper deposition by the prior art.
도 2는 종래 기술에 의한 구리배선 형성시의 문제점을 나타내는 도면.2 is a view showing a problem when forming a copper wiring according to the prior art.
도 3은 본 발명의 따른 반도체 배선 형성방법을 도시한 공정 순서도.3 is a process flowchart showing a method for forming a semiconductor wiring according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
10 : 기판 11 : 절연막10 substrate 11 insulating film
12 : 트랜치 또는 콘택트 홀 13 : 배리어층 (barrier layer)12 trench or contact hole 13 barrier layer
14-1: 구리산화막 14 : 구리씨앗층막 (copper seed layer)14-1: copper oxide film 14: copper seed layer
15 : 구리막 16: 공동 (void)15: copper film 16: void
상기와 같은 목적을 달성하기 위하여 기판상에 절연막을 형성하고(도3a), 이 절연막을 부분 식각하여 트랜치나 접속 구멍을 형성하는 단계와(도3b), 상기 절연연막과 트랜치나 접속 구멍에 배리어 층을 증착하는 단계와(도3c), 상기 배리어 층위에 컨포멀하게 구리산화막을 증착하는 단계와(도3d), 상기 증착된 구리산화막을환원제를 이용하여 환원시켜 구리씨앗층을 만드는 단계와(도3e), 상기 환원된 구리씨앗층막 위에 컴포멀한 구리를 증착하는 단계(도3f)를 포함하여 진행하는 것을 특징으로 하는 반도체 배선 형성 방법이 제공된다.Forming an insulating film on the substrate (FIG. 3A) and partially etching the insulating film to form a trench or a connection hole (FIG. 3B), and a barrier to the insulating lead and the trench or connection hole to achieve the above object. Depositing a layer (FIG. 3C), conformally depositing a copper oxide film on the barrier layer (FIG. 3D), and reducing the deposited copper oxide film using a reducing agent to form a copper seed layer; FIG. 3E) provides a method for forming a semiconductor wiring, comprising the step of depositing conformal copper on the reduced copper seed layer film (FIG. 3F).
이하, 본 발명의 반도체 배선 형성 방법을 첨부한 도면에 도시한 실시예에 따라 상세히 설명하면 다음과 같다.Hereinafter, the semiconductor wiring forming method of the present invention will be described in detail with reference to the embodiments shown in the accompanying drawings.
먼저, 기판(10)상에 절연막(11)을 증착하고(도3a), 이 절연막(11)을 부분식각하여 접속 트랜치 또는 접속구멍(12)을 형성(도3b)하고 나서, 상기 절연막(11)과 트랜치나 접속구멍(12)에 배리어층(13)을 증착하는(도3c) 것은 종래와 동일하다.First, an insulating film 11 is deposited on the substrate 10 (FIG. 3A), the insulating film 11 is partially etched to form a connection trench or a connection hole 12 (FIG. 3B), and then the insulating film 11 ) And the barrier layer 13 in the trench or the connection hole 12 (FIG. 3C) are the same as before.
본 발명의 반도체 배선 형성방법은 상기와 같이 증착된 배리어층(13)위에 콘포멀한 구리산화막(14-1)을 증착하고(도3d), 상기 구리산화막(14-1)을 수소와 같은 환원제를 이용하여 환원시켜 콘포멀한 구리씨앗층(14)을 형성하고(도3e), 상기 구리씨앗층 위에 콘퍼멀한 증착방법인 화학증착법이나 도금법을 이용하여 제2의 구리 증착막(15)을 형성(도3f)하는 순서로 진행된다.In the method for forming a semiconductor wiring of the present invention, a conformal copper oxide film 14-1 is deposited on the barrier layer 13 deposited as described above (FIG. 3D), and the copper oxide film 14-1 is a reducing agent such as hydrogen. Reduction to form a conformal copper seed layer 14 (FIG. 3E), and a second copper deposition film 15 is formed on the copper seed layer by chemical vapor deposition or plating. It proceeds in the order shown in FIG.
상기 기판은 실리콘(Si), 실리콘산화막, 실리사이드(silicide), 알루미늄(Al), 알루미늄 합금(Al alloy), 구리중 어느 하나를 포함하는 재질의 것이고, 이들의 두 개이상의 적층구조도 이에 해당한다.The substrate is made of a material including any one of silicon (Si), silicon oxide film, silicide, aluminum (Al), aluminum alloy (Al alloy), and copper, and two or more stacked structures thereof are also applicable thereto. .
상기 배리어층(13)은 질화 티타늄, 질화 텅그스텐, 질화탄탈륨 등을 포함하는 질화계 금속들로 되는 것이 바람직하며, 구리의 확산방지막 효과성(effectiveness)를 증대하기 위하여 제3의 물질인 산소, 코발트(Co)등을 첨가할수도 있다. 또한, 상기 배리어층은 화학증착법(chemical vapor deposition)이나, 애톰층증착법(atomic layer deposition, ALD)을 이용하여 증착하고, 상기 절연막(11)과 트랜치나 접속구멍(12)에 10-500Å 정도의 두께로 증착한다. 또한 상기 배리어층을 증착하는 방법으로 물리 증착법(physical vapor deposition)을 사용할수도 있다.The barrier layer 13 is preferably made of nitride metals including titanium nitride, tungsten nitride, tantalum nitride, and the like, and includes a third material, oxygen, to increase the diffusion barrier effectiveness of copper. Cobalt (Co) etc. can also be added. In addition, the barrier layer is deposited using chemical vapor deposition or atomic layer deposition (ALD), and the insulating layer 11 and the trench or the connection hole 12 are about 10-500 mV. Deposit to thickness. In addition, physical vapor deposition may be used as a method of depositing the barrier layer.
상기 배리어층(13)상에 구리산화막을 증착하는 방법은 애톰층증착법(atomic layer deposition)을 이용하여 1-500Å의 정도의 구리산화막(14)을 증착한다.In the method of depositing a copper oxide film on the barrier layer 13, a copper oxide film 14 having a degree of 1 to 500 kV is deposited using atomic layer deposition.
상기 애톰층증착법(atomic layer deposition)을 이용하여 증착하는 경우에 구리전구체(Cu precursor)로는 구리 알콕사이드(alkoxide), 구리알콕사이드-아마이드(amide), 또는 구리알콕사이드-이미드(imide) 화합물, 그리고 구리 베타디케토네이트(β-diketonate)를 근간으로 하는 구리1가 혹은 구리2가의 화합물등을 이용하고, 반응화합물로는 산소, 오존, 과산화수소수, 물, 또는 알코올류(alcohol)등을 이용하고, 증착온도는 50-400℃로, 반응기의 압력은 0.001-50 torr로 유지한다.In the case of deposition using the atomic layer deposition method, as a copper precursor, Cu alkoxide, copper alkoxide-amide, or copper alkoxide-imide compound, and copper Copper monovalent or copper divalent compounds based on beta diketonate (β-diketonate) are used, and the reaction compound is oxygen, ozone, hydrogen peroxide, water, alcohols, etc. The deposition temperature is 50-400 ° C. and the reactor pressure is maintained at 0.001-50 torr.
또한 상기 구리산화막(14)을 증착하는 방법으로 상기 애톰층 증착법(ALD)외에도 화학증착법(chemical vapor deposition)을 사용할수도 있으며, 상기 애톰층 증착법(ALD)에 사용되는 전구체(precursor)들을 이용한다.In addition, in addition to the Atom layer deposition method (ALD), a chemical vapor deposition method may be used as a method of depositing the copper oxide layer 14, and precursors used in the Atom layer deposition method (ALD) are used.
다음 상기 구리산화막(14-1)을 수소 또는 활성화된 수소를 포함하는 분위기 가스를 이용하여 구리막으로 환원시켜 구리씨앗층(14)을 형성한다. 이때 구리산화막을 환원시키는 매개체는 수소, 수소와 비활성가스혼합물, 활성화된 수소, 또는 활성화된 수소와 활성화된 비활성가스 혼합물등을 사용할수도 있다. 그리고 환원을 위한 온도는 50-500℃로, 반응기의 압력은 0.001-760 torr로 유지한다.Next, the copper oxide layer 14-1 is reduced to a copper film using an atmosphere gas containing hydrogen or activated hydrogen to form a copper seed layer 14. At this time, the medium for reducing the copper oxide film may be hydrogen, hydrogen and inert gas mixture, activated hydrogen, or activated hydrogen and activated inert gas mixture. And the temperature for reduction is 50-500 ℃, the pressure of the reactor is maintained at 0.001-760 torr.
다음 상기 구리씨앗층(14)위에, 제2의 구리막을 애톰층 증착법(ALD),화학증착법(chemical vapor deposition) 또는 도금법(plating)을 이용하여 증착한다. 상기 애톰층 증착법(ALD) 또는 화학증착법(chemical vapor deposition)을 이용하여 구리를 증착하는 경우에 사용될수 있는 구리전구체(Cu precursor)로는 베타디케토네이트(β-diketonate)를 근간으로 하는 구리1가 혹은 구리2가의 화합물등을 이용하고, 반응화합물로는 수소, 포름알데하이드, 알콜류 또는 물등을 이용하고, 증착온도는 50-400℃로, 반응기의 압력은 0.001-250 torr로 유지한다.Next, on the copper seed layer 14, a second copper film is deposited using Atom layer deposition (ALD), chemical vapor deposition, or plating. As a copper precursor that can be used when the copper is deposited using the atom layer deposition method (ALD) or chemical vapor deposition (chemical vapor deposition) (Cu precursor) based on beta diketonate (β-diketonate) is based on Alternatively, a copper divalent compound or the like is used, and hydrogen, formaldehyde, alcohols or water are used as the reaction compound, and the deposition temperature is maintained at 50-400 ° C., and the reactor pressure is maintained at 0.001-250 torr.
상기와 같은 본 발명의 반도체 배선 형성 방법의 작용을 설명하면 다음과 같다.The operation of the semiconductor wiring forming method of the present invention as described above is as follows.
상기 배리어층(13)은 항상 표면에 자연 산화막이 존재하게 되며, 경우에 따라서는 배리어 효과를 극대화 하기위해서 산화막을 의도적으로 만들어 주기도 한다. 그런데, 화학반응을 이용하여 자연산화막이 존재하는 배리어 상에 직접 구리를 증착할 경우에는 구리의 핵화(nucleation)이 균질하지 못하고, 핵화가 어렵게 때문에 연속적이며, 콘포멀한 막을 제조할수가 없다.(도1) 그러나 본발명의 방법에서는 산화막이 존재하는 배리어상에 구리산화막을 증착하기 때문에 기저층의 산화여부 또는 산화정도 (degree of oxidaton) 에 무관하게 구리산화막의 핵생성이 균일하게 이루어 지게되며, 연속적이고 치밀한 구리산화막을 증착할 수가 있다. 그 이유는 산화금속막 위에 산화금속막의 성장은 매우 용이하게 이루어지지만, 반면에 산화금속막위에 순수 금속막의 성장은 매우 어려운 특성이 있기 때문이다. 따라서 상기와 같은 구리 산화막은 배리어 상에 매우 균일한 핵형성 (nucleation)을 통하여 얇고,연속적인 구리산화막이 된다. 상기와 같은 1단계 구리 산화막 씨앗층을 형성한후, 구리산화막 씨앗층을 환원시키면 얇고, 연속적이며 순수한 구리씨앗층을 형성할 수가 있다.The barrier layer 13 always has a natural oxide film on the surface, and in some cases, the oxide film is intentionally made to maximize the barrier effect. However, when copper is deposited directly on the barrier where the natural oxide film is present using a chemical reaction, it is impossible to produce a continuous and conformal film because the nucleation of copper is not uniform and the nucleation is difficult. 1) However, in the method of the present invention, since the copper oxide film is deposited on the barrier where the oxide film exists, the nucleation of the copper oxide film is uniformly performed regardless of whether the base layer is oxidized or the degree of oxidation. It is possible to deposit a dense copper oxide film. The reason is that the growth of the metal oxide film on the metal oxide film is very easy, whereas the growth of the pure metal film on the metal oxide film is very difficult. Therefore, such a copper oxide film is a thin, continuous copper oxide film through a very uniform nucleation (nucleation) on the barrier. After forming the one-step copper oxide seed layer as described above, by reducing the copper oxide seed layer can be formed a thin, continuous and pure copper seed layer.
이는 산화구리(Cu oxides)가 수소나 활성화된 수소가 있는 분위기에서 (온도는 50-600 ℃) 쉽게 순수구리로 환원되는 특성을 이용한 것이다. 상기 제 1단계의 구리 산화막 씨앗층을 형성한후(도3d), 2단계로 구리 산화막 씨앗층을 환원 공정을 이용하여 얇고, 연속적인 순수 구리 씨앗층을 형성하면(도3e), 종래의 방법으로 얻을수 없었던 층덮임이 우수한 콘포멀한 구리 씨앗층을 형성할수 있게 된다. 따라서 상기 반도체 배선 형성 방법의 작용을 이용하면, 배리어층의 표면이 산화되어 있을지라도 매우 층덮임이 우수한 구리 씨앗층을 얻을수 있고, 상기 층덮임이 우수한 구리 씨앗층위에 증착속도가 빠른 화학기상증착법 또는 도금법을 이용하여 제2의 구리를 증착하므로서, 고단차를 갖는 기판이나 종횡비가 큰 트랜치나 접속 구멍에 공동이 없는 구리 증착막을 형성하게 하여, 신뢰성이 우수한 반도체 구리 배선 형성방법을 제공하게 되는 것이다. 또한 본 발명의 작용을 이용하게 하면 배리어 위의 증착 구리막의 균일도를 이룰수 있고, 증착 구리막과 배리어층간의 접촉력(adhesion)을 우수하게 할 수 있는 반도체 구리 배선 형성 방법도 제공하게 된다.This is because copper oxides (Cu oxides) are easily reduced to pure copper in the presence of hydrogen or activated hydrogen (temperature is 50-600 ℃). After forming the copper oxide seed layer of the first step (FIG. 3D), and forming a thin, continuous pure copper seed layer using the reduction process of the copper oxide seed layer in the second step (FIG. 3E), the conventional method It is possible to form an excellent conformal copper seed layer, which could not be obtained with the layer covering. Therefore, by using the action of the semiconductor wiring forming method, even if the surface of the barrier layer is oxidized, a copper seed layer having excellent layer coverage can be obtained, and a chemical vapor deposition method or a plating method having a high deposition rate on the copper seed layer having excellent layer coverage is used. By depositing the second copper by use, a copper deposition film having no cavity is formed in a substrate having a high step, a trench having a high aspect ratio, or a connection hole, thereby providing a method for forming a semiconductor copper wiring with excellent reliability. In addition, by utilizing the operation of the present invention, it is possible to achieve a uniformity of the deposited copper film on the barrier, and to provide a method for forming a semiconductor copper wiring which can improve the adhesion between the deposited copper film and the barrier layer.
본 발명의 반도체 배선 형성방법에 의하면, 구리 산화막의 증착과 상기 구리산화막을 환원시켜 순수 구리막을 형성하는, 2단계로 진행되는 구리씨앗층 제조공정을 통하여, 고단차를 갖는 기판이나 종횡비가 큰 트랜치나 접속 구멍에 매우 치밀하고, 연속적이며, 콘포멀한 구리 씨앗층을 형성하게 하여, 구리씨앗층위에 성막되는 증착 구리막의 균일도를 이루며, 증착 구리막과 배리어층간의 접촉력(adhesion)을 우수하게 하므로써, 반도체 소자의 배선 신뢰성을 확보할수 있는 효과가 있다.According to the method for forming a semiconductor wiring of the present invention, a substrate having a high step and a high aspect ratio trench are formed through a two-step copper seed layer manufacturing process of depositing a copper oxide film and reducing the copper oxide film to form a pure copper film. (B) by forming a very dense, continuous, conformal copper seed layer in the junction hole, achieving a uniformity of the deposited copper film deposited on the copper seed layer, and improving the adhesion between the deposited copper film and the barrier layer. Therefore, the wiring reliability of the semiconductor device can be secured.
Claims (15)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020015499A KR20020043464A (en) | 2002-03-21 | 2002-03-21 | The method of fabrication of metal line structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020015499A KR20020043464A (en) | 2002-03-21 | 2002-03-21 | The method of fabrication of metal line structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20020043464A true KR20020043464A (en) | 2002-06-10 |
Family
ID=27725894
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020020015499A KR20020043464A (en) | 2002-03-21 | 2002-03-21 | The method of fabrication of metal line structure |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20020043464A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040001470A (en) * | 2002-06-28 | 2004-01-07 | 주식회사 하이닉스반도체 | METHOD OF FORMING Cu SEED LAYER FOR FORMING OF WIRING OF SEMICONDUCTOR DEVICE |
| KR20170089774A (en) * | 2016-01-27 | 2017-08-04 | 도쿄엘렉트론가부시키가이샤 | Cu WIRING MANUFACTURING METHOD AND Cu WIRING MANUFACTURING SYSTEM |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000077411A (en) * | 1998-08-31 | 2000-03-14 | Nec Corp | Semiconductor device and manufacture thereof |
| KR20000055562A (en) * | 1999-02-08 | 2000-09-05 | 김영환 | Manufacturing Method for Interconnection of Semiconductor Devices |
| KR20010003614A (en) * | 1999-06-24 | 2001-01-15 | 김영환 | A method for forming damascene type metal wire in semiconductor device |
| KR20010046222A (en) * | 1999-11-11 | 2001-06-05 | 박종섭 | Wiring forming method for semiconductor device |
-
2002
- 2002-03-21 KR KR1020020015499A patent/KR20020043464A/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000077411A (en) * | 1998-08-31 | 2000-03-14 | Nec Corp | Semiconductor device and manufacture thereof |
| KR20000055562A (en) * | 1999-02-08 | 2000-09-05 | 김영환 | Manufacturing Method for Interconnection of Semiconductor Devices |
| KR20010003614A (en) * | 1999-06-24 | 2001-01-15 | 김영환 | A method for forming damascene type metal wire in semiconductor device |
| KR20010046222A (en) * | 1999-11-11 | 2001-06-05 | 박종섭 | Wiring forming method for semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040001470A (en) * | 2002-06-28 | 2004-01-07 | 주식회사 하이닉스반도체 | METHOD OF FORMING Cu SEED LAYER FOR FORMING OF WIRING OF SEMICONDUCTOR DEVICE |
| KR20170089774A (en) * | 2016-01-27 | 2017-08-04 | 도쿄엘렉트론가부시키가이샤 | Cu WIRING MANUFACTURING METHOD AND Cu WIRING MANUFACTURING SYSTEM |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6605549B2 (en) | Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics | |
| EP0982771B1 (en) | Process for semiconductor device fabrication having copper interconnects | |
| KR100623556B1 (en) | Interconnection structure and fabrication process therefor | |
| US7405143B2 (en) | Method for fabricating a seed layer | |
| US20080237859A1 (en) | Diffusion barrier for integrated circuits formed from a layer of reactive metal and method of fabrication | |
| US20080237860A1 (en) | Interconnect structures containing a ruthenium barrier film and method of forming | |
| US6277765B1 (en) | Low-K Dielectric layer and method of making same | |
| US20050029662A1 (en) | Semiconductor production method | |
| KR100449223B1 (en) | Method for depositing copper onto a barrier layer | |
| US8344352B2 (en) | Using unstable nitrides to form semiconductor structures | |
| US6395627B1 (en) | Semiconductor device a burried wiring structure and process for fabricating the same | |
| TW490805B (en) | Method of forming a metal wiring in a semiconductor device | |
| KR100450738B1 (en) | Method for forming aluminum metal wiring | |
| KR100289515B1 (en) | Barrier emtal layer and method of forming the same | |
| KR100488223B1 (en) | Electroless plating process, and embedded wire and forming process thereof | |
| KR20020043464A (en) | The method of fabrication of metal line structure | |
| US6255734B1 (en) | Passivated copper line semiconductor device structure | |
| JP2002356775A (en) | Method of achieving high adhesion property of thin cvd copper film on tan substrate | |
| JP2000124310A (en) | Semiconductor device and manufacture thereof | |
| KR100247643B1 (en) | A reaction chamber for forming metal layer and method for forming metal layer in semiconductor device using the same | |
| KR20060079359A (en) | Method of fabricating the diffusion barrier layer using tasin layer and method of fabricating the metal interconnection using the method | |
| KR20030059489A (en) | Method of manufacturing semiconductor device having diffusion barrier layer in metal interconnection | |
| KR20010011307A (en) | Method for forming metal wire using zirconiumdiboride layer as diffusion barrier | |
| KR20000003941A (en) | Barrier metal of semiconductor devices | |
| KR20000015238A (en) | Method for forming a metal wire of a semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E601 | Decision to refuse application |