KR100278801B1 - Internal clock generation circuit to reduce current consumption - Google Patents

Abstract

The present invention relates to a semiconductor device having an internal clock generation circuit. The present invention divides taps connected between first and second synchronization delay lines into predetermined sections. That is, although each section has the same delay amount, a large number of taps are configured in the sections at the front end and a small number of taps are formed in the sections at the rear end. Therefore, the amount of current consumed at the rear end can be reduced. Also, each of the taps includes phase comparators for providing the switching signals Ti, and the switching operation of the interval after the final clock is blocked by the switching signals, thereby reducing the amount of current consumed in the subsequent stage. In addition, since the final clock may be provided in the preceding section in the second cycle with the sub delay circuit 100, there is an effect that can greatly reduce the current consumed thereafter.

Description

Internal clock generation circuit to reduce current consumption

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an internal clock generation circuit of a semiconductor device for reducing current consumption.

Generally, an internal clock generation circuit is employed in a synchronous dynamic memory semiconductor device. The internal clock generation circuit inputs the system clock CLK to provide an internal clock signal PCLK suitable for the semiconductor internal circuit. A clock buffer is embedded in the internal clock generation circuit, and the clock buffer converts the system clock CLK to a level suitable for the internal circuit. Each element in the chip is operated in response to the system clock CLK by the internal clock PCLK provided from the internal clock generation circuit in the semiconductor device. However, since the clock buffer merely serves to buffer an external clock such as a system clock (CLK) supplied from the outside to generate an internal clock required inside the chip, the external clock (CLK) and the internal clock (PCLK). Phase difference due to the delay of the buffer is necessarily generated. Due to such a phase difference, when a phase difference between clocks is generated, an operation inside the chip is applied after the external clock CLK is delayed by the phase difference. Therefore, the internal clock PCLK having the same phase as the external clock CLK supplied from the outside, that is, the internal clock PCLK of phase difference " 0 " in which time skew does not occur in synchronization with the external clock CLK is generated. The following internal clock generation circuit is required.

1 is a diagram illustrating an internal clock generation circuit of a semiconductor device having a synchronous delay line (hereinafter referred to as "SDL") according to the prior art, and FIG. 2 is a diagram illustrating waveforms of main signals according to FIG. 1. to be. 1, the buffer circuit 2, the main delay circuit 4, the plurality of unit delays 6a. 6n · 8a... 8n, phase comparators 10a... 10n and switches 12a... 12n. Main delay circuit 4 and a plurality of unit delays 6a... 6n are connected in series to each other to form a first synchronization delay line SDL1, and the plurality of unit delayers 8a... 8n are connected in series to each other to form a second synchronization delay line SDL2. In this case, it should be noted that the second synchronization delay line SDL2 includes only unit delay units without the main delay circuit 4. An operation according to the above configuration will be described with reference to FIG. 2. The buffer circuit 2 buffers an external clock, for example, the system clock CLK to provide a signal BD delayed by a predetermined time. The signal BD provides the signal delays D1 repeatedly delayed by the time set by the main delay circuit 4 to the respective unit delays 6. The phase detectors 10 sequentially compare the signals BD and the signals BD provided to the output nodes of the respective unit delays 6. As shown in Fig. 2, when the phases of the signal BD and the signal D12 are matched, that is, when the phases are matched at the 12th tap, the 12th phase detector provides the activated signal F12. The twelfth switch is turned on by the signal F12. On the other hand, as described above, the second synchronization delay line SDL2 provides the signals Dn 'which are delayed by the unit BDs only with the signal BD without the main delay unit 4. Therefore, the output signal D12 'of the 12th unit delay unit is provided as the internal clock PCLK by the turn-on operation of the 12th switch. The internal clock PCLK is a signal which is faster than the output signal BD of the buffer circuit 2 by the delay amount of the main delay circuit 4. As a result, the phase difference between the system clock CLK and the internal clock PCLK becomes "0". Meanwhile, for convenience of description, the tap is a vertical configuration of the unit delay unit 6, the phase comparator 10, the switch 12, and the unit delay unit 8 as shown in FIG.

The phase difference between the system clock CLK and the internal clock PCLK may be eliminated by using the first and second synchronization delay lines SDL1 and SDL2. However, the SDL includes a plurality of unit delays 6a... 6n · 8a... 8n are connected in series and these delays are all operated until they are output in synchronization with the internal clock (PCLK). At this time, the amount of power consumed is quite large. Moreover, for low frequencies, increasing the number of taps results in a greater amount of power consumed.

An object of the present invention is to provide an internal clock generating circuit having an SDL that can minimize power consumption.

Another object of the present invention is to provide an internal clock generation circuit of a semiconductor device for minimizing current consumption.

1 illustrates an internal clock generation circuit of a semiconductor device having a synchronization delay line SDL according to the prior art.

2 shows the waveforms of the main signals according to FIG. 1;

3 illustrates an internal clock generation circuit of a semiconductor device having a synchronization delay line SDL according to an embodiment of the present invention.

4 and 5 are views provided to explain the first branch research officer and the second branch research officer.

FIG. 6 shows detailed circuits of respective sections connected in the synchronization delay lines SDL of FIG.

7 is a detailed circuit of the sub delay circuit 100 of FIG.

8 shows waveforms of the main signals according to FIG. 3;

In order to achieve the above objects, the present invention provides a buffer circuit for receiving an external clock and providing a buffer delay signal BD, and a predetermined width of an output signal of a main delay circuit for delaying the buffer delay signal. A first synchronization delay line for outputting the nodes of the respective unit delayers by the unit, and outputs the buffer delay signal BD from the nodes of the unit delayers by a predetermined width without the main delay. An internal clock generation circuit comprising a second synchronization delay line for the purpose of; A specific switch for comparing the phases of the respective signals Di in the first synchronization delay line and the buffer delay signal BD to provide a specific signal Di 'in the second synchronization delay line as the internal clock. The apparatus has a phase comparator for providing a first control signal Fi for controlling the control signal and a second control signal Ti for controlling the next switch operation.

Hereinafter, an embodiment of an internal clock generation circuit according to the present invention will be described in detail with reference to the drawings, in order to help a thorough understanding of the present invention, various elements in the drawings are schematically provided. Various specific details are shown in the drawings, which are provided to help a more general understanding of the present invention, and it is obvious to those skilled in the art that the present invention may be practiced without these specific details. something to do.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

3 is a diagram illustrating an internal clock generation circuit of a semiconductor device having a synchronization delay line SDL according to an embodiment of the present invention. Referring to FIG. 3, the buffer circuit 2 receives the external clock, for example, the system clock CLK, and provides the buffer delay signal BD. The buffer delay signal BD is used as an operating voltage of elements in the semiconductor device. The buffer circuit 2 includes a plurality of inverters and serves to buffer the system clock CLK. The buffered buffer delay signal BD is input to the main delay circuit 4. The main delay circuit 4 is designed to have the same delay width as the buffer circuit 2. The output node of the main delay circuit 4 is connected to the first synchronization delay line SDL1, and the output node of the buffer circuit 2 is connected to the second synchronization delay line SDL2. Between each of the first and second synchronous delay lines, the unit site research officer 1, the first site research officer 3, and the plurality of second site research officers 5, 7, 9; Is connected. The unit delay study unit 1 includes a unit delay unit 6a connected to the first synchronization delay line SDL1, a phase comparator 10a, a switch 12a, and a unit delay unit 8a connected to the second synchronization delay line SDL2. . Meanwhile, for convenience of description, the configuration of each unit delay unit, phase comparator, and switch connected between the first and second synchronization delay lines is defined as a "tap (or set)". Therefore, it can be seen that the unit study executive 1 is composed of one tap. Meanwhile, the first branch research officer 3 is a section composed of a plurality of tabs, and the second branch research officer 5, 7, 9... Is a section configured as the number less than the number of taps in the first branch research officer 3. 4 shows that the first branch research officer 3 is arranged side by side as a plurality of tabs. Each tap is composed of a unit delay unit 6 connected to the first synchronization delay line SDL1, a phase comparator 10, a switching 12, and a unit delay unit 8 connected to the second synchronization delay line SDL2. Meanwhile, FIG. 5 is representative of the second paper studies 5, 7, and 9, and it can be seen that the number of taps is smaller than that of the first paper studies. Similarly, the tap consists of a unit delay unit 6, a phase comparator 10, a switching 12, and a unit delay unit 8. Thus, although the number of taps of the first branch research officer 1 is greater than the number of taps of the second branch research officers, the delay amount is 5, 7, 9... This is designed relatively large. That is, the second branch research officers 5,7,9... Each of the unit delays in the unit basically has a NAND gate and an inverter, and the number of the inverters is designed to be larger than the number of unit delays in the first branch research officer. In the unit delay units 6 and 8 shown in FIG. 5, the NAND gate and a relatively large number of inverters are included. Therefore, the first branch research officers 1 and the second branch research staffs 5, 7, 9. Is different in the number of configured taps, and the number of inverters in the unit delay units varies by the number of taps. As a result, the first branch and second branch executives have the same delay. Therefore, in the first branch research board 1, the number of taps is large, so that the phase difference between the system clock CLK and the internal clock PCLK synchronized with it can be almost eliminated. It can reduce power consumption in the parts. 3, each of the delay sections 1, 3, 5, 7, 9... Provides the signals Di, BD, Ti, Di ', 0. Each signal will be described in detail in the following description. On the other hand, the sub delay circuit 100 is connected between the buffer circuit 2 and the main delay signal 4. The sub delay circuit 100 is composed of unit delay units S / D1s, switches SSW0, SSW1, SSW2, SSW3, and SSW4. The sub-delay circuit 100 includes the first branch research officer 3 and the second branch research officer 3. It has the same delay width as The sub delay circuit 100 delays the buffer delay signal BD to a predetermined width by a switching operation in response to the signal Ti to provide the signal SD to the main delay circuit 4 and the unit delay researcher 1. That is, in the second delay circuit 100, the switching operation is determined by combinations of the output signals Ti of the phase comparators in the second cycle. The operation of the switches SSW causes the delays S / D1 to go through one, two, three or not. For example, when the switching signals Ti all become "high" in the first cycle, the switching signals change in the second cycle. At this time, one of the switches SSW is turned on by the combination of the switching signals Ti provided from the respective delay sections to operate the delay unit S / D1. As described above, when the delay units S / D1 of the sub delay circuit 100 pass, the final clock is determined in the preceding delay section instead of passing through the delay sections. In this way, when the final clock is determined in the delay section of the preceding stage, the transition from the next stage is not performed. For example, when the switching signals Ti are all "high" or all "low", the switches SSW in the sub delay circuit 100 do not operate. That is, the sub delay circuit 100 is operated only when at least one switching signal Ti is "low" or "high". Then, one switch SSW is turned on by the switching signal Ti, and when the specific switch SSW is turned on, the switching signal Ti, which is clock information of the next cycle, receives the switching information.

FIG. 6 is a detailed circuit of the first paper research manager 1 connected in the synchronization delay lines SDL of FIG. 3. Referring to FIG. 6, a plurality of unit delayers 6b, 6c, 6d... In the first synchronization delay line SDL1. This is connected in series. The plurality of unit delay units 8b, 8c, 8d. This is connected in series. Each unit delay unit consists of a NAND gate 14 and an inverter 16. Meanwhile, the second branch research officers 5, 7, 9... The unit delay units of the NAND gate and the plurality of inverters are as described above. On the other hand, the output nodes of the respective unit delays are provided with respective delay signals Di and Di '. Phase comparators 10b, 10c, 10d,... Between the output nodes. Is connected. Phase comparators 10b, 10c, 10d,... Is composed of a transmission gate 18, 26, a plurality of inverters 20, 22, 24, 28, 30, 34, and NAND gates 32, 36, respectively. The phase comparator 10 compares the phase difference between the delay signal Di provided from the output node of the unit delay unit 6 and the buffer delay signal BD (or the output signal SD of the sub delay circuit) and activates the NAND gate 36 when the phases coincide with each other. Provide the signal F. Enabled signal F is provided to switch 12. The switch 12 is composed of an inverter 38 and a transmission gate 40 which is switched by an enabled signal F. Therefore, the delay signal D 'of one of the unit delay units 12 connected in the second synchronization delay line is output to the final output. This final output is the internal clock PCLK. On the other hand, the inverter 34 of the phase comparator 10 provides the above-described switching signal Ti. The switching signal Ti is input to the NAND gates 14 configured in the unit delay units 6 and 12 of the rear stage. Meanwhile, the switching signal Ti is used as an input of the sub delay circuit 100 as described above. Therefore, when the final cycle is outputted to the internal clock PCLK by the phase comparator 10b in the first cycle, the operation of the unit delay units 6 and 8 of the subsequent stage is blocked by the switching signal T3. 6 shows the first branch research officer 3 composed of a preset number of tabs, and the second branch research officers 5, 7, 9... Similar configuration and action.

FIG. 7 is a detailed circuit of the sub delay circuit 100 of FIG. 3. Referring to FIG. 7, the output signals Ti of the phase comparators 10 (Ti; T1, T2, T3, T4, and T5) are respectively inverters and NAND gates 107, 109, 111, 113, 108, 110, 112, and 114. And NANDGATE 124. The output signals of the NAND gates 108, 110, 112, and 114 are provided to the controller 104. The control unit 104 is composed of the transmission gates TR1, TR2, TR3, TR4 and the inverter 117. The output of the controller 104 is sent to the switch 103. The switch 103 is composed of switch sections S4, S3, S2, S1 and latched inverters L1, L2, L3, L4. On the other hand, the delay nodes SD3, SD2 and SD1 are serially connected to the output node of the NAND gate 102. The delays SD include a resistor connected between the power supply voltage and the ground voltage terminal and inverters R1, R2 and I1, capacitors C1 and C2 connected between the power supply voltage and the ground voltage terminal and the inverter I2. That is, the buffer delay signal BD via the NAND gate 102 is input to the delayers SD3, SD2, and SD1 by the operation of the switch 103. As shown in FIG. 7, the switching signal Ti is composed of the transfer gate TR5, the inverter 121, and the N-channel MOS transistor 122 and the N-channel MOS transistor 106 connected to the NAND gate 119. High "or both" low "serves to prevent the signal BD from going through the delays SD.

8 are waveforms of the main signals according to FIG. 3. A brief operation according to FIG. 3 will now be described with reference to FIG. 8. First, the phase coinciding with the BD is detected in the section including D11 in the first cycle. The switching signals T11 to T14 are transitioned in accordance with the transition of the L11 to L14 sections. The transition between the sections L11 to L14 and T10 at the "high" level causes F11 to transition. As F11 is activated to the "low" level, the eleventh switch 12 is switched to output D11 'as the final clock (as an internal clock). From this time, it can be easily seen that the phase between the internal clock PCLK and the external clock, for example, the system clock CLK, coincides. On the other hand, in accordance with the transition of T11 to T14, F12 to F14 maintain the " high " level so that the operations of the switches 12 and the unit delay units 6 and 8 at the rear end (after the eleventh) are blocked. In the second cycle, the delay period in the sub delay circuit 100 is set by the "high" level of T6 and the "low" level of T13. The buffer delay signal BD is provided to the first synchronous delay line SDL1 and the second synchronous delay line SDL2 through which the delayed signal SD is set via the delays S / D1 in the sub delay circuit 100 through the main delay circuit. . Therefore, in the second cycle, the final clock (internal zone 3) is included in the 3rd tap section (first paper research section 3), not the delay section including the 11th tap section (any one of 3, 5, 7, and 9). Clock) is provided. At this time, L3 becomes the "low" level of T3, and it can be seen that no transition occurs after D7 '. Then, the signals after F3 are all "high" level by the signals after T3, so that the switches after F3 are all cut off. In response to the transition of F3, D3 'is output as the final clock.

Although one embodiment of the disclosed invention has been limited to the internal clock generation circuit, it should be noted that the present invention can be applied to other types of semiconductor devices employing a similar structure known in the art. Moreover, the present invention is not limited to the specific embodiments described herein as the best method contemplated for carrying out the present invention, but is defined by the equivalents of the claims as well as the claims below. Should.

According to the present invention as described above, the taps connected between the first and second synchronization delay lines are divided into preset sections. That is, a large number of taps are configured in the sections at the front end and a small number of taps are formed in the sections at the rear end. However, the delay amount of each section is the same. Therefore, the amount of current consumed at the rear end can be reduced. In addition, each of the taps is configured with a phase comparator for providing switching signals, and the switching operations of the interval after the final clock are blocked by the switching signals, thereby reducing the amount of current consumed in the subsequent stage. In addition, since the final clock may be provided in the preceding section in the second cycle with the sub delay circuit 100, there is an effect that can greatly reduce the current consumed thereafter.

Claims (6)

A buffer circuit for receiving an external clock and providing a buffer delay signal BD, and outputting the output signal of the main delay circuit which delayed the buffer delay signal from the nodes of the unit delayers by a predetermined width. An internal clock generation including a first synchronization delay line for outputting the second synchronization delay line for outputting the buffer delay signal BD from the nodes of the respective unit delayers by a predetermined width without the main delay; In a circuit; A specific switch for comparing the phases of the respective signals Di in the first synchronization delay line and the buffer delay signal BD to provide a specific signal Di 'in the second synchronization delay line as the internal clock. And a phase comparator for providing a first control signal (Fi) for controlling the control signal and a second control signal (Ti) for controlling the next switch operation. According to claim 1, The unit delays are composed of a NAND gate and an inverter, the NAND gate is the input signal of the unit delays of the previous stage and the second control signal (Ti) of the phase comparator of the previous stage as an input Device characterized in that. The method of claim 1; The unit delays, the phase comparators, and the switches in the first and second synchronization delay lines are divided into n sections to control the switching operation by using the output signals of the last phase comparators of each section. Characterized in that the device. The method of claim 1; And the main delay circuit inputs an output signal SD of a sub delay circuit having a delay amount corresponding to a delay amount of the divided section. The method of claim 4; The sub delay circuit includes n-1 unit delays, n switchings, the switching controllers, and a plurality of input / output elements, which are one less than the number of divided sections. The method of claim 4; The sub delay circuit inputs the second control signals Ti and if the signals are all "high" or "low", the sub delay circuit does not pass through the sub delay circuit, and at least one of the signals is "low" or " High ", the controller has a control for passing through the sub delay circuit.