KR100277209B1 - Manufacturing method for quantum dot transistor - Google Patents

Abstract

The present invention relates to a method for manufacturing a quantum dot transistor, a conventional method for manufacturing a quantum dot transistor has a problem that the characteristics of the quantum dot transistor is degraded by damaging the substrate using an etching process to form the quantum dot. In view of the above problems, the present invention voluntarily forms a quantum dot by using a metalorganic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MEB) method, or a low pressure chemical vapor deposition (LPCVD) method, thereby preventing the substrate from being damaged. Thus, there is an effect of preventing the characteristics of the quantum dot transistor from deteriorating.

Description

Quantum dot transistor manufacturing method {MANUFACTURING METHOD FOR QUANTUM DOT TRANSISTOR}

The present invention relates to a method for manufacturing a quantum dot transistor, and more particularly, to a method for manufacturing a quantum dot transistor that is suitable for reducing process steps by manufacturing a transistor operating at room temperature using spontaneously formed quantum dots.

In general, semiconductor technology has shown an exponential increase in the density of integrated circuits based on silicon materials. However, due to the development of information and communication technology, it is possible to increase the current mega-class storage capacity to the tera level to store large amounts of information. In order to improve the degree of integration, it is required to develop unit devices at the atomic level smaller than the size of devices that can be obtained by photo lithography technology. A quantum dot transistor using a quantum dot as a channel is of interest.

FIG. 1 is a schematic diagram of a general quantum dot transistor. As shown in FIG. 1, a source 2 and a drain 3 positioned in a symmetrical structure with respect to the quantum dot 1 at a position spaced a predetermined distance apart from the quantum dot 1 and; The gate electrode 4 is formed at a position spaced apart from the quantum dot 1 by a side of the position where the source 2 and the drain 3 are formed. In such a configuration, the source 2 and the drain 3 are connected to a quantum dot 1 that can bind electrons in three dimensions by a tunnel barrier, and the electrostatic potential of the quantum dot 1 The structure includes a gate electrode 4 capable of continuously changing potential).

In such a structure, if the size of the quantum dot (1) that binds the electron is sufficiently small, the single electron charging energy and quantum energy level difference of the quantum dot is thermal fluctuation energy (k _B T-k _B is larger than the Boltzmann constant, T is the absolute temperature), and the movement of each electron through the quantum dot can be controlled by using the bias variation of the source 2 and the drain 3 and the gate electrode 4. .

In the conventional method of manufacturing a quantum dot transistor, a lithography pattern of quantum wells, which is a method of forming quantum dots so far, to form the most important quantum dots, localization and patterning of impurity disordering by ion beam injection It was formed using a selective growth method using the substrate.

However, the method of using the quantum well's lithography pattern is a heterostructure using laser holographic lithography or electron beam lithography after the method of modifying the structure of the quantum well through plasma etching or active ion etching. Decreases the properties. In addition, the ion beam implantation method may result in interdiffusion and surface damage of group III atoms.

In addition, the selective growth method may be most suitable for forming a quantum dot because the position and size of the quantum structure can be easily adjusted. Such selective growth methods include growth on patterned substrates having ridges and tetrahedral pits, growth on buffer layers having multiatomic steps formed on vicinal substrates. How to. Then, there is a method of growing on the mesa surface of gallium arsenide (GaAs) in the {100} direction formed on the patterned oxide film.

However, all of the above methods use dry etching in the process of patterning the substrate, which may cause damage to the substrate, and the position and width of the three-dimensional structure according to the angle of misorientation. Restrictions are applied. In addition, the method of using the mesa surface of gallium arsenide in the oxide patterned substrate has a limitation in controlling the position of the quantum dots. The facet surface is formed in the {110} direction so that the position of the quantum dots is mainly {110]. } Because it is aligned in the direction.

As described above, the conventional method of manufacturing a quantum dot transistor uses an etching process to etch a part of a substrate to form a quantum dot, thereby damaging the substrate and lowering the characteristics of the quantum dot transistor. There was also an increasing problem.

It is an object of the present invention to provide a quantum dot transistor manufacturing method capable of forming quantum dots without using an etching process.

1 is a schematic diagram of a typical quantum dot transistor.

Figure 2 is a plan view showing an electron micrograph of a quantum dot transistor prepared by the method of manufacturing a quantum dot transistor of the present invention.

FIG. 3 is a graph showing results of measuring the current voltage characteristics of the source and the drain and their differential characteristics at room temperature in FIG. 2; FIG.

4 is a plan view showing an electron micrograph of a sample in which silicon quantum dots are formed on an insulating substrate.

FIG. 5 is a plan view showing an electron micrograph of a sample in which a source and a drain are formed on the upper part of FIG.

FIG. 6 is a graph showing results of measuring the current voltage characteristics of the source and the drain and their differential characteristics at room temperature in FIG. 5; FIG.

*** Description of the symbols for the main parts of the drawings ***

10: gallium arsenide substrate 20: silicon oxide film

1: quantum dot 2: source

3: drain 4: gate electrode

The above object is a quantum dot forming step of spontaneously forming a plurality of quantum dots on the substrate; Depositing a metal on the substrate on which the quantum dots are formed and patterning the metal by electron beam lithography to space a predetermined distance from one of the quantum dots selected from the plurality of quantum dots, and to form a symmetrical position on the substrate. It is achieved by forming an electrode forming step of forming a gate electrode spaced by a predetermined distance and the source and drain located in the quantum dot, as described in detail with reference to the accompanying drawings, the present invention.

FIG. 2 is a plan view showing an AFM (Atomic force microscope) photograph of a quantum dot transistor manufactured by a method of manufacturing a quantum dot transistor according to the present invention. As shown in FIG. After growing the InAs quantum dots (1) by using a vapor deposition method, one of the self-assembled plural indium arsenic quantum dots (1) is selected to A source 2 and a drain symmetrical about the quantum dot 1 at positions spaced at an interval of 30 nm or less from the side surface, and 0.5 from the quantum dot 1 The gate electrode 4 is formed at a position separated by m or more.

At this time, the size of the spontaneous quantum dot (1) is formed to be less than 20nm in the case of the III-V compound semiconductor quantum dot, 10nm or less in the case of silicon quantum dot can be expected to be a single electron charging effect and quantum effect at room temperature have.

The source 2, the drain 3, and the gate electrode 4 may include metals such as Al, Au, Cu, Ti, W, and Pt on the gallium arsenide substrate 10 on which the indium arsenide quantum dots 1 are formed. The metal may be deposited and formed by patterning the deposited metal in a structure as described above using an electron beam lithography method.

In such a structure, when a bias voltage is applied to the source 2 and the drain 3, a current flows through the selected quantum dot 1 positioned between the source 2 and the drain 3. In this case, although current may flow between the source 2 and the drain 3 through the other quantum dots 1 formed on the gallium arsenide substrate 10, the current flows through a plurality of quantum dots (1) The resistance increases exponentially as compared with the case of passing through one quantum dot so that the main current flows through the selected one quantum dot 1.

FIG. 3 is a graph showing the results of measuring the current voltage characteristics and derivatives of the quantum dot transistors 2 and 3 of the quantum dot transistors shown in FIG. 2 at room temperature. As shown in FIG. It can be seen that Coulomb staircase and Coulomb oscillation exist.

FIG. 4 is a plan view showing an electron micrograph of a structure in which silicon quantum dots are spontaneously formed by using a low pressure chemical vapor deposition (LPCVD) method on the silicon oxide film 20, and FIG. 5 is a source (on top) of FIG. 2) and a plan view showing an electron microscope photograph taken after the formation of the drain 3, as shown in the figure, the size of the silicon quantum dot 1 is 10 nm or less, and as in the above-described operation, the source 2 And most of the current flows through the silicon quantum dot 1 positioned between the drain 3 and the drain 3.

FIG. 6 is a graph showing the results of measuring the current voltage characteristics and the differential characteristics of the source 2 and the drain 3 of the quantum dot transistor shown in FIG. 5 at room temperature. It can be seen that Coulomb staircase and Coulomb oscillation exist.

In addition, a method of spontaneously growing the above quantum dots may use a molecular beam epitaxy (MBE) method.

As described above, the method of manufacturing the quantum dot transistor of the present invention spontaneously forms a quantum dot so that the etching process is not used to form the quantum dot, thereby preventing damage to the substrate, thereby preventing the characteristics of the quantum dot transistor from deteriorating. In addition, there is an effect of reducing the manufacturing cost by simplifying the process step.

Claims (5)

A quantum dot forming step of spontaneously forming a plurality of quantum dots on the substrate; Depositing a metal on the substrate on which the quantum dots are formed and patterning the metal by electron beam lithography to space a predetermined distance from one of the quantum dots selected from the plurality of quantum dots, and to form a symmetrical position on the substrate. A method of manufacturing a quantum dot transistor comprising an electrode forming step of forming a gate electrode spaced apart from the source and drain and the quantum dot by a predetermined distance. The method of claim 1, wherein the method for spontaneously forming the quantum dots in the quantum dot forming step is selected from metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MEB) method, low pressure chemical vapor deposition (LPCVD) method A method for manufacturing a quantum dot transistor, comprising growing a quantum dot. The method of claim 1, wherein the quantum dots spontaneously formed in the quantum dot forming step are 20 nm or less for the III-V compound semiconductor quantum dots and 10 nm or less for the silicon quantum dots. The method of claim 1, wherein the source and the drain are formed to be spaced apart from the quantum dot by 30 nm or less. The method of claim 1, wherein the source, drain, and gate electrodes are formed of one of Al, Au, Cu, Ti, W, and Pt.