JP3149037B2 - High-speed semiconductor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed semiconductor device capable of one-dimensional injection and traveling of carriers to reduce the influence of scattering, and a method of manufacturing the same.

2. Description of the Related Art In general, carrier injection and traveling in a semiconductor device have been performed three-dimensionally. However, a high electron mobility transistor (high electron mobility transistor) is used.
With the emergence of an obligatory transfer (HEMT), it has become common to reduce the effects of scattering by injecting and traveling carriers two-dimensionally, and such high-speed semiconductor devices play an important role in many electronic devices. Is being carried.

[0003] In recent years, techniques relating to carrier injection and traveling in semiconductor devices have been further advanced, and high-speed semiconductor devices that perform one-dimensional carrier injection and traveling such as quantum wires have attracted attention. . However,
At present, research and development of this kind of high-speed semiconductor device has just begun, and first, a device that can actually operate must be realized.

[0004]

2. Description of the Related Art FIG. 11 is a cutaway side view showing a conventional example of a high-speed semiconductor device capable of performing one-dimensional carrier injection and traveling.

In the figure, 1 is a semi-insulating GaAs substrate,
2 is an n-GaAs anode layer, 3 is a resonance tunneling layer.
Barrier (resonant tunneling ba)
(rrier: RTB) layer, 4 is an n-GaAs cathode layer, 5 is a cathode electrode, and 6 is an anode electrode. The RTB layer 3 is actually made of i-GaAs
The upper and lower portions of the well layer 3W are sandwiched between the i-AlAs barrier layers 3B. W is the width of the region where the carrier is injected, that is, the width of the cathode layer.

The following is an example of the main data relating to each part. (1) Anode layer 2 Thickness: 200 [nm] Impurity concentration: 1 × 10 ¹⁸ [cm ⁻³ ] (2) RTB layer 3 Thickness of i-GaAs well layer 3W: 3 [nm] i-AlAs Thickness of barrier layer 3B: 3 [nm] (3) Cathode layer (carrier injection layer) 4 Thickness: 200 [nm] Impurity concentration: 1 × 10 ¹⁸ [cm ⁻³ ] Width W: 50 [nm] ( 4) For the cathode electrode 5 Material: AuGe / Au Thickness: 20 [nm] / 200 [nm] (5) For the anode electrode 6 Material: AuGe / Au Thickness: 20 [nm] / 200 [nm]

In this high-speed semiconductor device, for example, electron beam lithography is applied to mesa etching so that the width W of the cathode layer 4 becomes about 50 [nm], and the carrier, that is, in this case, Electrons are injected and traveled, and one-dimensional carrier injection and travel are possible, although not to the extent of vertical quantum wires.

[0008]

In the high-speed semiconductor device shown in FIG. 11, the cathode layer 4 serving as a carrier injection layer is provided.
The narrowing of the width W is limited by the current lithography technology, and it is difficult to further reduce the size and approach a quantum wire.

The present invention achieves narrowing of a region in which one-dimensional carrier injection is performed, beyond the limitations imposed by the lithography technology, and therefore enables the carrier to move closer to the quantum wire to achieve high-speed operation. Try to improve.

[0010]

FIG. 1 is a cutaway side view of an essential part showing a high-speed semiconductor device for explaining the principle of the present invention. The same symbols as those used in FIG. 11 denote the same parts. Or have the same meaning.

In the figure, 7 is an n ⁺ -GaAs cathode contact layer, 8 is a depletion electrode made of WSi formed on the side surface of the n-GaAs cathode layer 4, and 9 is n-Ga
The depletion layers extending to the As cathode layer 4 are shown. The cathode layer 4 may be called a carrier injection layer, and the same applies to the following description.

[0012] Of the illustrated portions, the main data in the same portion as the portion shown in FIG. 11 is not different from the above-mentioned data and is omitted, and the main data of only the newly illustrated portion is omitted. An example of such data is shown below.

(1) Cathode contact layer 7 Thickness: 200 [nm] Impurity concentration: 1 × 10 ¹⁷ [cm ^-3 ] (2) Depletion electrode 8 Type: Schottky (WSi, etc.) Thickness: 100 [nm] (3) Regarding the depletion layer 9 Maximum extension on one side: 100 [nm] (20 when adding both sides)
0 [nm])

In the sample prepared for the experiment, the width of the n-GaAs cathode layer 4 having an impurity concentration of 1 × 10 ¹⁷ [cm ⁻³ ] was set to 220 [nm]. Since the maximum extension of the depletion layer 9 extended by forming the depletion electrode 8 made of WSi of the contact is 200 [nm] on both sides, the minimum width of the region into which carriers are injected is 20 [nm]. In general, the width that can function as a quantum wire is about 10 [nm] at the maximum, so that it can be said that it is very close to that, and one-dimensional carrier injection and traveling have become possible.

Here, _assuming that the extension of the depletion layer 9 is W _D , W _D = (2ε _s (V _bi −V−kT / q) / qN _D ) ^1/2 ε _s : dielectric constant of the semiconductor V _bi : Built-in voltage V: Applied voltage k: Boltzmann constant T: Absolute temperature q: Elementary charge N _D : Carrier concentration

Experiment 1 Cathode layer 4: n-GaAs N _D : 1 × 10 ¹⁷ [cm ⁻³ ] Temperature: 4.2 [K] V: 0 [V], W _D is 100 [nm], and the whole is At 200 [n
m], so that the minimum width of the carrier injection region is 20 [n
m].

Experiment 2 Cathode layer 4: n-GaAs N _D : 1 × 10 ¹⁸ [cm ^-3 ] Temperature: 4.2 [K] V: 0 [V], W _D is 15.0 [nm] , 30.0 in total
[Nm], so that the minimum width of the carrier injection region is 19
0.0 [nm].

Experiment 3 Cathode layer 4: n-GaAs N _D : 1 × 10 ¹⁸ [cm ⁻³ ] Temperature: 4.2 [K] V: 0.8 [V], W _D is 30 [nm] , 60 [nm] in total,
Therefore, the minimum width of the carrier injection region is 160 [nm].

Experiment 4 Cathode layer 4: n-GaAs N _D : 2 × 10 ¹⁸ [cm ^-3 ] Temperature: 4.2 [K] V: 0 [V], W _D is 10 [nm], and the whole is 20 [nm],
Therefore, the minimum width of the carrier injection region is 200 [nm].

Experiment 5 Cathode layer 4: n-InGaAs (lattice-matched to InP) N _D : 1 × 10 ¹⁷ [cm ^-3 ] Temperature: 4.2 [K] V: 0 [V], W _D is 45 [nm], 90 [nm] in total,
Therefore, the minimum width of the carrier injection region is 130 [nm].

Experiment 6 Cathode layer 4: n-InGaAs (lattice match to InP) N _D : 1 × 10 ¹⁸ [cm ^-3 ] Temperature: 4.2 [K] V: 0 [V], W _D is 14 [nm], 28 [nm] in total,
Therefore, the minimum width of the carrier injection region is 192 [nm].

As described above, in the high-speed semiconductor device according to the present invention, the doping amount of the impurity in the cathode layer, that is, the carrier injection layer, or the voltage applied to the depletion electrode of the Schottky contact formed in the carrier injection layer is reduced. Therefore, the extension of the generated depletion layer can be arbitrarily changed within a large range, and the effective width of the carrier injection region changes accordingly, so that one-dimensional carrier injection can be well controlled. Became. The effective width of the carrier injection region is, of course, a fine one that cannot be realized by the lithography technique.

Therefore, in the semiconductor device and the method of manufacturing the same according to the present invention, (1) required semiconductor layers (for example, n
A GaAs anode layer 2, an RTB layer 3, an n-GaAs cathode layer 4, etc.) in a carrier injection layer (eg, an n-GaAs cathode layer 4) with a resonance tunneling barrier layer (eg, an RTB layer 3) as a base. A carrier (for example, a WSi depletion electrode 8) formed of a refractory metal or a silicide thereof, which is applied to a side surface and forms a Schottky junction with the carrier injection layer to expand a depletion layer (for example, depletion layer 9). Characterized by one-dimensional injection and running, or

(2) A base layer (for example, n-GaAs base layer 24) and a resonant tunneling barrier layer (for example, RTB layer 25) and an emitter layer (for example, n-GaAs) serving as a carrier injection layer are formed in the vertical direction. An emitter layer 26), and a Schottky junction formed on the side surface of the emitter layer to form a Schottky junction with the emitter layer to expand a depletion layer (for example, the depletion layer 31) and have a lower end in contact with the base layer. An electrode (for example, a WSi base electrode 27) made of a melting point metal or a silicide thereof, and one-dimensional carrier injection and travel, or

(3) In the above (2), the key of the base layer
Carrier concentration (for example, 1 × 10¹⁸〔cm^-3] Above)
Carrier concentration in the emitter layer (e.g.,
1 × 10 ¹⁷〔cm^-3] Degree)
Electrodes made of high melting point metal or its silicide
Ohmic contact with the
For the emitter layer, which is the carrier injection layer,
Characterized by contacting, or

(4) A required semiconductor layer is vertically laminated and mesa-etched from the surface to the surface of the resonance tunneling barrier layer which is the base of the carrier injection layer, and the side surface of the carrier injection layer is exposed. Or a step of forming a coating made of a refractory metal or a silicide thereof only on the side surfaces of the exposed carrier injection layer, or

(5) At least a base layer, a resonant tunneling barrier layer, and an emitter layer serving as a carrier injection layer are formed in a vertical direction, and a resonance tunneling layer is formed from the surface thereof.
Mesa-etching up to the surface of the base layer underlying the barrier layer to expose the side surface of the carrier injection layer and the side surface of the resonant tunneling barrier layer and the surface of the base layer; Forming a refractory metal or an electrode made of a silicide thereof in contact with the surface of the base layer, the side surfaces of the resonant tunneling barrier layer, and the side surfaces of the carrier injection layer.
Or,

(6) In the above (5), it is preferable that a base layer having a carrier concentration sufficient for maintaining ohmic contact with an electrode made of a high melting point metal or a silicide thereof and a Schottky contact with the electrode be maintained. A step of vertically stacking a resonant tunneling barrier layer having a possible carrier concentration and an emitter layer serving as a carrier injection layer.

[0029]

By adopting the above-mentioned means, a high-speed semiconductor device having an RTB capable of injecting and running carriers one-dimensionally in the vertical direction, for example, RHET, RBT, etc., can surpass the limitations of the current lithography technology. It can be realized relatively easily.

[0030]

FIGS. 2 to 8 are cutaway side views of a main part of a semiconductor device in a process step for explaining a process of manufacturing a first embodiment of the present invention. This will be described in detail with reference to FIG. Note that the same symbols as those used in FIG. 1 represent the same parts or have the same meaning.

See FIG. 2 2- (1) For example, molecular beam epitaxial growth (molecula)
By applying the r beam epitaxy (MBE) method, an n-GaAs anode layer 2 (thickness: 200 [nm], an impurity concentration: 1 × 10 ¹⁸ [cm] is formed on a semi-insulating GaAs substrate 1.
^-3 ]) i-AlAs barrier layer 3B, i-GaAs well layer 3W,
RT having a three-layer laminated structure of i-AlAs barrier layer 3B
B layer 3 (thickness: well layer 3W = 3 [nm], barrier layer 3B = 3
[Nm]) n-GaAs cathode layer 4 (thickness 200 [nm], impurity concentration: 1 × 10 ¹⁸ [c
m ^-3 ]).

2- (2) Chemical vapor deposition
In this case, an insulating film 11 made of SiO _{2 having} a thickness of, for example, 200 [nm] is formed by applying an O.I.
To form

2- (3) By applying an electron beam resist process in an electron beam (EB) lithography technique, the width is set to, for example, 220 [nm].
A resist film 12 having a pattern for forming a mesa is formed.

2- (4) Reactive ion etching using CHF ₃ as an etching gas:
By applying the RIE method, the insulating film 11 is etched to form a mesa etching mask pattern.

FIG. 3 3- (1) By applying the RIE method using CCl ₂ F ₂ as an etching gas, the mesa of the n-GaAs cathode layer 4 is formed using the resist film 12 and the insulating film 11 as a mask. Perform etching. Note that this mesa etching is performed on the i-
It stops automatically at the AlAs barrier layer 3B.

FIG. 4 4- (1) After removing the resist film 12, the thickness is, for example, 200 [nm] to 30 by applying a sputtering method.
A WSi film of about 0 [nm] is deposited on the entire surface.

FIG. 5 5- (1) RIE method using CF ₄ as an etching gas (gas flow rate:
50 [sccm], pressure: 3 [Pa], high frequency output: 1
00 [W]), the WSi film is anisotropically etched. After this step, only the WSi film deposited on the side surface of the cathode layer 4 remains in a side wall shape and the other is removed, and the WSi depletion electrode 8 is formed there.

6- (1) The etching gas is CH ₄ (for AlAs) and CCl ₂
By applying the RIE method using F ₂ (for GaAs), mesa etching is performed from the RTB layer 3 to the inside of the n-GaAs anode layer 2 using the insulating film 11 and the WSi depletion electrode 8 as a mask.

See FIG. 7 7- (1) After removing the insulating film 11 by applying a wet etching method using hydrofluoric acid as an etchant, for example, metalorganic chemical vapor deposition (metalorga)
nic chemical vapor depos
An n ⁺ -GaAs contact layer 13 having a thickness of, for example, 400 [nm] is selectively formed on the surface of the cathode layer 4 and the surface of the anode layer 2 by applying an ition (MOCVD) method.

Here, Ga is placed on the WSi depletion electrode 8.
Since As is not grown, the n ⁺ -GaAs contact layer 13 formed on the cathode layer 4 and that formed on the anode layer 2 are completely separated from each other. Note that n ⁺
To form the GaAs contact layer 13, the MOCV
In addition to the D method, a gas source MBE method or the like can be applied.

7- (2) AuG having a thickness of, for example, 20 [nm] / 200 [nm] by applying a resist process, a sputtering method, and a lift-off method in the lithography technique.
An anode electrode 14 made of e / Au is formed.

8- (1) The thickness is, for example, 400 by applying the CVD method.
An interlayer insulating film 15 made of [nm] SiO ₂ is formed. The interlayer insulating film 15 can be made of, for example, polyimide, in addition to SiO ₂ . 8- (2) A thick resist film is formed on the entire surface so that the surface becomes flat by applying the spin coating method.

8- (3) Plasma using etching gas of CF ₄ + CHF ₃
Etch-back is performed by applying an etching method, and the etching is terminated when the top surface of the n ⁺ -GaAs contact layer 13 on the cathode layer 4 is exposed. 8- (4) Resist process in lithography technology, and
By applying the RIE method using CHF ₃ as an etching gas, the interlayer insulating film 15 is etched to form an anode electrode contact window. 8- (5) By applying a resist process, a sputtering method, and a lift-off method in the lithography technique, A
The cathode lead electrode 16 and the anode lead electrode 17 are formed.

The semiconductor device thus produced is
As in the semiconductor device described with reference to FIG. 1, one-dimensional carrier injection and traveling can be performed, and it goes without saying that the speed is extremely high.

FIG. 9 is a cutaway side view of an essential part for describing a three-terminal high-speed semiconductor device according to a second embodiment of the present invention.
In the figure, 21 is a semi-insulating GaAs substrate, 22 is n-
GaAs collector layer, 23 is an i-AlGaAs collector / barrier layer, 24 is an n-GaAs base layer, and 25 is an i-AlGaAs base layer.
An RTB layer having a three-layer structure of an AlAs barrier layer 25B, an i-GaAs well layer 25W, and an i-AlAs barrier layer 25B, 26 is an n-GaAs emitter layer, 27 is a WSi base electrode, and 28 is n ⁺ -GaAs. An emitter contact layer, 29 is a collector electrode, 30 is an emitter electrode, and 31 is a depletion layer. Incidentally, i-AlGaAs which is a material forming the collector / barrier layer 23 is used.
Is actually i-Al _0.22 Ga _0.78 As, and in this embodiment, the n-GaAs emitter layer 26 is a carrier injection layer.

In the second embodiment shown in the figure, the mesa etching is performed after each semiconductor layer is formed in the same manner as in the case of manufacturing the first embodiment. Not only the n-GaAs emitter layer 26 but also R
If the TB layer 25 and a part of the n-GaAs base layer 24 are performed, a WSi base electrode 27 having a side wall shape is formed, and then the second mesa etching is performed. can get.

In this embodiment, the n-GaAs emitter layer 2
6, the impurity concentration is set to about 1 × 10 ¹⁷ [cm ⁻³ ],
Further, by setting the impurity concentration in the n-GaAs base layer 24 to 1 × 10 ¹⁸ [cm ⁻³ ] or more, the junction between the WSi base electrode 27 and the n-GaAs emitter layer 26 becomes a Schottky junction, Since the junction with the n-GaAs base layer 24 can be an ohmic junction, it may be operated by applying a voltage lower than a voltage at which a current flows through the Schottky junction.・ Hot electron transistor (re
sonntunneling hot select
RON transistor (RHET).

FIG. 10 is a cutaway side view of a main part for describing a three-terminal high-speed semiconductor device according to a third embodiment of the present invention.

In the figure, 41 is a semi-insulating GaAs substrate, 42 is an n ⁺ -GaAs collector contact layer,
3 is an n-GaAs collector layer, 44 is a p ⁺ -GaAs base layer, 45 is an i-AlAs barrier layer 45B and i-Ga
An RTB layer having a three-layer structure of an As well layer 45W and an i-AlAs barrier layer 45B, 46 is n-GaAs
An emitter layer, 47 is a WSi depletion electrode having a side wall shape, 48 is an n ⁺ -GaAs emitter contact layer, 49 is a collector electrode, 50 is a base electrode, 51 is an emitter electrode, and 52 is a depletion layer. ing.
In this embodiment, the n-GaAs emitter layer 46 is a carrier injection layer.

The three-terminal high-speed semiconductor device is a resonant tunneling bipolar transistor (reson
ant tunneling bipolar tra
nsistor: RBT).

This embodiment can also be manufactured in the same manner as the first embodiment described with reference to FIGS. 2 to 8, except that the types of the semiconductor layers to be stacked are different.
If the step-like mesa etching is increased due to the presence of the base electrode 50 or the like, and this is not preferable,
The WSi depletion electrode 47 in the side wall shape is
It is attached to the side surface of the TB layer 45 and the lower end is p ⁺ -GaAs.
The structure shown in FIG. 9 may be brought into contact with the s base layer 44, in which case the device can be operated as an RBT.

As is apparent from the above description, in any case, the width of the carrier injection region is narrowed, and the carrier can be injected and run one-dimensionally.
It is possible to achieve the objectives of increasing the gain and increasing the P / V in the negative differential characteristic.

[0053]

In the high-speed semiconductor device and the method of manufacturing the same according to the present invention, required semiconductor layers are formed in a vertical direction, and a side face of a carrier injection layer having a resonance tunneling barrier layer as a base is formed. A film made of a high melting point metal or a silicide thereof is formed to form a Schottky junction with the carrier injection layer and expand the depletion layer.

By adopting the above configuration, a high-speed semiconductor device having an RTB capable of injecting and running carriers one-dimensionally in the vertical direction, such as RHET and RBT, can be used without exceeding the limitations of the current lithography technology. It can be realized relatively easily.

[Brief description of the drawings]

FIG. 1 is a fragmentary side view showing a high-speed semiconductor device for describing the principle of the present invention.

FIG. 2 is a fragmentary side view showing a semiconductor device at a key point in a process for explaining a process of manufacturing the first embodiment of the present invention.

FIG. 3 is a fragmentary side view showing a semiconductor device at a key point in a process for explaining a process of manufacturing the first embodiment of the present invention.

FIG. 4 is a fragmentary side view showing a semiconductor device in a process step for explaining a process of manufacturing the first embodiment of the present invention.

FIG. 5 is a fragmentary side view showing the semiconductor device at a key point in the process for explaining the process of manufacturing the first embodiment of the present invention.

FIG. 6 is a fragmentary side view showing the semiconductor device at a key point in the process for explaining the process of manufacturing the first embodiment of the present invention.

FIG. 7 is a fragmentary side view showing a semiconductor device at a key step for explaining a step of manufacturing the first embodiment of the present invention.

FIG. 8 is a fragmentary side view showing a semiconductor device at a key point in a process for explaining a process of manufacturing the first embodiment of the present invention.

FIG. 9 is a cutaway side view of an essential part for describing a three-terminal high-speed semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a fragmentary side view for explaining a three-terminal high-speed semiconductor device according to a third embodiment of the present invention.

FIG. 11 is a cutaway side view of an essential part showing a conventional example of a high-speed semiconductor device capable of performing one-dimensional carrier injection and traveling.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semi-insulating GaAs substrate 2 n-GaAs anode layer 3 RTB layer 4 n-GaAs cathode layer 5 cathode electrode 6 anode electrode 7 n ⁺ -GaAs cathode / contact layer 8 depletion electrode made of WSi 9 depletion layer 11 insulating film Reference Signs List 12 resist film 13 n ⁺ -GaAs contact layer 14 anode electrode 15 interlayer insulating film 16 cathode lead electrode 17 anode lead electrode

Claims (6)

(57) [Claims] A depletion layer formed on a side surface of a carrier injection layer having a resonance tunneling barrier layer as an underlayer among required semiconductor layers laminated in a vertical direction to form a Schottky junction with the carrier injection layer. A high-speed semiconductor device comprising a coating made of a refractory metal or a silicide thereof, which spreads, and one-dimensionally injects and runs carriers. 2. An emitter layer serving as a base layer, a resonant tunneling barrier layer, and a carrier injection layer, which are sequentially formed in a longitudinal direction, and a Schottky junction with the emitter layer is formed on a side surface of the emitter layer. A high-melting-point metal having a high-melting-point metal or an electrode made of a silicide thereof, the lower end of which is in contact with the base layer, and the injection and running of carriers are made one-dimensional. apparatus. 3. The carrier concentration of the base layer is sufficiently increased as compared with the carrier concentration of the emitter layer which is a carrier injection layer, and an electrode made of a high melting point metal or a silicide thereof is formed with respect to the base layer. 3. The high-speed semiconductor device according to claim 2, wherein the semiconductor device has an ohmic contact and has a Schottky contact with the emitter layer serving as the carrier injection layer. 4. A mesa-etching process from a surface of a required semiconductor layer to a surface of a resonance tunneling barrier layer, which is a base of the carrier injection layer, to expose side surfaces of the carrier injection layer. Forming a high-melting-point metal or a silicide coating on only the exposed side surfaces of the carrier injection layer. 5. A semiconductor device comprising: a base layer, a resonant tunneling barrier layer, and an emitter layer serving as a carrier injection layer, which are vertically laminated at least to form a mesa from the surface to the surface of the base layer underlying the resonant tunneling barrier layer. Etching to expose the side surface of the carrier injection layer and the side surface of the resonant tunneling barrier layer and the surface of the base layer; and then, the exposed surface of the base layer and the side surface of the resonant tunneling barrier layer and the carrier. Forming a high melting point metal or an electrode made of a silicide thereof in contact with the side surface of the injection layer. 6. A base layer having a carrier concentration sufficient to maintain ohmic contact with an electrode made of a refractory metal or a silicide thereof, and a resonant tunneling barrier having a carrier concentration capable of maintaining Schottky contact with the electrode. 6. The method for manufacturing a high-speed semiconductor device according to claim 5, further comprising a step of vertically forming a layer and an emitter layer as a carrier injection layer.