CN1159769C - Single-electron transistor and its preparing process - Google Patents
Single-electron transistor and its preparing process Download PDFInfo
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- CN1159769C CN1159769C CNB001335170A CN00133517A CN1159769C CN 1159769 C CN1159769 C CN 1159769C CN B001335170 A CNB001335170 A CN B001335170A CN 00133517 A CN00133517 A CN 00133517A CN 1159769 C CN1159769 C CN 1159769C
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Abstract
The present invention relates to a microelectron and micromanufacturing method, and provides a single electron transistor which is composed of one-dimensional waveguide, a line grid, etc. The single electron transistor of the present invention is manufactured by techniques of quantum dots formed by combining the one-dimensional waveguide and the line grid, etc. The present invention decreases the process-induced damage by the techniques of grooving, etc., and enhances the rate of finished products. The single electron transistor of the present invention has good working stability, and is suitable for integration. The size of the quantum dot of the present invention can achieve the nanometer level, and thus, the working temperature of the device is greatly enhanced.
Description
Technical field
The present invention relates to microelectronic component and micro-processing method.
Background technology
The conditional electronic transistor is realized functions such as switch, vibration and amplification by the collective motion of the electronics in groups of control more than ten million; The behavior that single-electronic transistor then needs only by an electronics just can realize specific function.Along with the raising of integrated level, power consumption has become the restraining factors of microelectronic device circuits stability.The element that constitutes with single-electronic transistor can improve microelectronic integrated level greatly and can make power consumption be reduced to 10
-5
Fig. 1 is the principle schematic of known single-electronic transistor, by source electrode 1, and drain electrode 2, quantum dot (or coulomb island) 3, two tunnellings joint 4 and 5 and is regulated coulomb grid of island electron number 6 and is formed.Its two primary conditions of regular event palpus: the resistance between (1) source, drain electrode is greater than the quantum resistance R
q=h/e2 ≈ 26k Ω; (2) the enough little e that makes of the electric capacity of quantum dot
2/ 2C＞＞k
BT.Wherein: C is the electric capacity of quantum dot, k
BBe Boltzmann constant, T is a working temperature.When the effective diameter of quantum dot during less than 10 nanometers, single-electronic transistor just can be at working and room temperature.
Single-electronic transistor can be divided into from material system at present: (1) metal single-electronic transistor, (2) organic material single-electronic transistor, (3) semiconductor single-electronic transistor.Preceding two kinds of single-electronic transistors are mainly used in technology exploration and fundamental characteristics research, last a kind of can be used for application study even product development.The preparation method of these single-electronic transistors mainly contains: (1) scanning probe microscopy SPM technology, (2) focused ion beam is injected FIB technology, (3) electron beam lithography.The single-electronic transistor repeatability and the stability of preceding two kinds of technology preparation are all poor, and the microfabrication time of first kind of technology is oversize.Thereby utilize electron beam lithography to prepare the semiconductor single-electronic transistor to have prior meaning, particularly utilizing the sample of high mobility two-dimensional electron gas structure to prepare single-electronic transistor has more potential meaning.At present the quantum-dot structure of the single-electronic transistor of this respect all is that back bias voltage by the wide area surface grid exhausts and realizes.Fig. 2 is wherein typical single-electronic transistor structure and principle schematic, it mainly emits superficial layer 9 and surperficial grid 6 to constitute by cover layer 7, two-dimensional electron gas layer 8, lid, on grid 6, add enough big back bias voltage and form quantum dot 3 (document 1, R.C.Ashooriza, on February 1st, 1996, Nature).This surperficial bar single electronic transistor has following deficiency: the big back bias voltage on (1) surperficial grid causes big depletion region, makes the physical dimension of quantum dot can not too little (as shown in Figure 3), must be greater than (B1+B2), otherwise transistor is with not conducting.This transistorized quantum dot potential energy distribution is smooth, and depletion widths is big, and the physical dimension of its quantum dot can't be little of nanometer scale, thereby it can only be worked under utmost point low temperature.(2) increase of overall impurity number under the potential barrier that causes of the not precipitous and large-area surperficial grid of the potential energy exterior feature of quantum dot causes the unstable working condition of single-electronic transistor.(3) quantum dot is realized by surperficial grid fully, thus limited its application and made it integrated become impossible.
Summary of the invention
The objective of the invention is to overcome the deficiency of prior art, a kind of single-electronic transistor of being made up of one-dimensional wave guide and lines grid etc. be provided, its working temperature height, stable performance, be suitable for integrated.Single-electronic transistor of the present invention is that the technology of utilizing one-dimensional wave guide and lines grid to be combined to form quantum dot prepares.Reduced process-induced damage and improved rate of finished products by The Application of Technology such as " groovings ".
The object of the present invention is achieved like this:
Single-electronic transistor of the present invention is to constitute like this: be the two-dimensional electron gas layer between substrate and resilient coating and table top, utilize the two-dimensional electron gas layer to form ohmic contact as source electrode and drain electrode by alloy, " grooving " technology of utilization forms one-dimensional wave guide between source electrode and drain electrode, one-dimensional wave guide is partly isolated by groove and other table tops, deposition forms two potential barrier lines grid and two sideline bar grid on one-dimensional wave guide, on potential barrier lines grid, add back bias voltage, exhaust the electron gas under these two potential barrier lines grid, thereby form quantum dot in the waveguide between them.
Its quantum dot is formed by one-dimensional wave guide and the back bias voltage that is added in the lines barrier gate, and the wave guide zone under these two potential barriers lines grid is two tunnel junctions of single-electronic transistor just.Bias voltage on the grid of limit can change the electron number in the quantum dot.
Preparation single-electronic transistor method of the present invention realizes according to the following steps:
(1) sample of two-dimensional electron gas layer is arranged with methods such as molecular beam epitaxy, liquid phase epitaxy or vapour phase epitaxy growths, be not more than 60 nanometers to the electronics thickness of gas from sample surfaces.
(2) peel off by metal deposition with conventional photoetching process or electron beam lithography method or the mesa etch technology prepares overlay mark, the height of mark must be greater than 200 nanometers, otherwise will influence alignment precision.
(3) be equipped with the large tracts of land part of device with common photoetching legal system, be equipped with part table comprising the deep etch legal system, short annealing prepares the lead-in wire contact portion that ohmic contact and evaporation of metal prepare Schottky gate.
(4) be equipped with the one-dimensional wave guide that width W w is 1000 nanometers 〉=Ww 〉=200 nanometers with the wet corrosion legal system, " grooving " technology of employing (reaches the corrosion cross section of control " del " as shown in Figure 4,, " grooving " depth H w is 70 nanometers 〉=Hw 〉=40 nanometers, the width W c of groove is 1000 nanometers 〉=Wc 〉=50 nanometers, if will utilize groove to form planar gate, then its width preferably is limited in about 500 nanometers.The also available dry etching of this step is finished.
(5) utilize electron beam lithography method, X ray or phase shift mask method in waveguide, to prepare the lines grid.Hang the rate of finished products that gate technique (shown in Figure 5) can improve device if adopt.Because the bar grid on the step contoured surface have strong stress in the part, it is easy to occur rupturing in the part in peeling off; The inhomogeneities of bar grid local stress can make bar grid and waveguide surface virtual connection touch and can not form Schottky barrier in addition, the bar grid are contacted with the two-dimensional electron gas of erosional surface and causes big leakage current.Appearance for fear of above situation, in evaporation process, make evaporation angle in source become 90 degree evaporations with bar grid orientation, select the evaporation source metal so that the Schottky barrier that adhesiveness is good and sample forms of itself and sample surfaces and higher barrier height, good stability are arranged and be difficult for oxidation.In the technical process, be after discharging the human body sensing electricity just can be near sample, otherwise its discharge will damage the waveguide and the atomic thin lines grid of narrow raceway groove.
The operation principle of single-electronic transistor of the present invention is that electronics is limited in moving in the one-dimensional wave guide, and this electronic waveguide is equivalent to optic Fabry-Parot cavity, thereby quantum effect such as the easier demonstration of this single-electronic transistor position is relevant; In this single-electronic transistor structure, the minimizing of surperficial grid area has also reduced builds the probability that the assorted son in district exists, and has improved the stability of device work; Utilize the corrosion cross section of del to avoid contacting of grid and channel layer, reduced leakage current, and improved the rate of finished products of device with the suspension gate technique; Utilize the lines grid to replace the wide area surface grid, weakened the shielding action of metal gate, and reduced the electric capacity of quantum dot, thereby improved the working temperature of device electronics; Little gate bias can form tunnel junctions under grid, make the wide precipitous rule (Fig. 6) of potential energy of quantum dot and make the stable performance, reliable of device.The size of its quantum dot can reach nanometer scale for a short time, thereby improves the working temperature of device greatly.
Description of drawings
Fig. 1: the principle schematic of known single-electronic transistor.
Fig. 2: traditional single-electronic transistor structure and principle schematic.
Fig. 3: the quantum dot potential energy distribution figure of traditional single-electronic transistor.
Fig. 4: the structural representation of single-electronic transistor of the present invention.
Fig. 5: utilize the one-dimensional wave guide and of wet corrosion " grooving " technology preparation to hang the lines grid.
Fig. 6: the quantum dot potential energy distribution figure of single-electronic transistor of the present invention.
Embodiment
Embodiment 1
Utilize AlGaAs/InGaAs/AlGaAs modulation doping two-dimensional electron gas sample preparation stable performance, the high single-electronic transistor (as shown in Figure 4) that also is fit to application of working temperature.
Sample grown: 1) utilize the molecular beam epitaxy technique 750 nanometer thickness resilient coatings 11 of growing on the Si-GaAs substrate, growth temperature is 750 ℃; 2) on resilient coating, at 650 ℃ of growth two-dimensional electron gas layers 8: i.e. the GaAs layer of the InGaAs layer of 14.5 nanometers and 1 nanometer, wherein In content is 0.18; 3) underlayer temperature is raised to 780 ℃, grow 10 nanometer AlGaAs layers and mix the 30 nanometer AlGaAs layers of Si, 4) underlayer temperature drops to 750 ℃ of growth 10 nanometer GaAs cover layers.Step 3) and 4 wherein) forms table top 10 through excessive erosion.
Device preparation: I) overlay mark preparation: 1) with sample ultrasonic cleaning 5 minutes in trichloroethylene, acetone, absolute ethyl alcohol respectively; 2) 110 ℃ of bakings 30 minutes, remove sample surfaces steam; 3) toasted 60 minutes at the electron beam resist PMMA that gets rid of 600 nanometers on the sample surfaces and at 170 ℃ with sol evenning machine; 4) prepare symmetrical two "+" word mark with the electron beam photoetching, its live width is the 1-5 micron, and length is 1000 microns; 5) develop 30 seconds also with isopropyl acetone photographic fixing 50 seconds with hexone; 6) clean sample 60 seconds and put eb evaporation chambers into absolute ethyl alcohol; 7) vacuum degree when vaporization chamber reaches above 7 * 10
-4During Pa, evaporation titanium (or niobium, road) 50 nanometers-100 nanometer and more than golden 150 nanometers; 8) ultrasonic peeling off; 9) long-time UV exposes more than 60 minutes and repeats second step by step suddenly to remove remaining electron beam resist.II) with the source electrode 1 of conventional photoetching process fabricate devices table top 10, ohmic contact with drain 2 and large tracts of land lead-in wire contact portion; III) preparation of one-dimensional wave guide 12: 10) with electron beam photoetching preparation " grooving " figure, repeat the step in preceding 5 steps, but the thickness of the electron beam resist of this moment is 100 nanometers, its photoresist can be PMMA, also can be ZIP or the like.11) clean sample with absolute ethyl alcohol, select H
2SO
4: H
2O
2: H
2O system " grooving ", its degree of depth just reaches the two-dimensional electron gas layer.Utilize the corrosion cross section of wet method opposite sex corrosion control " del ", form groove 17,18, make on the one hand effective duct width narrow as far as possible, avoided may directly contacting of two-dimensional electron gas 19 and bar grid 13,14,15,16 in the raceway groove on the other hand to improve the device working temperature.Be to realize the corrosion cross section of " del ", edge etching should be along＜011〉and＜011〉direction, and corrosive liquid such as the corrosion systems such as dilute sulfuric acid, phosphoric acid and propylhomoserin of selecting electrochemistry to control, corrosion rate is controlled between per second 0.1 nanometer and 1.6 nanometers.12) remove photoresist with acetone and repeated for the 9th step to remove remaining electron beam resist.IV) lines grid preparation: 15) repeat the technology in the 10th, 7 and 8 steps, but evaporate titanium (or Ni, Chrome) 5 nanometers-30 nanometer and golden 20 nanometers-30 nanometer this moment.Waveguide between potential barrier lines grid 13,15 is quantum dot 3.
Device performance: the rate of finished products of device is more than 95% and goodish stability arranged.(1) at one month
Interior 8 devices of duplicate measurements respectively 60 times, single electron coulomb oscillations curve overlaps separately fully; (2) one-dimensional wave guide is wide is that the width of 280 nanometers, 4 lines grid and device that mutual spacing all is 50 nanometers all can the temperature more than 20K show clearly single electron coulomb oscillations; (3) utilize this single-electronic transistor, we have detected the single electron storing process of single-electron memory and successfully it have been developed into hypersensitization Coulomb meter to electric charge.
Utilize AlGaAs/GaAs modulation doping two-dimensional electron gas sample (basic identical with the technology of embodiment 1, except that InGaAs changes layer GaAs layer into) prepared the single-electronic transistor of multiple Quantum Properties: the single-electronic transistor of (1) quantum waveguide type, observe the modulating action of quantum coherent characteristic to single electron coulomb oscillations amplitude; (2) on the bar grid 16 of Fig. 4, add-1.2 volts bias voltage, formed the single-electronic transistor of double quantum point, observed the energy level lotus root of double quantum point and closed effect; (2) bar grid width and the spacing single-electronic transistor that all equals 50 nanometers has shown tangible spin coulomb blockade effect.
Replace " electron beam lithography " preparation overlay mark among the embodiment 1 with " conventional photoetching ", prepared the low temperature single-electronic transistor.Its rate of finished products is 76%, and is low more than the rate of finished products among the embodiment 1.
Embodiment 4
Replace " metal deposition lift-off technology " preparation overlay mark among the embodiment 1 with " mesa etch ", the mesa etch degree of depth is 500 nanometers.The rate of finished products of single-electronic transistor is 68%.
Embodiment 5
Replace " metal deposition lift-off technology " preparation overlay mark among the embodiment 3 with " mesa etch ", the mesa etch degree of depth is 500 nanometers.The rate of finished products of single-electronic transistor is 56%.
Embodiment 6
Replace the wet corrosion among the embodiment 1 to prepare one-dimensional wave guide with dry etching, the rate of finished products of single-electronic transistor is 89%.The duplicate measurements of single electron coulomb oscillations curve is difficult to overlap fully.This is mainly because dry etching has infringement to cause to sample.
Sample among the embodiment 1 is changed to following sample: 1) utilize the molecular beam epitaxy technique 750 nanometer thickness resilient coatings of growing on the Si-GaAs substrate, growth temperature is 750 ℃, 2) at the 650 ℃ of growth Si-InGaAs layers of 14.5 nanometers and the GaAs layers of 1 nanometer, wherein In content is 0.18. 3) underlayer temperature is raised to 780 ℃ of growth 40 nanometer AlGaAs layers 4) underlayer temperature drops to 750 ℃ of growth 10 nanometer GaAs cover layers.
The characteristic of its single-electronic transistor is all very complicated, has shown acyclic single electron coulomb oscillations.This mainly is the cause that contains a plurality of quantum dots in the one-dimensional wave guide.
Claims (6)
1. single-electronic transistor, it is characterized in that: between substrate and resilient coating (11) and table top (10) is two-dimensional electron gas layer (8), utilize the two-dimensional electron gas layer to form ohmic contact as source electrode (1) and drain electrode (2) by alloy, " grooving " technology of utilization forms one-dimensional wave guide (12) between source electrode and drain electrode, one-dimensional wave guide is partly isolated with other table tops by groove (17) and (18), deposition forms two potential barrier lines grid (13) on one-dimensional wave guide, (15) and two sideline bar grid (14), (16), at potential barrier lines grid (13), (15) add back bias voltage on, exhaust the electron gas under these two potential barrier lines grid, thereby form quantum dot (3) in the waveguide between them.
2. method for preparing the single-electronic transistor of claim 1 is characterized in that: carry out according to the following steps:
(1) sample of two-dimensional electron gas layer is arranged with molecular beam epitaxial method growth, be not more than 60 nanometers to the electronics thickness of gas from sample surfaces;
(2) prepare overlay mark with the electron beam photoetching process by the mesa etch technology, the height that makes mark is greater than 200 nanometers;
(3) be equipped with the large tracts of land part of device with common photoetching legal system, promptly be equipped with the lead-in wire contact portion that part table, annealing preparation ohmic contact and evaporation of metal prepare Schottky gate with the deep etch legal system;
(4) be equipped with the one-dimensional wave guide that width W w is 1000 nanometers 〉=Ww 〉=200 nanometers with the wet corrosion legal system, the corrosion cross section of " grooving " technology of employing and control " del ", " grooving " depth H w is 70 nanometers 〉=Hw 〉=40 nanometers, and the width W c of groove is 1000 nanometers 〉=Wc 〉=50 nanometers;
(5) utilize the electron beam lithography method in waveguide, to prepare lines grid (13), (14), (15) and (16), in evaporation process, make source evaporation angle become 90 degree evaporations with bar grid orientation, select the evaporation source metal so that the Schottky barrier that adhesiveness is good and sample forms of itself and sample surfaces and high barrier height, good stability are arranged and be difficult for oxidation, in the technical process, just can be after discharging the human body sensing electricity near sample.
3. by the described preparation method of claim 2, it is characterized in that: wherein step (1) can also adopt liquid phase epitaxy or vapour phase epitaxy to grow the sample of two-dimensional electron gas layer.
4. by the described preparation method of claim 2, it is characterized in that: wherein step (2) can also adopt conventional photoetching process to prepare overlay mark.
5. by the described preparation method of claim 2, it is characterized in that: wherein step (2) can also prepare overlay mark by the metal deposition lift-off technology.
6. by the described preparation method of claim 2, it is characterized in that: wherein step (4) can also prepare one-dimensional wave guide with dry etching.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8512568B2 (en) | 2001-08-09 | 2013-08-20 | Siemens Industry, Inc. | Method of cleaning membrane modules |
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| JP3661061B2 (en) * | 2002-10-09 | 2005-06-15 | 松下電器産業株式会社 | Plasma vibration switching element |
| CN1321465C (en) * | 2002-10-15 | 2007-06-13 | 中国科学技术大学 | Coulomb island style rectifying monomolecular diode and preparation thereof |
| CN101359683B (en) * | 2007-08-01 | 2011-05-04 | 中国科学院半导体研究所 | Silicon based single electron device having double quantum point contact construction and producing method thereof |
| CN110148622B (en) * | 2019-05-06 | 2020-12-15 | 中国科学院半导体研究所 | Impurity atom transistor based on silicon nanocrystal bundling and preparation method thereof |
| CN110658584B (en) * | 2019-10-08 | 2020-08-14 | 浙江大学 | Ultra-large bandwidth silicon-based waveguide MEMS optical switch |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US8512568B2 (en) | 2001-08-09 | 2013-08-20 | Siemens Industry, Inc. | Method of cleaning membrane modules |
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