KR102098092B1 - Single Electron Transistor Using Three-Dimensional Dirac Semimetal and Method for Manufacturing Same - Google Patents

Abstract

Disclosed is a single-electron transistor, which comprises a gate electrode, a source electrode, a drain electrode and a channel layer formed between the source electrode and the drain electrode, wherein the channel layer includes a three-dimensional Dirac semimetal nanowire placed in a magnetic field. According to an aspect of the present invention, the single-electron transistor has an effect of realizing a single-electron transistor with increased operation speed by suppressing tunneling by applying a magnetic field while using a three-dimensional Dirac semimetal nanowire.

Description

Single Electron Transistor Using Three-Dimensional Dirac Semimetal and Method for Manufacturing Same}

It relates to a single-electron transistor using a three-dimensional Dirac metalloid and a manufacturing method thereof.

As the degree of integration of semiconductor memory devices increases, the operation of conventional MOS transistors has reached a limit and problems with device reliability have been raised. Several problems could be solved to some extent by appropriately modifying the size of the conventional transistor structure or each component. However, by the terascale integrated scale, fundamental transistor structure changes are inevitable.

As an alternative to overcome the limitations of MOS transistors, a single electron transistor (SET) has been proposed. SET has the advantage of being able to control electrons one by one and operating at very low voltages.

One nano-sized quantum dot (QD) between the source and drain and a capacitively coupled gate form one SET.

Due to the very small capacitance of the QD, the charge transfer from the source is blocked as the QD charging energy of one electron becomes greater than the thermal energy. This phenomenon is called the Coulomb-blockade (CB) phenomenon. In order to observe this CB phenomenon, the energy of QD storage of one electron must be greater than the thermal fluctuation k _B T. In addition, the electrical resistance between QD and the source and drain, that is, the tunnel resistance (R _t ) must be greater than the quantum resistance (R _k ), h / e ² (= 25.813 kΩ). The current blocking by the CB is removed while lowering the QD potential barrier by changing the gate voltage (V _G ) so that electrons tunnel continuously one by one.

More specifically, when the gate voltage V _G is increased, the induced charge increases in QD (in this case, the amount of induced charge may be smaller than the basic charge e because it is a continuous value) and QD energy increases. When the induction charge amount of QD reaches the basic charge e, one electron from the source tunnels and cancels the induction charge amount to minimize the QD energy again. In this way, a phenomenon in which the induced charge of a continuous value in QD increased by the gate voltage V _G is canceled by the tunneling electrons (quantized to the basic charge e) from the source to minimize energy is a sweeping of the gate voltage. While repeating periodically. This is called coulomb oscillation. The Coulomb vibration is observed as a periodic on / off of the drain current according to the change of the gate voltage. This CB model shows that the periodicity of the Coulomb vibration is fundamentally caused by the quantization phenomenon of the tunneling charge, and each electron in the QD increases by one on each peak.

However, in order to operate the single-electron transistor at room temperature, a difficult technique for reproducing a quantum dot of a size of several tens to tens of nm at a desired position is required. In particular, for the purpose of manufacturing a single electron switch, a technique of forming one or two quantum dots in a desired size at a desired position is essential rather than a technique of forming many quantum dots at a high density.

In addition, Dirac Semimetal is a material with a unique band structrue, where the conduction band and the valence band intersect at one point in the momentum space. Because of this, unlike a normal conductor, it has a Fermi point instead of a Fermi surface. In addition, it has a linear dispersion relationship near the Fermi point, which results in a phenomenon in which the energy interval is zero and the state density at the Fermi level is zero. These characteristics have unique properties, and accordingly, it is attracting attention as a new platform for quantum devices. Graphene is a representative two-dimensional Dirac metalloid, recently, Cd ₃ As ₂ , a three-dimensional Dirac metalloid, Research on Na ₃ Bi and TaAs has also been actively conducted.

However, it is currently known that the formation of quantum dots for dilock metalloids can be realized by a lithographically patterned structure for graphene, but the system made by the method is inevitably contaminated or in a specific area. Since the edges are too rough, there is a problem that causes random potential fluctuations and makes the device unstable.

For example, Republic of Korea Patent No. 10-1287317, the invention is (a) by depositing a sealing material, which is a gas molecule or atomic sealing material formed on a substrate to the top opening (top-opening) of the nano-cylindrical hole, Gradually reducing the diameter of the upper opening to shrink the nano-opening such that the opening diameter of the nano-opening is smaller than the diameter of the upper opening, and (b) holding the substrate in a horizontal direction and gas molecules or atoms Arranged so that the vapor deposition material in the state is orthogonal to the reduced nano-opening, the island electrode nano quantum dots having the same diameter as the reduced nano-opening are nanoparticles by the deposition material passing through the reduced nano-opening Allowing a cylindrical hole to be deposited directly at the expected location on the surface of the substrate, and (c) outputting the deposition material as before. Holding in the direction, and tilting the substrate to the right to have an inclination angle around the reduced nano-opening, so that the drain electrode nano quantum dot by the deposition material passing through the reduced nano-opening of the island electrode on the surface of the substrate Depositing at the expected right position, and (d) maintaining the output of the deposition material in the same direction as before, tilting the substrate to the left to have an inclination angle around the reduced nano-opening, and thus reducing the reduced nano-opening. Depositing a source electrode nano quantum dot by the passing deposition material at an expected left position of the island electrode on the surface of the substrate, and (e) maintaining the output of the deposition material in the same direction as before, and holding the substrate. The reduced nano-opening is clockwise to have a rotation angle at an inclination angle (θ) about the central axis. Rotating to deposit gate electrode nano quantum dots with the deposition material at the expected forward position of the island electrode on the surface of the substrate, and (f) finally, solution rinsing (ie wet etching) or gas etching (ie , Dry etching) to remove the nano-cylindrical hole in the photoresist on the substrate, a single-electron transistor including nanoscale island electrode nano quantum dots, drain electrode nano quantum dots, source electrode nano quantum dots and gate electrode nano quantum dots Disclosed is a method of manufacturing a single electron transistor (SET) using a nanolithographic technique in a semiconductor process using a processing step comprising directly manufacturing (SET) on the surface of the substrate. However, it is easy to contaminate, and the edge of a specific area is too rough, which causes a random potential fluctuation, making the device unstable.

In addition, another method for forming quantum dots is a method of forming an electrostatic potential by using a pn junction or the like to confine the quantum (quanntum confinement). Dirac Fermion) is difficult to confine both because it can pass pn junctions with very high transmittance. Such tunneling is referred to as Klein tunneling, and there is a problem that it is difficult to control it.

For example, the non-patent document "Chiral tunneling and the Klein paradox in graphene" discloses the results of forming an electrostatic barrier in graphene and measuring the results of kine tunneling. In addition, since it also occurs in the 3D Dirac metalloid, it is necessary to control the crane tunneling in order to realize a single electron transistor.

Republic of Korea Registered Patent No. 10-1287317

Katsnelson, M. I .; Novoselov, K. S .; Geim, A. K. Nat. Phys. 2006, 2, 620-625, "Chiral tunnelling and the Klein paradox in graphene"

An object of one aspect of the present invention is to provide a single-electron transistor implemented by applying a magnetic field to a three-dimensional Dirac metalloid nanowire.

In order to achieve the above object, in one aspect of the present invention

A single-electron transistor comprising a gate electrode, a source electrode, a drain electrode, and a channel layer formed between a source electrode and a drain electrode, wherein the channel layer is provided with a single-electron transistor comprising a three-dimensional Dirac metalloid nanowire placed in a magnetic field. .

In addition, in another aspect of the present invention

A single-electron transistor including a gate electrode, a source electrode, a drain electrode, a channel layer formed between a source electrode and a drain electrode, and a magnetic field generator, wherein the channel layer is placed in a magnetic field generated by the magnetic field generator and is a three-dimensional Dilock metalloid. A single-electron transistor comprising nanowires is provided.

In the single-electron transistor provided in one aspect of the present invention, the mobility of the carrier of the three-dimensional Dirac metalloid used as a channel is very high, and thus an operation speed is improved compared to a conventional transistor.

However, in Dirac metalloids, tunneling easily occurs, and when used in transistors, there is a problem that current may flow even when not desired, but a transistor can be implemented by suppressing tunneling by applying a magnetic field.

1 is a TEM and SEM photograph of a three-dimensional Dirac metalloid nanowire according to an embodiment of the present invention,
2 is a SEM photograph of the structure and measurement setup of a single electron transistor according to an embodiment of the present invention,
3 is a schematic diagram showing a single electron transistor according to an embodiment of the present invention,
4 is a schematic diagram showing the structure and energy band structure of a transistor according to a gate voltage in a single electron transistor according to an embodiment of the present invention,
5 is a graph for confirming a differential conductance according to a gate voltage while changing a magnetic field in a single electron transistor according to an embodiment of the present invention,
6 is a graph for confirming a differential conductance according to a gate voltage and a drain voltage while changing a magnetic field in a single electron transistor according to an embodiment of the present invention,
7 is a graph in which the gate voltage at 9 T is -2 V to -3.5 V in an enlarged range in the result of FIG. 6;
8 is a graph for confirming a differential conductance according to a drain voltage with respect to an empty state of a quantum dot while changing a magnetic field in a single electron transistor according to an embodiment of the present invention,
9 is a graph showing energy required to add holes one by one from an empty state to a quantum dot in a single electron transistor according to an embodiment of the present invention,
10 is a schematic diagram showing the behavior of an energy band structure and a carrier when a magnetic field is applied when an npn junction is formed by a gate voltage in a single electron transistor according to an embodiment of the present invention,
11 is a graph of confirming a transmission probability according to an incident angle of a carrier while changing a magnetic field in a single electron transistor according to an embodiment of the present invention,
12 is a graph showing each differential conductance when the temperature is 2.6 K and 300 mK in a single electron transistor according to an embodiment of the present invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by a person skilled in the art to which the present invention pertains. In general, the nomenclature used herein is well known and commonly used in the art. An object of one aspect of the present invention is to provide a single electron transistor implemented by applying a magnetic field to a three-dimensional Dirac metalloid.

To this end, the present inventors are single-electron transistors including a gate electrode, a source electrode, a drain electrode, and a channel layer formed between a source electrode and a drain electrode, wherein the channel layer comprises a three-dimensional Dirac metalloid nanowire placed in a magnetic field. An electronic transistor (see FIG. 3) was developed.

Hereinafter, the gate voltage V _G is defined as a voltage applied between the gate electrode and the source electrode, and the drain voltage V _D is defined as a voltage applied between the drain electrode and the source electrode.

Hereinafter, the operating principle of the transistor provided in one aspect of the present invention will be described in detail.

In Dirac metalloids, the conduction band and the valence band intersect at one point in the momentum space, which causes the Fermi point instead of the Fermi surface, unlike ordinary conductors. ). In addition, it has a linear dispersion relationship near the Fermi point, which results in a phenomenon in which the energy interval is zero and the state density at the Fermi level is zero. Three-dimensional Dirac metalloids are three-dimensional analogs of graphene, such as Cd3As2, Na3Bi and TaAs. When using a three-dimensional Dirac metal, unlike graphene, it is possible to grow in a one-dimensional structure such as nanowires. If it is in the form of nanowires, it will be suitable for use as a terminal point transistor because it is easy to form quantum dots and it is easy to confine electrons. In addition, in the case of graphene, an etching method should be used, but in this case, as inevitably contaminated as mentioned above, or because the edge of a specific region is too rough, it may cause a random potential fluctuation and destabilize the device. We want to realize single-electron transistors with three-dimensional Dirac metalloids.

Since a three-dimensional dirac point exists in the three-dimensional dilock metalloid, when a voltage V _G is applied through the gate electrode, the channel part may be of n-type or p-type depending on the voltage. It can be clearly understood with reference to FIG. 4. When a voltage is applied through the gate electrode, the carrier type and density of the nanowires between the source electrode and the drain electrode are easily changed, but the nanowire portion under the source electrode and the drain electrode is Thomas-Fermi screening. ) Because it is less affected by the gate voltage by the effect, it remains doped. By applying an appropriate voltage in consideration of the existing doped state, it is possible to form an npn or pnp junction to create an electrostatic potential.

However, in the 3D Dirac metalloid, since the conduction band and the valence band intersect at one point, there is no band gap, and thus there is a problem in that quantum confinement essential for quantum dot formation is difficult. We want to realize quantum confinement by making electrostatic potential using pn junction, but Dirac Fermion without mass can pass pn junction with very high transmittance. ). When a magnetic field is applied to the Dirac metalloid in order to control such tunneling, the movement path of Dirac Fermion is bent, so that tunneling can be suppressed. Under a large magnetic field, as Dirac Fermions perform a cyclotron motion, tunneling can be further suppressed. It can be clearly understood with reference to FIG. 10.

Through this, a single-electron transistor can be realized from a three-dimensional Dirac metalloid.

Hereinafter, a single electron transistor provided in one aspect of the present invention will be described in detail for each configuration.

The single electron transistor provided in one aspect of the present invention includes a gate electrode, a source electrode, a drain electrode, and a channel layer.

Further, the single electron transistor may include a magnetic field generating device.

The source electrode, the drain electrode and the channel layer included in the single electron transistor are from the group consisting of silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium arsenide (InAs) and indium phosphide (InP). It may be formed on a substrate of one or more selected.

Further, the channel layer included in the single-electron transistor includes a three-dimensional Dirac metalloid. The three-dimensional dilock metalloid may be at least one selected from the group consisting of Cd ₃ As ₂ , Na ₃ Bi and TaAs.

In addition, the three-dimensional Dirac metalloid nanowire of the channel layer included in the single-electron transistor is preferably 1 μm to 10 μm in length. When the length is 1 µm or more, it is preferable in that the process is relatively easy, and in the case of 10 µm or less, it is preferable in that it can maintain proper performance as a transistor.

In addition, the three-dimensional Dirac metalloid nanowire of the channel layer included in the single-electron transistor preferably has a diameter of 50 nm to 150 nm or less. When the diameter is 50 nm or more, it is preferable in that the process is relatively easy, and when the diameter is 150 nm or less, it is preferable in terms of easy quantization.

Further, the source electrode and the drain electrode included in the single-electron transistor may be at least one selected from the group consisting of gold (Au), nickel (Ni), titanium (Ti), and oxide-based electrodes.

Further, the gate electrode included in the single-electron transistor is a back gate doped with a substrate or is selected from the group consisting of gold (Au), nickel (Ni), titanium (Ti), and oxide-based electrodes separately formed. It may be one or more types of electrodes.

Further, in the single-electron transistor, the channel layer is preferably placed in a magnetic field of 4 T or more, and preferably in a magnetic field of 4 T to 30 T. When the strength of the magnetic field is 4 T or more, it is preferable in that the tunneling of the carrier can be sufficiently controlled, and the higher the magnetic field, the stronger the bondage of the carrier, which is advantageous. In the single electron transistor, the channel layer is more preferably placed in a magnetic field of 5 T or more, and more preferably placed in a magnetic field of 6 T or more. The quantization effect of the channel layer is maximized from 6 T or more.

Also, the single electron transistor may include an insulating layer. The insulating layer may be at least one selected from the group consisting of SiO ₂ , Si _x N _y layer, and Al ₂ O ₃ layer.

In addition, the magnetic field generator that may be included in the single electron transistor may include a superconducting magnet.

The single-electron transistor is preferably implemented at a temperature of 10 K or less. When it is 10 K or less, it is preferable in that the thermal energy is small enough to cause coulomb blockade.

Hereinafter, the present invention will be described in more detail through examples and experimental examples.

<Example 1> Fabrication of a single-electron transistor comprising a three-dimensional di-lactone metal nanowire

Embodiment 1 can be understood with reference to FIG. 1.

Cd ₃ As ₂ , a 3D di-lactone metal nanowire, is synthesized by vapor deposition, and Cd ₃ As ₂ powder is placed in a ceramic boat inside a quartz tube reactor. The substrate is made of silicon, and the silicon substrate is coated with a 1 mM BiI ₃ ethanol solution to form nanoparticles of the Bi catalyst, and is located 8 cm from the powder source. Argon gas is continuously supplied at a rate of 200 sccm under atmospheric pressure during growth, and the temperature of the powder source is set to 450 ° C. The substrate was maintained at 350 ° C to synthesize nanowires. A transmission electron microscope (TEM) image and a scanning electron microscope (SEM) image for this can be seen in FIG. 1.

Cd ₃ As ₂ nanowires are transferred to a very high concentration of doped p ++ silicon substrate using micromanipulation technology, which is covered with silicon dioxide (SiO ₂ ) formed by a 300 nm thick thermal oxidation process. have. The p ++ silicon substrate is used as a global back gate.

The typical diameter of the resulting Cd ₃ As ₂ nanowires is 60-100 nm, and argon (Ar) plasma etching (Plasm etcing) removes the native oxide on the nanowire surface. Thereafter, a source electrode and a drain electrode of Ti / Au (5/100 nm) are formed at a distance of 250 nm.

<Experimental Example 1> Analysis of transistor behavior according to gate voltage under different magnetic fields

For the transistor of Example 1, the magnetic field is applied in a direction perpendicular to the nanowires, that is, in a direction perpendicular to the electric field, the intensity of the magnetic field is changed from 0 T to 9 T, and differential conductance according to the gate voltage V _G Conductance) was measured and shown in FIG. 5. Measured at a temperature of 300 mK, the voltage between the source and drain (V _SD ) was fixed to zero.

Referring to FIG. 5, it can be seen that a dirac peak appears near -2.5 V. It can be seen that the nanowire is slightly n-doped. As the strength of the magnetic field increases, the conductance decreases, and depending on the applied gate voltage, the nanowire may have both p-type and n-type properties. In the graph of FIG. 5, when V _G is less than -2.5 V, it becomes a p type, and when V _G is greater than -2.5 V, it becomes an n type. The nanowire portion under the source electrode and the drain electrode is less affected by the gate voltage by the Thomas-Fermi screening effect, and thus remains doped. If at this time represents the nanowire portion of the source electrode and the drain electrode under the n ^* region, when V _G is less than -2.5 V n ^* -pn ^* to form a junction, when V _G is greater than -2.5 V n ^{* -} nn ^* to form a joint (4).

 In addition, as the magnetic field increases, the magnetoresistance effect increases, so the conductance decreases, and in a strong magnetic field of about 9 T, a very small conductance near the Dirac peak.

That is, when a magnetic field is not applied, tunneling occurs to have a large conductance even near the Dirac peak, but it can be seen that tunneling is well controlled under a strong magnetic field.

<Experiment 2> Transistor behavior analysis according to gate voltage and drain voltage under different magnetic fields

The transistor of Example 1 was tested in the same manner as Experimental Example 1, but the differential conductance according to V _SD and V _G was measured and shown in FIG. 6.

In FIG. 6, when a magnetic field is not applied, only very weak aperiodic vibrations of 0.9 to 1.3 e ² / h are seen, but it can be seen that in a strong magnetic field of 8 T or more, it has a clear diamond-shaped region. This is called a coulomb diamond, and the conductance line at the edge of the diamond is straight, and the coulomb diamond can be clearly seen near the Dirac peak (V _G = 2.5 V). This indicates that a single quantum dot is formed between the source and drain electrodes. Since the coulomb diamond is mainly observed in the p region compared to the n region, it can be seen that quantum dots can be formed by npn junction.

FIG. 7 is an enlarged range of V _G = -2 V to V _G = -3.5 V when the magnetic field is 9 T in FIG. 6. The largest Coulomb diamond appears near V _G = -2.5 V, which means an empty state at the quantum dot, that is, the number of carriers N is zero. In the two adjacent coulomb diamonds, the right side represents one electron (N = 1e) and the left side represents one hole (N = 1h). The effective band-gap is measured at about 4 meV. By applying a negative gate voltage, the number of holes sequentially increases one by one in a state having one hole in the quantum dot (N = 1), and the energy for adding holes to the quantum dot is about 2 eV to 4 eV. Is (Fig. 9).

From the right side of the empty state (N = 0) of the quantum dot, a small diamond (N = 1) due to the first electron can be observed. Since this n-doped region is merged into the n-doped region (n ^* ) of the electrode portion, the gate voltage As this height increases, the coulomb blockade capable of controlling tunneling disappears (see FIG. 4).

8 shows the conductance according to V _SD while changing in the magnetic field 8 to 9 in an empty state (N = 0) of the quantum dot. As the magnetic field increases, it can be seen that the conductance in the Coulomb shield state becomes small, and thus it can be seen that tunneling can be more strongly controlled under a strong magnetic field.

<Experiment 3> Calculation of tunneling probability according to magnetic field

To confirm the probability of tunneling according to the magnetic field, the transmission probabillity according to the carrier incident angle was calculated while changing the size of the magnetic field for the p-n junction. The transmission probability was calculated using a transfer matrix and is shown in FIG. 11.

Potential height (Electrical potential height, V ₀ ) was 200 meV, Fermi Energy (E _F ) is 50 meV, Fermi velocity (V _F ) is 2 × 10 ⁵ m / s, and the source electrode The distance between the drain electrodes was calculated to be 120 nm. In addition, the magnetic field was applied along the z-axis direction and induces a gauge potential that increases linearly along the x-axis direction.

In FIG. 11, it can be seen that as the magnetic field increases, the angular range in which transmission is allowed is reduced and the electrons are strongly localized. From this, it can be confirmed that the p-n junction of the Dirac metalloid under a strong magnetic field can act as a barrier to control tunneling by constraining fermions without mass in the p-n-p junction or the n-p-n junction.

<Experiment 4> Transistor behavior analysis according to temperature

In order to analyze the behavior of the single-electron transistor according to the temperature, the conductance when the magnetic field strength is 8T is observed for the case where the temperature T is 300 mK and 2.6 K, and is shown in FIG. 12.

In the case of T = 2.6 K, it was confirmed that the conductance was higher than in the case of T = 300 mK, and it was confirmed that the coulomb diamond region became broader and dimmed. This means that as the temperature increases, thermal energy increases, making it difficult to maintain the Coulomb shield.

As described above, the present invention has been described in detail through preferred examples and experimental examples, but the scope of the present invention is not limited to specific examples, and should be interpreted by the appended claims. In addition, those skilled in the art should understand that many modifications and variations are possible without departing from the scope of the present invention.

Claims (7)

It is a single-electron transistor including a gate electrode, a source electrode, a drain electrode, and a channel layer formed between the source electrode and the drain electrode,
The channel layer is a single-electron transistor comprising a three-dimensional Dirac metalloid nanowire placed in a magnetic field.
According to claim 1,
The three-dimensional Dirac metal is Cd ₃ As ₂ , A single-electron transistor, characterized in that at least one member selected from the group consisting of Na ₃ Bi and TaAs.
According to claim 1,
The single-electron transistor, characterized in that the diameter of the three-dimensional Dirac metalloid nanowire is 50 nm to 150 nm, and the length is 1 μm to 10 μm.
According to claim 1,
The channel layer is a single-electron transistor, characterized in that placed under a magnetic field of 4 T to 30 T.
According to claim 1,
The channel layer is a single-electron transistor, characterized in that a pnp junction is formed by a gate voltage.
According to claim 1,
The channel layer is a single-electron transistor, characterized in that an npn junction is formed by a gate voltage.
It is a single-electron transistor including a gate electrode, a source electrode, a drain electrode, a channel layer formed between the source electrode and the drain electrode, and a magnetic field generator,
The channel layer is a single-electron transistor comprising a three-dimensional Dilock metalloid nanowire placed in a magnetic field generated from the magnetic field generator.

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