CN1160797C - Point-contact planar-gate single-electron transistor and its preparation method (2) - Google Patents

Abstract

The invention relates to a microelectronic device and a micromachining method, in particular to a point-contact planar gate high-temperature single-electron transistor and a preparation method thereof. Prepared by electron beam lithography and conventional photolithography. There are source and drain electrodes in the conductive material layer on the substrate; between the source electrode and the drain electrode is a narrow channel containing quantum dots, on both sides of the narrow channel are point contact planar gates, and on the conductive material layer is a A layer of insulating material is deposited, on which a surface gate is covered. The size of the single-electron transistor quantum dot of the invention can reach the atomic scale, can work at room temperature, and satisfies two basic conditions for the normal operation of the single-electron transistor.

Description

Point-contact planar-gate single-electron transistor and its preparation method (2)

The invention belongs to a microelectronic device and a microprocessing method, in particular to a point-contact planar grid type high-temperature single-electron body tube and a method for preparing the device by using a nanotechnology process.

The importance of nanotechnology has been fully valued, and the research funding for developing nanotechnology is increasing day by day. The core of its research is the research of nanomaterials, nanoprocessing technology and nanodevices. The study of nanomaterials has made rapid progress, but the study of nanodevices has just emerged and progressed slowly. Single-electron transistors are currently one of the most successful and recognized nanodevices, and are the most promising nanodevices, as reported in Physics Today (January 1994). Traditional electronic transistors realize functions such as switching, oscillation, and amplification by controlling the collective movement of more than tens of millions of electrons in groups; single-electron transistors can achieve specific functions only through the behavior of one electron. With the improvement of integration, power consumption has become a limiting factor for the circuit stability of microelectronic devices. Components composed of single-electron transistors can greatly increase the integration of microelectronics and reduce power consumption to 10 ^-5 . The extremely low power consumption of single-electron transistors can solve the problem of unstable factors caused by heat dissipation in existing integrated circuits. Its high degree of integration can far exceed the current limit of large-scale integration, and can reach the limit set by Heisenberg's uncertainty principle and become a new type of device that cannot be replaced in the future.

The single-electron transistor includes a source, a drain, quantum dots or Coulomb islands that are weakly coupled to the source and drain, and a gate that can be used to adjust the electrochemical potential of the quantum dots, that is, to control the number of electrons in the quantum dots. Its normal operation requires two basic conditions: (1) The resistance between the source and the drain is greater than the quantum resistance R _q = h/e2≈26kΩ; (2) The capacitance of the quantum dot is small enough so that e ² /2C＞＞k _B T. Among them: C is the capacitance of the quantum dot, k _B is the Boltzmann constant, and T is the working temperature. When the quantum dots have an effective diameter of less than 10 nanometers, single-electron transistors can operate at room temperature. Therefore, in order to improve the operating temperature of the single-electron transistor and its anti-interference ability, it is necessary to reduce the geometric size of the quantum dot.

At present, the main preparation technologies of high-temperature single-electron transistors are: (1) the scanning probe microscope SPM technology reported in "Applied Physics Letters" [Appl.Phys.Lett., 1996, 68, 34-36], (2) focused ion beam Inject FIB technology [Appl.Phys.Lett., 1993, 63, 51-53], (3) self-assembly technology [Appl.Phys.Lett., 1997, 71, 2294-2296], (4) electron beam lithography Technology [Appl. Phys. Lett., 1996, 69, 406-4086]. Scanning probe microscopy (SPM) technology can prepare atomic-scale room-temperature single-electron transistors, but it is rarely used in actual device preparation due to its long processing time, poor repeatability and stability. Focused ion beam implantation (FIB) technology has certain damage to the device and it is difficult to realize atomic-scale nanostructures, so it is not used much in real device preparation. The method of preparing nanostructures with self-assembly technology is quite common, and has been widely used in the fields of physics, chemistry and biology, but it has great limitations: 1) the uncertainty of the position, 2) the geometric size and Inhomogeneity of spatial distribution, 3) and mismatch of device process. Therefore, the high-temperature single-electron transistor prepared by this process has the disadvantage of being complicated and difficult to control. At present, the preparation of single-electron transistors mainly uses electron beam lithography. It realizes the quantum dots of single-electron transistors by exposing and developing photoresist with electron beams. Since the limit of electron beam lithography is 30 nanometers, the diameter of the prepared quantum dots is larger than 50 nanometers. Therefore, the integrated stable single-electron transistors prepared at present can only work in the extremely low temperature region.

The purpose of the present invention is to overcome the shortcomings of the prior art, avoid the complexity of the device preparation process and the characteristics that the device can only work in the extremely low temperature region, so as to provide a point-contact planar gate single-electron transistor and its preparation method. The method of the invention can also be applied in preparing other nanometer devices, biomolecular devices and realizing miniaturization of biochips and the like.

The purpose of the present invention is achieved like this:

The single-electron transistor of the present invention is constituted like this, as shown in Figure 1: in the conductive material layer 7 on the substrate 8, source electrode 1 and drain electrode 2 are arranged; The narrow channel 3 has a width of 3-800 nanometers; both sides of the narrow channel 3 are point-contact planar grids 4, and the narrow channel is further narrowed by negative bias extrusion on the point-contact planar grid, resulting in only a single quantum Narrow channel for point control. On the conductive material layer 7 is a deposited insulating material layer 6 with a thickness of 10-800 nanometers; the insulating material layer 6 is covered with a surface gate 5 . The quantum dots in the narrow channel are formed by the self-assembly method in the material preparation or the corrosion, oxidation and other reasons in the process. If the conductive material layer itself is a non-conductive layer, through the positive bias applied to the surface gate, an inverse two-dimensional electron gas is formed in the conductive material layer, and the number of electrons in a single quantum dot and the source and drain electrodes are adjusted and controlled. current between. If the conductive material layer itself is a doped conduction layer, an insulating layer should be deposited or oxidized between the point contact planar gate and the narrow channel. At this time, the surface gate is mainly used to adjust and control the number of electrons and current between source and drain. The substrate can be further covered with a buffer epitaxial layer made of the following materials: 1) Si, Ge or GeSi semiconductor element material, 2) GaN, NAlGaAs, NInGaAs, NAlGaAs, NInAlGaAs, GaAs, AlGaAs, InGaAs or InAlGaAs semiconductor compound, 3 ) Composites of silicon, phosphorus ions, nitrogen ions, arsenic ions, oxygen ions or boron fluoride ions doped into Si, Ge, GeSi, GaN, NAlGaAs, NInGaAs, NInAlGaAs, GaAs, AlGaAs, InGaAs or InAlGaAs semiconductor materials Materials, 4) materials whose lattice constants are similar to those described in 1), 2) and 3) above and can be combined arbitrarily, 5) insulating materials such as silicon oxide, aluminum oxide, silicon nitride or titanium oxide. These buffer epitaxial layers further improve the quality of the conductive material layer. If the buffer epitaxial layer is a non-doped layer, it can be used as an insulating layer between the doped substrate and the conductive material layer to prevent the generation of leakage current. The buffer epitaxial layer can be the same as various materials constituting the conductive material layer, but the combination of materials is different and the structure is also different.

The substrate can be 1) silicon on semiconductor insulator (SOI); 2) oxide material, such as sapphire Al ₂ O ₃ , silicon oxide SiO ₂ , magnesium oxide MgO or strontium titanate SrTiO ₃ ; or 3 ) glass, SiC, Ge, silicon or single crystal silicon with a layer of oxide on the surface; 4) doped semiconductor material or non-doped semiconductor material, the non-doped semiconductor material is GaAs, Cr- GaAs, Si or InP; doped semiconductor material is N ⁺ -GaAs, N ⁺ -InP or N ⁺ -GaN.

The conductive material includes 1) Si, Ge or SiGe semiconductor element materials, 2) GaN, NAlGaAs, NInGaAs, NInAlGaAs, GaAs, AlGaAs, InGaAs or InAlGaAs semiconductor compounds, or 3) silicon, magnesium, phosphorus ions, nitrogen ions , arsenic ions, oxygen ions or boron fluoride ions doped into Si, Ge, SiGe, GaN, NAlGaAs, NInGaAs, NInAlGaAs, GaAs, AlGaAs, InGaAs or InAlGaAs semiconductor materials.

The insulating material includes silicon oxide, aluminum oxide, silicon nitride or titanium oxide.

The point-contact planar grid includes metal layers such as Al, Au, W, Cr, Ti, Ni, Pt, Ge, Ta or Mo and any compound layers between them.

The surface gate is an evaporated metal film, or an N+ doped polysilicon film that has been deposited, implanted and annealed.

The metal film is a metal layer such as Al, Au, W, Cr, Ti, Ni, Pt, Ge, Ta, Mo or In and any composite layer between them.

The preparation method of the single-electron transistor of the present invention is simple, and can be prepared not only in combination with advanced electron beam photolithography methods, but also in combination with conventional photolithography nano-processing methods. The method of the present invention has versatility, and various materials can be used to prepare the single-electron transistor of the present invention, and the materials include modulated doped two-dimensional electron gas structure materials, materials containing nanoparticles or quantum dots, doped and non-doped thin layers Miscellaneous thin film materials, organic compound materials, biomolecular materials, and their combinations or composite materials, etc. Biomolecular devices can be fabricated using biomolecular materials.

The preparation single-electron transistor method of the present invention comprises the following steps, by volume ratio:

(1) Select the material covered with the conductive material layer 7 on the substrate 8, and thin the conductive material layer 7 by repeated oxidation and corrosion. It is oxidized in a mixed atmosphere of N ₂ : O ₂ =0-900:1-500, and the oxidation temperature is 350-1200°C. The oxide layer is removed with an etching solution HF:H ₂ O=1-100:1-5000 or HCl:H ₂ O=1-100:1-5000. Then oxidize and corrode again until the thickness of the conductive material layer 7 reaches 2-300 nanometers. If the selected conductive material layer 7 contains self-assembled quantum dots, the distance between the quantum dots and the upper surface of the thinned conductive material layer 7 is 2-200 nanometers; the electron gas in the conductive material layer (7) is formed by Caused by implantation, original doping in conductive material, or external bias.

(2) On the thinned conductive material layer 7, use conventional photolithography, X-ray photolithography, electron beam photolithography, ion beam photolithography or phase-shift mask photolithography to prepare overlay marks , part of the mesas formed by corrosion, corroded grooves or deposited films (including metal films) can be used as overlay marks; the metal films are metal layers such as W, Cr, Pt, Ta, or Mo and the interlayer between them Any composite layer.

(3) Utilize the overlay mark to locate, adopt conventional photolithography to prepare a mask, etch the conductive material layer 7 with the overlay mark, wherein, etch away the part in the mask pattern of the conductive material layer 7, and the part outside the mask pattern The conductive material layer 7 is the mesa for making the device, and the etching can be known dry etching or wet etching, wherein: the wet etching solution is H ₂ SO ₄ : _{H 2} O ₂ :H ₂ O=1-100:1-60:1-500, NH ₄ OH:H ₂ O ₂ :H ₂ O=1-100:1-60:1-5000, H ₃ PO ₄ : _{H 2} O ₂ : H ₂ O=1-100:1-60:1-500, H ₂ SO ₄ :H ₃ PO ₄ : _{H 2} O=1-100:1-60:0-500, KOH:H ₂ O=1- 100:1-5000, NaOH:H ₂ O=1-100:1-5000, HF:H ₂ O=1-100:1-5000 or HCl:H ₂ O=1-100:1-5000 solution.

(4) Utilize the positioning of the overlay mark, prepare a mask for ion implantation on the conductive material layer 7 with the overlay mark by photolithography, and its mask material includes 1) PMMA, ZEP, AZ or SAL etc. Resist, 2) metal layers such as Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta or Mo and any composite layer between them, or 3) silicon oxide, aluminum oxide, silicon nitride Or insulating materials such as titanium oxide. Ions are implanted into the mask, wherein the implanted elements include silicon, phosphorus ions, nitrogen ions, arsenic ions, oxygen ions, nitrogen ions or boron fluoride ions. After ion implantation, the mask used for ion implantation is removed, and the element to be implanted is activated by high-temperature annealing, and the annealing temperature is 500-1200°C.

(5) Utilize overlay mark to locate, prepare the pattern photoresist mask for making source electrode 1 and drain electrode 2 on the conductive material layer 7 of finishing by photolithography, deposit on band photoresist pattern mask Metal film, or when there is a high temperature process higher than 500°C in step 6), the metal film deposition and alloy annealing are carried out in step 10); the thickness of the metal film is 50-900 nanometers. The deposited metal film includes Pd, Zr, Ag, Gd, Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta or Mo and any composite layer between them. The fabrication device is removed and soaked in a solvent. The metal film outside the mask pattern is removed by stripping and other processes, and the metal film in the mask pattern left behind is the source electrode 1 and the drain electrode 2 after alloy annealing. The annealing temperature is 300-800°C, and the time is 5-3600 seconds. .

(6) Utilize overlay marks to position, use photolithography methods such as conventional photolithography, X-ray photolithography, electron beam photolithography, ion beam photolithography or phase-shift mask photolithography to directly print on the conductive material layer 7 Prepare a graphic mask on it, and its mask material includes 1) photoresist such as PMMA, ZEP, AZ or SAL, 2) metal such as Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta or Mo layers and any composite layers between them, or 3) insulating materials such as silicon oxide, aluminum oxide, silicon nitride or titanium oxide. Etching the conductive material layer 7 by a dry etching method or a wet etching method, etching away the part without a mask on the conductive material layer 7, preparing a narrow channel 3 connecting the source 1 region and the drain 2 region on the conductive material layer 7, Its width is 2-800 nm and its height is 1-150 nm. For the conductive material layer 7 that does not contain self-assembled quantum dots, the quantum dots are formed in the narrow channel 3 by over-etching, lateral etching or dry oxygen oxidation, and the width of the narrow channel is further reduced by dry oxygen oxidation. The narrow channels form quantum dots, and the distance between the quantum dots and the upper surface of the conductive material layer 7 is 2-200 nanometers. The dry oxygen oxidation method can obtain a dense oxide layer and can control the oxidation rate with high precision, thereby improving the repeatability of the process and the stability of the device work. The gas fed during dry oxygen oxidation is O ₂ :N ₂ =1-4:0-20, and the oxidation temperature is 500-980°C.

(7) Utilize overlay mark positioning, adopt conventional photolithography, X-ray photolithography, electron beam photolithography, ion beam photolithography, phase-shift mask photolithography, in the prepared narrow channel 3 Prepare a photoresist pattern mask for making point contact planar grid 4 on the conductive material layer 7, and deposit a metal film thereon, or use self-consistent deposition method directly on the photoresist pattern mask for preparing narrow channel 3 A metal film is deposited, and the thickness of the metal film is 10-150 nanometers. The deposited metal film includes metal layers such as Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta or Mo and any composite layer between them. The fabrication device is removed and soaked in a solvent. The metal film outside the mask pattern is removed by stripping and other processes, and the metal film on both sides of the narrow channel 3 in the mask pattern is the point contact planar grid 4 .

(8) Cover the insulating material layer 6 on the conductive material layer 7 . Insulating materials, including silicon oxide, aluminum oxide, silicon nitride, or titanium oxide, are deposited by vapor deposition, electron beam evaporation, or sputtering, with a thickness of 10 nm to 800 nm. The substrate temperature during deposition is 10-400°C.

(9) Prepare the surface grid 5 on the insulating material layer 6 by positioning with overlay marks. First, a mask for making the surface gate 5 is prepared on the insulating material layer 6 by conventional photolithography, and then a metal film is deposited on the mask. The metal film includes Al, Au, W, Cr, Ti, Ni, Pt, Ge, Ta or Mo etc. and any composite layer among them, and the thickness is 10-800 nanometers. The mask material is photoresist. The metal film outside the mask pattern is removed by a process such as stripping, and the metal film in the mask pattern left is the metal surface gate 5 . The surface gate 5 on the insulating material layer 6 can also be made of a polysilicon film, and the preparation technology is a known polysilicon gate preparation technology.

(10) If the metal film deposition and alloy annealing processes have not been implemented in the preparation of the source electrode 1 and the drain electrode 2 in step (5), the source electrode and the drain electrode 2 are prepared by conventional photolithography through processes such as perforation, deposition, and alloy annealing. electrode in the drain region. Deposited metals include metal layers such as Pd, Zr, Ag, Gd, Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta, In or Mo and their composite layers, with a thickness of 100-8000 nanometers . Stripping, cleaning, and annealing the alloy in a mixed atmosphere of N ₂ :H ₂ =1-900:0-500 at a temperature of 300-800°C.

(11) The single-electron transistor of the present invention is prepared through perforation and wiring.

The solvent used was acetone.

Quantum dots in narrow channels are induced by the following mechanisms: 1) fluctuation of Si single crystal film thickness, 2) fluctuation of narrow channel width, 3) oxidation rate dependent dry oxygen oxidation process of pattern structure, 4) corrosion and oxidation Induced strain, 5) existence of localized states, 6) nanoparticles at the interface. Therefore, the fabrication process of the transistor of the present invention described above can easily naturally form quantum dots in the narrow channel between the source and the drain. A single-electron transistor with a single quantum dot 13 is realized by using the point-contact planar gate 4 to squeeze and deplete the narrow channel. As shown in Figure 2, the quantum dots (quantum dot 9, quantum dot 10, quantum dot 11 and quantum dot 12) on the edge of the depletion channel of the point contact planar gate, the number of electrons in these quantum dots does not change with the change of the applied electric field, Has no effect on single-electron transistors. Thus, a single-electron transistor with a single quantum dot (that is, only the quantum dot 13 controlling the characteristics of the transistor) is realized. Since the quantum dot is not completely defined by the size of the lithography mask, its size can be much smaller than the limit limited by lithography, so these single-electron transistors can operate at room temperature.

The single-electron transistor of the present invention is prepared by extruding a narrow channel with a point-contact planar gate, and using the principle that a single quantum dot controls the transport characteristics of the narrow channel. Therefore, the size of the quantum dot can reach the atomic scale, and the single-electron transistor can be used in Work at room temperature. It can meet the two basic conditions for the normal operation of single-electron transistors: (1) The resistance between the source and the drain is greater than the quantum resistance R _q = h/e2≈26kΩ (2) The capacitance of the quantum dot is small enough that e ² /2C＞ >k _B T.

The quantum dots of the single-electron transistor of the present invention are naturally formed by self-assembly methods, self-consistent thermal oxidation (pattern-dependent thermal oxidation), or by the fluctuation of disorder potential, so it is easy to form nanoscale quantum dots, that is to say, it The working temperature is high. The electrical characteristics of the single quantum dot control transistor in the narrow channel are ensured by squeezing the narrow channel with the negative bias voltage on the point contact planar gate, which overcomes the complex and difficult-to-control shortcomings of the traditional high-temperature single-electron transistor. Therefore, the single-electron transistor of the present invention is an ideal and stable high-temperature single-electron transistor. More importantly, it can be fabricated using conventional photolithographic nanofabrication techniques. In addition, it also has a wide range of options for making device materials, has universal applicability, and can be used to prepare biomolecular devices.

Compared with the traditional single electron transistor, the single electron transistor of the present invention has the following advantages: 1) simple preparation, 2) stable performance, and 3) high working temperature.

Below in conjunction with accompanying drawing and embodiment the present invention is described in detail:

Fig. 1 is a schematic diagram of the structure of the single-electron transistor of the present invention.

Fig. 2 The narrow channel in the single-electron transistor of the present invention and the multiple quantum dots in the channel.

Figure 3 The principle process of preparing narrow channels and quantum dots by conventional photolithography.

Figure 4 shows the Coulomb oscillation characteristics of a narrow-channel single-electron transistor with a width of 70 nanometers and no external bias on a point-contact planar gate.

Figure 5 shows the Coulomb oscillation characteristics of a narrow-channel single-electron transistor with a width of 70 nanometers and a bias of -116mV on a point-contact planar gate.

Figure 6 shows the Coulomb oscillation characteristics of a narrow-channel single-electron transistor with a width of 30 nanometers and a -60mV bias applied to the point-contact planar gate.

Fig. 7 is the single quantum dot characteristic of the single electron transistor of the present invention.

Marked in the figure:

1. Source 2. Drain 3. Narrow channel 4. Point contact planar gate 5. Surface gate

6. Insulation layer 7. Conductive material layer 8. Substrate 9, 10, 11, 12. Quantum dots

13. A single quantum dot controlling the ideal properties of a single-electron transistor 14. Patterned photoresist mask

Example 1:

A P-type SOI substrate with (001) orientation is selected, the oxygen buried layer in the SOI is the substrate 8 for preparing the single electron transistor of the present invention, and the Si single crystal film on the SOI is the conductive material layer 7 . After cleaning according to the known SOI substrate cleaning method, the conductive Si single crystal film 7 is thinned by repeated oxidation and corrosion methods to make the thickness reach 70 nanometers. The oxidation described above is dry oxidation, which is oxidized in a mixed atmosphere of N ₂ :O ₂ =1:1, and the oxidation temperature is 850°C. In terms of volume ratio, the oxide layer was removed with an etching solution HF:H ₂ O=1:10.

On the thinned Si single crystal film 7 by electron beam lithography, prepare a photoresist PMMA mask with a "+" pattern, and deposit a metal film on the PMMA mask with a photoresist pattern. , the metal film is 50nm Cr/300nm W. The fabrication device is removed and soaked in a solvent. The Cr/W outside the mask pattern is removed by stripping and other processes, and the Cr/W in the remaining mask pattern is the overlay mark of the "+" pattern. The width of the two lines forming the "+" figure is both 1 micron and the length is 2000 microns.

Deposit 20 nm SiO ₂ and 120 nm Si ₃ N ₄ films on the Si single crystal film 7 with overlay marks. Utilize the known reactive ion etching method to remove the 120 nanometer thick Si ₃ N ₄ film outside the active region, remove the exposed 20 nanometer thick SiO ₂ film with HF: H ₂ O=1: 10 etching solution, utilize known The exposed Si single crystal film 7 is oxidized by a wet oxidation method, so as to realize device isolation and fabricate a mesa of the device.

Deposit 20 nm SiO ₂ and 120 nm Si ₃ N ₄ films on the Si single crystal film 7 with overlay marks. Use the overlay mark to position, prepare a mask for arsenic ion implantation on the deposited 20nm SiO ₂ and 120nm Si ₃ N ₄ films by photolithography, and implant 100keV arsenic ions into the mask with a dose of 8×10 ¹⁵ cm ^-2 . After the arsenic ion implantation, the _{120nm thick Si3N4 film} was removed by boiling at 80°C for 38 minutes with undiluted _H3PO4 , and the 20nm thick SiO2 film was removed with HF: _H2O =1: ₁₀ etching _solution . Anneal in a mixed atmosphere of N ₂ :H ₂ =2:1, the temperature is 1080°C, and the annealing temperature time is 7 seconds.

Using the positioning of the overlay mark, the pattern mask for making the narrow channel 3 is directly prepared on the Si single crystal film 7 with the overlay mark by electron beam lithography, and the mask material is PMMA film of 120 nanometers. Utilize the etching method of electron cyclotron resonance dry method to etch the Si single crystal film 7 with pattern mask in SF ₆ atmosphere and 120 ℃, the part without mask on the Si single crystal film 7 is etched away, on the Si single crystal film 7 The narrow channel 3 connecting the source 1 and the drain 2 is realized on the crystal film 7, the etching depth is 70 nanometers, and the width of the formed narrow channel 3 is 80 nanometers. Dry oxygen oxidation is used to further reduce the width of the narrow channel and form quantum dots in the narrow channel. The gas fed during the dry oxygen oxidation is O ₂ :N ₂ =1:3, the oxidation temperature is 780° C., and the oxidation time is 3 minutes.

The point contact planar grid 4 is prepared by self-aligned metal deposition method. 15nm Cr/30nm W was deposited by electron beam evaporation equipment and multi-angle evaporation method, soaked in acetone for 200 minutes, and the soaking temperature was 60°C. Take it out from the acetone and put it in water for 10 minutes, blow it dry with nitrogen, the flow rate and pressure of nitrogen are 100mL/min and 1×10 ⁵ Pa, respectively.

The SiO ₂ insulating material layer 6 is evaporated and deposited by electron beam evaporation equipment, and its thickness is 80 nanometers.

The contact holes are etched using known overlay means and HF buffered etchant. Evaporate 1 μm of Al by electron beam evaporation equipment, and anneal the alloy in a mixed atmosphere of N ₂ :H ₂ =3:1 at a temperature of 450°C.

The surface gate 5 of the transistor of the present invention is prepared by using the known preparation method of the Al surface gate of the MOS device. The Si single-electron transistor of the present invention is prepared by wire connection. As shown in Figure 1-2. The positive bias of the surface gate causes the two-dimensional electron gas in the inversion layer, and adjusts its concentration, that is, the number of electrons in the quantum dot. The point contact with the planar gate enables a single quantum dot in a narrow channel to control the characteristics of the transistor.

Example 2:

A P-type SOI substrate with (001) orientation is selected, the oxygen buried layer in the SOI is the substrate 8 for preparing the single electron transistor of the present invention, and the Si single crystal film on the SOI is the conductive material layer 7 . After cleaning according to the known SOI substrate cleaning method, the conductive Si single crystal film 7 is thinned by repeated oxidation and corrosion methods to make the thickness reach 120 nanometers. The oxidation described above is dry oxygen oxidation in a mixed atmosphere of N ₂ :O ₂ =2:1, and the oxidation temperature is 890°C. In terms of volume ratio, the oxide layer was removed with an etching solution HF:H ₂ O=1:20.

Utilize the conventional photolithography method on the thinned Si single crystal film 7 to prepare a rectangular photoresist AZ1400 mask, and deposit a metal film on the AZ1400 mask with a photoresist pattern, and the metal film is 50nm Cr/300nm W. The fabrication device is removed and soaked in a solvent. The Cr/W outside the mask pattern is removed by stripping and other processes, leaving the Cr/W in the mask pattern as a rectangular overlay mark. Its rectangular shape is 100 microns long and 20 microns wide.

A 25 nm SiO ₂ film and a 130 nm Si ₃ N ₄ film were deposited on the Si single crystal film 7 with overlay marks. Utilize the known reactive ion etching method to remove the 130 nanometer thick Si ₃ N ₄ film outside the active region, remove the exposed 25 nanometer thick SiO ₂ film with HF: H ₂ O=1: 20 etchant, utilize existing The exposed Si single crystal film 7 is oxidized by the known wet oxygen oxidation method, so as to realize the isolation of the device and manufacture the mesa of the device.

A 26 nm SiO ₂ film and a 136 nm Si ₃ N ₄ film were deposited on the Si single crystal film 7 with overlay marks. Using overlay marks to position, a mask for arsenic ion implantation was prepared on the deposited 26nm _SiO2 film and _{136nm Si3N4} film by photolithography, and 100keV arsenic ions were implanted into the mask with a dose of 8×10 ¹⁵ cm ^-2 . After the arsenic ion implantation, the _{136nm thick Si3N4 film was} removed by boiling with undiluted _H3PO4 at 80°C for 40 minutes, and the 26nm thick _SiO2 film was removed with HF: _H2O =1:10 etching solution. Anneal in a mixed atmosphere of N ₂ :H ₂ =5:1, the temperature is 1080°C, and the annealing temperature time is 9 seconds.

Using the overlay marks for positioning, a pattern mask for making the narrow channel 3 is prepared on the Si single crystal film 7 with the overlay marks by phase-shift mask photolithography, and the mask material is AZ1400. Utilize the etching method of electron cyclotron resonance method to etch the Si single crystal film 7 with pattern mask in SF ₆ atmosphere and 120 ℃, the part without mask on the Si single crystal film 7 is etched away, on the Si single crystal A narrow channel 3 connecting the source 1 and the drain 2 is realized on the film 7, the etching depth is 120 nanometers, and the width of the formed narrow channel 3 is 320 nanometers. Dry oxygen oxidation is used to further reduce the width of the narrow channel and form quantum dots in the narrow channel. The gas fed during the dry oxygen oxidation is O ₂ :N ₂ =1:3, the oxidation temperature is 780° C., and the oxidation time is 12 minutes.

The point contact planar grid 4 is prepared by self-aligned metal deposition method. 20nm Cr/100nm W was deposited by multi-angle evaporation using electron beam evaporation equipment, soaked in acetone for 200 minutes, and the soaking temperature was 60°C. Take it out from the acetone and put it in water for 10 minutes, blow it dry with nitrogen, the flow rate and pressure of nitrogen are 160mL/min and 2×10 ⁵ Pa, respectively.

The SiO ₂ insulating material layer 6 is evaporated and deposited by electron beam evaporation equipment, and its thickness is 100 nanometers.

Use the overlay mark to position, prepare the AZ1400 pattern mask for making the surface grid 5 on the Si single crystal film 7 after annealing by photolithography and known hollowing out technology, utilize electron beam evaporation method on its mask Deposit an Al film with a thickness of 1 μm, remove the Al film outside the mask pattern by stripping and other processes, and leave the Al film in the mask pattern as the surface gate 5

The Si single-electron transistor of the present invention is prepared by wire connection.

Example 3:

Narrow channel 3 in embodiment 1 and embodiment 2 also can realize with following method:

The SiO ₂ mask used to make the narrow channel 3 is prepared by conventional photolithography and SiO ₂ deposition methods, as shown in Figure 3 14 . The defined narrow channels of the _SiO2 mask follow the [110] crystallographic trend of the Si single crystal film 7, which is 90 nm thick.

Use KOH:H2O=1:3 etchant to carry out anisotropic selective etching on the _SiO2 mask with 3 patterns made of narrow channels. In this etching solution, the {111} crystal plane is the etching stop plane. Corrosion stops automatically when the {111} crystal planes on both sides of the narrow channel intersect.

Since the thickness of the Si single crystal film 7 on the oxygen buried layer 8 can be precisely controlled, the geometric width of the narrow channel can be completely repeated and controlled. The geometric size of the narrow channel is not affected by the size of the mask pattern and the thickness of the Si single crystal film can be controlled in the order of angstroms (A°), so the single electron transistor of the present invention prepared by this method can work at room temperature.

Example 4:

The original Si single crystal film 7 in Example 3 is thinned to 20 nanometers, and a back gate is prepared on the substrate 8 according to the preparation method of the narrow channel 3 in Example 3, using a known back gate preparation method. This back gate replaces the role of the surface gate 5 . The step of further reducing the width of the narrow channel by using the dry oxygen oxidation method in Embodiment 3 is omitted, and the preparation steps of the insulating layer 6 and the surface gate 5 in Embodiment 3 are also omitted.

Thus, the single-electron transistor of the present invention is realized. This is actually a modification of the single-electron transistor of the present invention.

Example 5:

Narrow channel 3 in embodiment 1 and embodiment 2 also can realize with following method:

Using overlay mark positioning, adopting the preparation method of "nano-electrode pair" reported in "Physics" No. 1, 2001, to realize the point-contact planar gate 4 and narrow channel 3 of the single-electron transistor of the present invention. Utilizing this "nano-electrode pair" and adopting the preparation process steps described in Examples 1, 2 and 3, a very ideal high-temperature single-electron transistor can be prepared.

The characteristics and behavior of the single-electron transistor of the present invention will be described below in combination with the actual measurement results of the single-electron transistor prepared in this embodiment.

Figure 4 shows the Coulomb oscillation characteristics of a 70nm wide and narrow channel single electron transistor. As the bias voltage (V ₅ ) on the surface gate 5 decreases, the current (I ₂ ) on the drain 2 decreases and exhibits non-periodic oscillations. It should be emphasized that it decreases and increases in jumps at D1, D2, D3 and D4. This behavior mirrors that of multiple quantum dots in narrow channels. Gradually increasing the negative bias voltage (V ₄ ) on the point contact planar gate 4 squeezes the effective width of the narrow channel and gradually depletes the quantum dot area at the edge of the channel. When V ₄ <-114mV, the number of electrons in the remaining quantum dots does not change with the external field, that is, only one quantum dot 3 in the narrow channel controls the electrical characteristics of the transistor. At this time, the transistor shows a rational periodic Coulomb oscillation, as shown in Figure 5. The observed period is 0.64V, that is to say, the capacitance between the surface grid 5 and the quantum dot 13 is 0.25aF. Tests on multiple devices have shown that the smaller the defined narrow channel width, the easier this periodic Coulomb oscillation is to be observed. Fig. 6 shows the Coulomb oscillation characteristics of the 30nm wide and narrow channel single electron transistor when V ₄ <-60mV. This Coulomb oscillation curve is more ideal, and its period is 0.55V. As the experimental temperature increases, the Coulomb oscillation becomes weaker, but the period remains unchanged, as shown in Figure 7. It can be seen from the figure that the transistor can work above 90K.

Embodiment 6:

A P-type SOI substrate with (001) orientation is selected, the oxygen buried layer in the SOI is the substrate 8 for preparing the single electron transistor of the present invention, and the Si single crystal film on the SOI is the conductive material layer 7 . After cleaning according to the known SOI substrate cleaning method, the conductive Si single crystal film 7 is thinned by repeated oxidation and corrosion methods to make the thickness reach 120 nanometers. The oxidation described above is dry oxygen oxidation in a mixed atmosphere of N ₂ :O ₂ =2:1, and the oxidation temperature is 880°C. In terms of volume ratio, the oxide layer was removed with an etching solution HF:H ₂ O=1:20.

On the thinned Si single crystal film 7 by electron beam lithography, prepare a photoresist PMMA mask with a "+" pattern, and deposit a metal film on the PMMA mask with a photoresist pattern. , the metal film is 30nm Cr/200nm W. The fabrication device is removed and soaked in a solvent. The Cr/W outside the mask pattern is removed by stripping and other processes, and the Cr/W in the remaining mask pattern is the overlay mark of the "+" pattern. The width of the two lines forming the "+" figure is both 2 micrometers and the length is 2000 micrometers.

Deposit 30 nm SiO ₂ and 120 nm Si ₃ N ₄ films on the Si single crystal film 7 with overlay marks. Utilize the known reactive ion etching method to remove the 120 nanometer thick Si ₃ N ₄ film outside the active region, remove the exposed 30 nanometer thick SiO ₂ film with HF: H ₂ O=1: 20 etching solution, utilize known The wet oxygen oxidation method oxidizes the exposed Si single crystal film 7 to realize device isolation and fabricate device mesa.

Deposit 30 nm SiO ₂ and 120 nm Si ₃ N ₄ films on the Si single crystal film 7 with overlay marks. Use the overlay mark to position, prepare a mask for arsenic ion implantation on the deposited 30nm SiO ₂ and 120nm Si ₃ N ₄ films by photolithography, and implant 100keV arsenic ions into the mask with a dose of 6×10 ¹⁵ cm ^-2 . After the arsenic ion implantation, the _{120nm thick Si3N4 film} was removed by boiling at 80°C for 42 minutes with undiluted _H3PO4 , and the 30nm thick SiO2 film was removed with HF: _H2O =1: _{20 etching} solution. Anneal in a mixed atmosphere of N ₂ :H ₂ =3:1, the temperature is 1060°C, and the annealing temperature time is 8 seconds. A patterned AZ1400 photoresist mask for making the source electrode 1 and the drain electrode 2 is prepared on the conductive material layer 7 by conventional photolithography, and a 1 micron thick Al film is deposited on the photoresist pattern mask. The fabrication device is removed and soaked in a solvent. The metal film outside the mask pattern is removed by stripping and other processes, and the remaining metal film in the mask pattern is the source electrode 1 and the drain electrode 2 after alloy annealing, and the annealing temperature is 450°C.

Utilize the positioning of the overlay mark, and directly prepare a pattern mask for making the narrow channel 3 on the Si single crystal film 7 with the overlay mark by electron beam lithography, and the mask material is PMMA film of 160 nanometers. Utilize the etching method of electron cyclotron resonance dry method, in SF ₆ atmosphere and 120 ℃ etch the Si single crystal film 7 that has pattern mask, the part that does not have mask on Si single crystal film 7 is etched away, on Si The narrow channel 3 connecting the source 1 region and the drain 2 region is realized on the single crystal film 7, the etching depth is 120 nanometers, and the width of the formed narrow channel 3 is 12 nanometers. Fluctuations in the width of the narrow channel 3 lead to the formation of quantum dots in the narrow channel.

The point contact planar grid 4 is prepared by self-aligned metal deposition method. 15nm Cr/30nm W was deposited by electron beam evaporation equipment and multi-angle evaporation method, soaked in acetone for 200 minutes, and the soaking temperature was 60°C. Take it out from the acetone and put it in water for 10 minutes, blow it dry with nitrogen, the flow rate and pressure of nitrogen are 100mL/min and 1×10 ⁵ Pa, respectively.

The SiO ₂ insulating material layer 6 is evaporated and deposited by electron beam evaporation equipment, and its thickness is 120 nanometers.

The surface gate 5 of the transistor of the present invention is prepared by using the known preparation method of the Al surface gate of the MOS device. The Si single-electron transistor of the present invention is prepared by wire connection. As shown in Figure 1-2. The positive bias of the surface gate causes the two-dimensional electron gas in the inversion layer, and adjusts its concentration, that is, the number of electrons in the quantum dot. The point contact with the planar gate enables a single quantum dot in a narrow channel to control the characteristics of the transistor.

Claims (30)

1. the preparation method of a point-contact planar grid type single-electronic transistor, it is characterized in that: preparation process comprises:

1) selects the material that on substrate (8), has been coated with conductive material layer (7) for use, by oxidation repeatedly, corroding method attenuate conductive material layer (7); Thickness up to conductive material layer (7) reaches the 2-300 nanometer;

2) conductive material layer behind attenuate (7) is gone up the preparation overlay mark, and the film of the part table top that the utilization corrosion forms, the groove of corrosion or deposition is as overlay mark;

3) utilize the overlay mark location, the preparation mask, corrosion has the conductive material layer (7) of overlay mark, wherein, erode the part in conductive material layer (7) mask pattern, the outer conductive material layer (7) of mask pattern is the table top of making device, and described corrosion is dry etching or wet etching;

4) utilize overlay mark location, go up preparation and be used for the mask that ion injects having the conductive material layer of overlay mark (7), inject ion to mask, after ion injects, remove the mask that is used for the ion injection, the element that the high-temperature annealing activation ion injects, its annealing temperature is 500-1200 ℃;

5) utilize the overlay mark location, go up preparation in order to make the figure photoresist mask of source electrode (1) and drain electrode (2) at accurately machined conductive material layer (7) by photoetching; Depositing metallic films on band photoresist figure mask, alloy annealing; Its thickness of metal film is the 50-900 nanometer; Taking-up is made device and is put into solvent and soak, and removes the outer metal film of mask pattern, and the metal film ECDC annealing of gold in the mask pattern that stays is source electrode (1) and drain electrode (2), and its annealing temperature is 300-800 ℃;

6) utilize the overlay mark location, directly go up preparation figure mask at conductive material layer (7), utilize dry corrosion method or wet corrosion method corrosion conductive material layer (7), to there be the partial corrosion of mask to fall on the conductive material layer (7), go up the narrow passage (3) that preparation connects source electrode (1) district and drain electrode (2) district at conductive material layer (7), to the conductive material layer (7) that does not comprise the self assembly quantum dot, adopt excessive erosion or lateral encroaching process in narrow passage (3), to form quantum dot again;

7) utilize the overlay mark location, go up preparation in order to make the photoresist figure mask of point-contact planar grid (4) at the conductive material layer (7) of the narrow passage that has prepared (3), and depositing metallic films thereon, or with being in harmony directly depositing metallic films on the photoresist figure mask of preparation narrow passage (3) of sedimentation certainly, taking-up is made device and is put into solvent and soak, remove the outer metal film of mask pattern, the metal film on the narrow passage in the mask pattern (3) both sides is point-contact planar grid (4);

8) go up covering insulating material layer (6) at conductive material layer (7); Its thickness is 10 nanometers～800 nanometers, and the underlayer temperature during deposition is 10-400 ℃;

9) utilize the overlay mark location, go up preparation surperficial grid (5) at insulation material layer (6); At first go up preparation in order to make the mask of surperficial grid (5), then depositing metallic films on mask at insulation material layer (6); Remove the outer metal film of mask pattern, the metal film in the mask pattern that stays is metal surface grid (5); Or utilize surperficial grid (5) on the polysilicon gate fabrication techniques insulation material layer (6);

10) just prepared point-contact planar grid type single-electronic transistor through perforation, lead-in wire.

2. the preparation method of single-electronic transistor as claimed in claim 1, it is characterized in that: the oxidizing gas of described step 1) (with volume ratio) is N ₂: O ₂The gaseous mixture of=0-900: 1-500; Oxidizing temperature is 350-1200 ℃; The corrosive liquid (with volume ratio) of corrosion usefulness is HF: H ₂O=1-100: 1-5000 or HCl: H ₂The solution of O=1-100: 1-5000.

3. the preparation method of single-electronic transistor as claimed in claim 1, it is characterized in that: the width of described narrow passage (3) is 3 nanometers-800 nanometers.

4. the preparation method of single-electronic transistor as claimed in claim 1, it is characterized in that: the thickness of described insulation material layer (6) is 10 nanometers～800 nanometers.

5. the preparation method of single-electronic transistor as claimed in claim 1, it is characterized in that: described substrate is 1) silicon on the semiconducting insulation body; 2) oxide material; 3) glass, SiC, Ge, silicon or the monocrystalline silicon of one deck oxide is arranged on silicon face; Or 4) semi-conducting material of semi-conducting material of Can Zaing or non-doping.

6. the preparation method of single-electronic transistor as claimed in claim 5, it is characterized in that: described oxide material is Al ₂O ₃, silica, magnesium oxide or strontium titanates.

7. the preparation method of single-electronic transistor as claimed in claim 5, it is characterized in that: the semi-conducting material of described non-doping is GaAs, Cr-GaAs, Si or InP; The semi-conducting material that mixes is N ⁺-GaAs, N ⁺-InP or N ⁺-GaN.

8. the preparation method of single-electronic transistor as claimed in claim 1, it is characterized in that: described electric conducting material comprises 1) Si, Ge or SiGe semiconductor element cellulosic material, 2) GaN, NAlGaAs, NInGaAs, NInAlGaAs, GaAs, AlGaAs, InGaAs or InAlGaAs semiconducting compound, or 3) by silicon, magnesium, phosphonium ion, nitrogen ion, arsenic ion, oxonium ion or the boron fluoride ion doping composite material in Si, Ge, SiGe, GaN, NAlGaAs, NInGaAs, NInAlGaAs, GaAs, AlGaAs, InGaAs or the InAlGaAs semi-conducting material.

9. the preparation method of single-electronic transistor as claimed in claim 1, it is characterized in that: described insulating material comprises silica, aluminium oxide, silicon nitride or titanium oxide.

10. the preparation method of single-electronic transistor as claimed in claim 1, it is characterized in that: described mask material comprises 1) PMMA, ZEP, AZ or SAL photoresist, 2) Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta or Mo metal level and any composite bed between them, or 3) silica, aluminium oxide, silicon nitride or titanium oxide insulating material.

11. the preparation method of single-electronic transistor as claimed in claim 1 is characterized in that: described surperficial grid are deposited metal films, or the N through depositing, injecting and anneal ⁺The doped polycrystalline silicon fiml.

12. the preparation method of single-electronic transistor as claimed in claim 1 is characterized in that: described metal film is Pd, Zr, Ag, Gd, Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta, In or Mo metal level and the composite bed arbitrarily between them.

13. the preparation method of single-electronic transistor as claimed in claim 1 is characterized in that: the corrosive liquid that described wet etching is used is (by volume) H ₂SO ₄: H ₂O ₂: H ₂O=1-100: 1-60: 1-500, NH ₄OH: H ₂O ₂: H ₂O=1-100: 1-60: 1-5000, H ₃PO ₄: H ₂O ₂: H ₂O=1-100: 1-60: 1-500, H ₂SO ₄: H ₃PO ₄: H ₂O=1-100: 1-60: 0-500, KOH: H ₂O=1-100: 1-5000, NaOH: H ₂O=1-100: 1-5000, HF: H ₂O=1-100: 1-5000 or HCl: H ₂The solution of O=1-100: 1-5000.

14. the preparation method of single-electronic transistor as claimed in claim 1 is characterized in that: the element of described injection comprises silicon, phosphonium ion, nitrogen ion, arsenic ion, oxonium ion, nitrogen ion or boron fluoride ion.

15. the preparation method of a point-contact planar grid type single-electronic transistor, it is characterized in that: preparation process comprises:

1) selects the material that on substrate (8), has been coated with conductive material layer (7) for use, by oxidation repeatedly, corroding method attenuate conductive material layer (7); Thickness up to conductive material layer (7) reaches the 2-300 nanometer;

2) conductive material layer behind attenuate (7) is gone up the preparation overlay mark, and the film of the part table top that the utilization corrosion forms, the groove of corrosion or deposition is as overlay mark;

3) utilize the overlay mark location, the preparation mask, corrosion has the conductive material layer (7) of overlay mark, wherein, erode the part in conductive material layer (7) mask pattern, the outer conductive material layer (7) of mask pattern is the table top of making device, and described corrosion is dry etching or wet etching;

4) utilize overlay mark location, go up preparation and be used for the mask that ion injects having the conductive material layer of overlay mark (7), inject ion to mask, after ion injects, remove the mask that is used for the ion injection, the element that the high-temperature annealing activation ion injects, its annealing temperature is 500-1200 ℃;

5) utilize the overlay mark location, directly go up preparation figure mask at conductive material layer (7), utilize dry corrosion method or wet corrosion method corrosion conductive material layer (7), to there be the partial corrosion of mask to fall on the conductive material layer (7), go up the narrow passage (3) that preparation connects source electrode (1) district and drain electrode (2) district at conductive material layer (7), to the conductive material layer (7) that does not comprise the self assembly quantum dot, adopt the dry-oxygen oxidation process in narrow passage (3), to form quantum dot again;

6) utilize the overlay mark location, go up preparation in order to make the photoresist figure mask of point-contact planar grid (4) at the conductive material layer (7) of the narrow passage that has prepared (3), and depositing metallic films thereon, or with being in harmony directly depositing metallic films on the photoresist figure mask of preparation narrow passage (3) of sedimentation certainly, taking-up is made device and is put into solvent and soak, remove the outer metal film of mask pattern, the metal film on the narrow passage in the mask pattern (3) both sides is point-contact planar grid (4);

7) go up covering insulating material layer (6) at conductive material layer (7); Its thickness is 10 nanometers～800 nanometers, and the underlayer temperature during deposition is 10-400 ℃;

8) utilize the overlay mark location, go up preparation surperficial grid (5) at insulation material layer (6); At first go up preparation in order to make the mask of surperficial grid (5), then depositing metallic films on mask at insulation material layer (6); Remove the outer metal film of mask pattern, the metal film in the mask pattern that stays is metal surface grid (5); Or utilize surperficial grid (5) on the polysilicon gate fabrication techniques insulation material layer (6);

9) utilize the overlay mark location, go up preparation in order to make the figure photoresist mask of source electrode (1) and drain electrode (2) at accurately machined conductive material layer (7) by photoetching; Depositing metallic films on band photoresist figure mask, its thickness of metal film is the 50-900 nanometer; The electrode in alloy annealing preparation source and drain region;

10) just prepared point-contact planar grid type single-electronic transistor through perforation, lead-in wire.

16. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: the oxidizing gas of described step 1) (with volume ratio) is N ₂: O ₂The gaseous mixture of=0-900: 1-500; Oxidizing temperature is 350-1200 ℃; The corrosive liquid (with volume ratio) of corrosion usefulness is HF: H ₂O=1-100: 1-5000 or HCl: H ₂The solution of O=1-100: 1-5000.

17. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: the width of described narrow passage (3) is 3 nanometers-800 nanometers.

18. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: the thickness of described insulation material layer (6) is 10 nanometers～800 nanometers.

19. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: described substrate is 1) silicon on the semiconducting insulation body; 2) oxide material; 3) glass, SiC, Ge, silicon or the monocrystalline silicon of one deck oxide is arranged on silicon face; Or 4) semi-conducting material of semi-conducting material of Can Zaing or non-doping.

20. the preparation method of single-electronic transistor as claimed in claim 19 is characterized in that: described oxide material is Al ₂O ₃, silica, magnesium oxide or strontium titanates.

21. the preparation method of single-electronic transistor as claimed in claim 19 is characterized in that: the semi-conducting material of described non-doping is GaAs, Cr-GaAs, Si or InP; The semi-conducting material that mixes is N ⁺-GaAs, N ⁺-InP or N ⁺-GaN.

22. the preparation method of single-electronic transistor as claimed in claim 15, it is characterized in that: described electric conducting material comprises 1) Si, Ge or SiGe semiconductor element cellulosic material, 2) GaN, NAlGaAs, NInGaAs, NInAlGaAs, GaAs, AlGaAs, InGaAs or InAlGaAs semiconducting compound, or 3) by silicon, magnesium, phosphonium ion, nitrogen ion, arsenic ion, oxonium ion or the boron fluoride ion doping composite material in Si, Ge, SiGe, GaN, NAlGaAs, NInGaAs, NInAlGaAs, GaAs, AlGaAs, InGaAs or the InAlGaAs semi-conducting material.

23. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: described insulating material comprises silica, aluminium oxide, silicon nitride or titanium oxide.

24. the preparation method of single-electronic transistor as claimed in claim 15, it is characterized in that: described mask material comprises 1) PMMA, ZEP, AZ or SAL photoresist, 2) Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta or Mo metal level and any composite bed between them, or 3) silica, aluminium oxide, silicon nitride or titanium oxide insulating material.

25. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: described surperficial grid are deposited metal films, or the N through depositing, injecting and anneal ⁺The doped polycrystalline silicon fiml.

26. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: described metal film is Pd, Zr, Ag, Gd, Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta, In or Mo metal level and the composite bed arbitrarily between them.

27. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: the corrosive liquid that described wet etching is used is (by volume) H ₂SO ₄: H ₂O ₂: H ₂O=1-100: 1-60: 1-500, NH ₄OH: H ₂O ₂: H ₂O=1-100: 1-60: 1-5000, H ₃PO ₄: H ₂O ₂: H ₂O=1-100: 1-60: 1-500, HSO ₄: H ₃PO ₄: H ₂O=1-100: 1-60: 0-500, KOH: H ₂O=1-100: 1-5000, NaOH: H ₂O=1-100: 1-5000, HF: H ₂O=1-100: 1-5000 or HCl: H ₂The solution of O=1-100: 1-5000.

28. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: described step 9) annealing conditions is at N ₂: H ₂Alloy annealing in the mixed atmosphere of=1-900: 0-500, its annealing temperature is 300-800 ℃.

29. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: the element of described injection comprises silicon, phosphonium ion, nitrogen ion, arsenic ion, oxonium ion, nitrogen ion or boron fluoride ion.

30. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: the gas that feeds during described dry-oxygen oxidation is O ₂: N ₂=1-4: 0-20, the temperature of oxidation is 500-980 ℃.

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