CN1160797C - Point-contact planar grid type single-electron transistor and its preparing process - Google Patents
Point-contact planar grid type single-electron transistor and its preparing process Download PDFInfo
- Publication number
- CN1160797C CN1160797C CNB011008342A CN01100834A CN1160797C CN 1160797 C CN1160797 C CN 1160797C CN B011008342 A CNB011008342 A CN B011008342A CN 01100834 A CN01100834 A CN 01100834A CN 1160797 C CN1160797 C CN 1160797C
- Authority
- CN
- China
- Prior art keywords
- preparation
- material layer
- mask
- conductive material
- electronic transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention relates to a microelectronic device and a micro-machining method, particularly to a point-contact planar grid type high temperature single-electron transistor and a preparing method thereof. The present invention is made by an electron beam photoetching method and a conventional photoetching method. A source electrode and a drain electrode are arranged in an electric conducting material layer on a substrate. A narrow channel with quantum dots is arranged between the source electrode and the drain electrode, and both sides of the narrow channel are provided with point-contact planar grids. A settled insulation material layer is arranged on an electric conducting material layer, and surface grids are covered on the insulation material layer. The size of the quantum dot of the single electron transistor of the present invention can reach the dimension of an atom. The present invention can work at room temperature and satisfy two main conditions of regular actions of the single electron transistor.
Description
The invention belongs to microelectronic component and micro-processing method, particularly relate to a kind of point-contact planar grid type high temperature single electron product body pipe and utilize the method for this device of nanometer technology prepared.
The importance of nanometer technology is fully paid attention to by people, and the reasearch funds of exploitation nanometer technology grow with each passing day.The core of its research is exactly the research of nano material, nanofabrication technique and nano-device.The research of nano material has obtained the development of advancing by leaps and bounds, but the research of nano-device is just risen and made slow progress.Single-electronic transistor is one of nano-device present success and that gain public acceptance, is most promising nano-device, is reported as " physics today " (Physics Today, January 1994).The conditional electronic transistor is realized functions such as switch, vibration and amplification by the collective motion of the electronics in groups of control more than ten million; The behavior that single-electronic transistor then needs only by an electronics just can realize specific function.Along with the raising of integrated level, power consumption has become the restraining factors of microelectronic device circuits stability.The element that constitutes with single-electronic transistor can improve microelectronic integrated level greatly and can make power consumption be reduced to 10
-5Single-electronic transistor so extremely low power consumption can solve the destabilizing factor problem that causes because of heat radiation in the existing integrated circuit.Its Highgrade integration degree can surmount the limit of present large scale integration far away, and can reach the limit that Heisenberg's uncertainty principle sets and become in the future can not substituted new device.
Single-electronic transistor comprises source electrode, drain electrode, with the quantum dot or coulomb island of source-drain electrode weak coupling and the electrochemical potential that can be used to regulate quantum dot promptly control the grid of electron number in the quantum dot.Its two primary conditions of regular event palpus: the resistance between (1) source, drain electrode is greater than the quantum resistance R
q=h/e2 ≈ 26k Ω; (2) the enough little e that makes of the electric capacity of quantum dot
2/ 2C＞＞k
BT.Wherein: C is the electric capacity of quantum dot, k
BBe Boltzmann constant, T is a working temperature.When the effective diameter of quantum dot during less than 10 nanometers, single-electronic transistor just can be at working and room temperature.Therefore be to improve the working temperature of single-electronic transistor and the physical dimension that its anti-jamming capacity just must reduce quantum dot.
The main technology of preparing of high-temperature single electron transistor has at present: (1) " Applied Physics wall bulletin " [Appl.Phys.Lett., 1996,68,34-36] the scanning probe microscopy SPM technology of report, (2) focused ion beam is injected FIB technology [Appl.Phys.Lett., 1993,63,51-53], (3) self-assembling technique [Appl.Phys.Lett., 1997,71,2294-2296], (4) electron beam lithography [Appl.Phys.Lett., 1996,69,406-4086].Scanning probe microscopy SPM technology can prepare the room temperature single-electronic transistor of atomic scale, but reason such as, repeatability oversize because of its process time and stability is all not so good seldom is used in the actual device preparation.Focused ion beam is injected the nanostructure that the FIB technology has certain damage to device and is difficult to realize atomic scale, thereby also uses seldom in real device preparation.The method for preparing nanostructure with self-assembling technique is quite general, be all to have obtained using widely at physics, chemistry and biological field, but it has significant limitation: the 1) uncertainty of position, 2) physical dimension and inhomogeneous in spatial distribution, 3) and the mismatch of device technology.Thereby the high-temperature single electron transistor that this prepared goes out has the shortcoming of complicated difficult control.Electron beam lithography is mainly used in the preparation of single-electronic transistor at present.It is mode by an electron beam exposure and development photoresist quantum dot of realizing single-electronic transistor.Because the limit of electron beam lithography is in 30 nanometers, the diameter of prepared quantum dot is greater than 50 nanometers.Thereby preparation at present can be integrated stable single-electronic transistor all can only be operated in very low temperature region.
The objective of the invention is to overcome the deficiency of prior art, avoid the complexity of device preparation technology and device can only be operated in the characteristic of very low temperature region, thereby a kind of point-contact planar grid type single-electronic transistor and preparation method thereof is provided.Method of the present invention also can be used at aspects such as preparation other nano-device, biomolecular device and the microminiaturizations of realization biochip.
The object of the present invention is achieved like this:
Single-electronic transistor of the present invention is to constitute like this, as shown in Figure 1: source electrode 1 and drain electrode 2 are arranged in the conductive material layer 7 on substrate 8; Between source electrode and drain electrode is one to contain the narrow passage 3 of quantum dot, and its width is the 3-800 nanometer; On narrow passage 3 both sides are point-contact planar grid 4, by the extruding of the back bias voltage on the point-contact planar grid narrow passage are further narrowed down, thereby cause only being subjected to the narrow passage of single quantum point control.Be the insulation material layer 6 of a deposition on conductive material layer 7, its thickness is the 10-800 nanometer; On insulation material layer 6, be coated with surperficial grid 5.Quantum dot in the narrow passage is formed by reasons such as burn into oxidations in self-assembling method in the material preparation or the technical process.If conductive material layer this as a non-conduction layer, by being added in the positive bias on the surperficial grid, form the transoid two-dimensional electron gas at conductive material layer, and regulate, the electron number in the single quantum dot of control and the electric current between source-drain electrode.If conductive material layer this as a doping conductting layer, then also should deposit between point-contact planar grid and the narrow passage or oxidation one insulating barrier, at this moment surperficial grid are mainly used to regulate, control electron number in the single quantum dot and the electric current between source-drain electrode.On substrate, can further cover the buffering epitaxial loayer that following material is made: 1) Si, Ge or GeSi semiconductor element cellulosic material, 2) GaN, NAlGaAs, NInGaAs, NAlGaAs, NInAlGaAs, GaAs, AlGaAs, InGaAs or InAlGaAs semiconducting compound, 3) by silicon, phosphonium ion, the nitrogen ion, arsenic ion, oxonium ion or boron fluoride ion etc. are doped to Si, Ge, GeSi, GaN, NAlGaAs, NInGaAs, NInAlGaAs, GaAs, AlGaAs, composite material in InGaAs or the InAlGaAs semi-conducting material, 4) above-mentioned 1), 2) and 3) but described lattice constant is close and the material of combination in any, 5) silica, aluminium oxide, insulating material such as silicon nitride or titanium oxide.These buffering epitaxial loayers can further improve the quality of conductive material layer.If the buffering epitaxial loayer is a non-doped layer, it can be used as the insulating barrier of doped substrate and conductive material layer, to stop the generation of leakage current.The buffering epitaxial loayer can be identical with the various materials that constitute conductive material layer, but the combination of material is inequality, and structure is also inequality.
Described substrate can be 1) silicon (being SOI) on the semiconducting insulation body; 2) oxide material is as sapphire Al
2O
3, silicon oxide sio
2, magnesium oxide MgO or strontium titanates SrTiO
3Deng; Or 3) glass, SiC, Ge, silicon or the monocrystalline silicon of one deck oxide is arranged from the teeth outwards; 4) semi-conducting material of semi-conducting material of Can Zaing or non-doping, the semi-conducting material of described non-doping are GaAs, Cr-GaAs, Si or InP; The semi-conducting material that mixes is N
+-GaAs, N
+-InP or N
+-GaN.
Described electric conducting material comprises 1) Si, Ge or SiGe semiconductor element cellulosic material, 2) GaN, NAlGaAs, NInGaAs, NInAlGaAs, GaAs, AlGaAs, InGaAs or InAlGaAs semiconducting compound, or 3) be doped to composite material in Si, Ge, SiGe, GaN, NAlGaAs, NInGaAs, NInAlGaAs, GaAs, AlGaAs, InGaAs or the InAlGaAs semi-conducting material by silicon, magnesium, phosphonium ion, nitrogen ion, arsenic ion, oxonium ion or boron fluoride ion etc.
Described insulating material comprises silica, aluminium oxide, silicon nitride or titanium oxide.
Described point-contact planar grid comprise metal level and any composite beds between them such as Al, Au, W, Cr, Ti, Ni, Pt, Ge, Ta or Mo.
Described surperficial grid are deposited metal films, or the N+ doped polycrystalline silicon fiml through depositing, injecting and anneal.
Described metal film is metal level and any composite beds between them such as Al, Au, W, Cr, Ti, Ni, Pt, Ge, Ta, Mo or In.
The preparation method of single-electronic transistor of the present invention is simple, both can prepare in conjunction with advanced person's electronic beam photetching process, can prepare in conjunction with the photolithographic nanoprocessing method of routine again.Method of the present invention has versatility; can prepare single-electronic transistor of the present invention with various materials, material comprises thin-film material, organic compound material, biomolecule material and their combination or the composite material etc. of the doping and the non-doping of modulation doping two-dimensional electron gas structural material, the material that contains nano particle or quantum dot, thin layer.Utilize the biomolecule material can prepare biomolecular device.
Preparation single-electronic transistor method of the present invention may further comprise the steps, in volume ratio:
(1) selects the material that on substrate 8, has been coated with conductive material layer 7 for use, by oxidation repeatedly, corroding method attenuate conductive material layer 7.At N
2: O
2Oxidation in the mixed atmosphere of=0-900: 1-500, its oxidizing temperature are 350-1200 ℃.Use corrosive liquid HF: H
2O=1-100: 1-5000 or HCl: H
2O=1-100: 1-5000 removes oxide layer.Reoxidize, corrosion again reaches the 2-300 nanometer up to the thickness of conductive material layer 7.If contained the self assembly quantum dot in the selected conductive material layer 7, then the distance of the upper surface of the conductive material layer 7 of quantum dot behind attenuate is the 2-200 nanometer; Electron gas in the conductive material layer (7) is caused by the former doping or the applying bias mode of injection, electric conducting material.
(2) on the conductive material layer behind the attenuate 7, utilize preparation overlay marks such as conventional photoetching process, X-ray lithography method, electron beam lithography method, ion beam lithography method or phase shift mask lithography method, part table top, the groove of corrosion or the film (comprising metal film) of deposition etc. that can utilize corrosion to form are used as overlay mark; Its metal film is metal level and any composite beds between them such as W, Cr, Pt, Ta or Mo.
(3) utilize the overlay mark location, adopt conventional photoetching process to prepare mask, corrosion has the conductive material layer 7 of overlay mark, wherein, erode the part in conductive material layer 7 mask patterns, the outer conductive material layer 7 of mask pattern is the table top of making device, and described corrosion can be known dry etching or wet etching, and wherein: described wet etching liquid is H
2SO
4: H
2O
2: H
2O=1-100: 1-60: 1-500, NH
4OH: H
2O
2: H
2O=1-100: 1-60: 1-5000, H
3PO
4: H
2O
2: H
2O=1-100: 1-60: 1-500, H
2SO
4: H
3PO
4: H
2O=1-100: 1-60: 0-500, KOH: H
2O=1-100: 1-5000, NaOH: H
2O=1-100: 1-5000, HF: H
2O=1-100: 1-5000 or HCl: H
2The solution of O=1-100: 1-5000.
(4) utilize the overlay mark location, on the conductive material layer 7 that has overlay mark, prepare the mask that is used for the ion injection by photoetching process, its mask material comprises 1) photoresist such as PMMA, ZEP, AZ or SAL, 2) metal level and any composite beds between them such as Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta or Mo, or 3) insulating material such as silica, aluminium oxide, silicon nitride or titanium oxide.Inject ion to mask, wherein, the element of injection comprises silicon, phosphonium ion, nitrogen ion, arsenic ion, oxonium ion, nitrogen ion or boron fluoride ion etc.After ion injects, remove the mask that is used for the ion injection, the element that the high-temperature annealing activation ion injects, its annealing temperature is 500-1200 ℃.
(5) utilize the overlay mark location, on accurately machined conductive material layer 7, prepare in order to make the figure photoresist mask of source electrode 1 and drain electrode 2 by photoetching, depositing metallic films on band photoresist figure mask, or, then in step 10), implement deposition, the alloy annealing of metal film when having in the step 6) when being higher than 500 ℃ pyroprocess; Its thickness of metal film is the 50-900 nanometer.The metal film of deposition comprises Pd, Zr, Ag, Gd, Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta or Mo and any composite bed between them.Taking-up is made device and is put into solvent and soak.Remove metal film outside the mask pattern through technology such as peeling off, the metal film ECDC annealing of gold in the mask pattern that stays is source electrode 1 and drain electrode 2, and its annealing temperature is 300-800 ℃, time 5-3600 second.
(6) utilize the overlay mark location, adopt directly preparation figure mask on conductive material layer 7 of photoetching methods such as conventional photoetching process, X-ray lithography method, electron beam lithography method, ion beam lithography method or phase shift mask lithography method, its mask material comprises 1) photoresist such as PMMA, ZEP, AZ or SAL, 2) metal level and any composite beds between them such as Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta or Mo, or 3) insulating material such as silica, aluminium oxide, silicon nitride or titanium oxide.Utilize dry corrosion method or wet corrosion method corrosion conductive material layer 7, will not have the partial corrosion of mask to fall on the conductive material layer 7, preparation connects the narrow passage 3 in source electrode 1 district and 2 districts that drain on conductive material layer 7, and its width is the 2-800 nanometer, highly is the 1-150 nanometer.To the conductive material layer 7 that does not comprise the self assembly quantum dot, adopt processes such as excessive erosion, lateral encroaching or dry-oxygen oxidation in narrow passage 3, to form quantum dot again, further reduce the width of narrow passage and form quantum dot at narrow passage by dry-oxygen oxidation method, quantum dot is the 2-200 nanometer from the distance of the upper surface of conductive material layer 7.But adopt dry-oxygen oxidation method can obtain the oxide layer and the High Accuracy Control oxidation rate of compact substance, improve the repeatability of technology and the stability of device work.The gas that feeds during dry-oxygen oxidation is O
2: N
2=1-4: 0-20, the temperature of oxidation is 500-980 ℃.
(7) utilize the overlay mark location, adopt conventional photoetching process, X-ray lithography method, electron beam lithography method, ion beam lithography method, phase shift mask lithography method, preparation is in order to make the photoresist figure mask of point-contact planar grid 4 on the conductive material layer 7 of the narrow passage 3 that has prepared, and depositing metallic films thereon, or with being in harmony directly depositing metallic films on the photoresist figure mask of preparation narrow passage 3 of sedimentation certainly, its thickness of metal film is the 10-150 nanometer.The metal film of deposition comprises metal level and any composite beds between them such as Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta or Mo.Taking-up is made device and is put into solvent and soak.Remove metal film outside the mask pattern through technology such as peeling off, the metal film on narrow passage 3 both sides in the mask pattern is point-contact planar grid 4.
(8) covering insulating material layer 6 on conductive material layer 7.With method deposition of insulative material such as vapour deposition, electron beam evaporation or sputters, comprise silica, aluminium oxide, silicon nitride or titanium oxide etc., its thickness is 10 nanometers～800 nanometers.Underlayer temperature during deposition is 10-400 ℃.
(9) utilize the overlay mark location, the surperficial grid 5 of preparation on insulation material layer 6.At first adopt conventional photoetching process on insulation material layer 6, to prepare, then depositing metallic films on mask in order to make the mask of surperficial grid 5.Its metal film comprises Al, Au, W, Cr, Ti, Ni, Pt, Ge, Ta or Mo etc. and any composite bed between them thereof, and thickness is the 10-800 nanometer.Its mask material is a photoresist.Remove metal film outside the mask pattern through technology such as peeling off, the metal film in the mask pattern that stays is metal surface grid 5.The also available polysilicon film of surperficial grid 5 on the insulation material layer 6 is made surperficial grid, and technology of preparing is known polysilicon gate technology of preparing.
(10) if also do not implement deposition, the alloy annealing process of metal film in source electrode 1 in the step (5) and drain electrode 2 preparations, then use conventional photoetching process, electrode through prepared source such as perforation, deposition, alloy annealing and drain region.Plated metal comprises metal level and their composite beds such as Pd, Zr, Ag, Gd, Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta, In or Mo, and its thickness is the 100-8000 nanometer.Peel off, clean, at N
2: H
2Annealed alloy in the mixed atmosphere of=1-900: 0-500, temperature are 300-800 ℃.
(11) just prepared single-electronic transistor of the present invention through perforation, lead-in wire.
Solvent for use is an acetone.
Quantum dot in the narrow passage is caused by following mechanism: the 1) fluctuation of Si single crystal film thickness, 2) fluctuation of narrow passage width, 3) oxidation rate depends on the dry-oxygen oxidation process of graphic structure, 4) strain that causes of corrosion and oxidation, 5) existence of local attitude, 6) nano particle at the interface.Thereby, form quantum dot naturally in the very easy narrow passage between leak in the source of the transistorized preparation technology of above-described the present invention.Utilize 4 extruding of point-contact planar grid to exhaust narrow passage, realize the single-electronic transistor of single quantum dot 13.As shown in Figure 2, the point-contact planar grid exhaust the quantum dot (quantum dot 9, quantum dot 10, quantum dot 11 and quantum dot 12) of channel edge, and the electron number in these quantum dots does not change with the variation of extra electric field, and single-electronic transistor is not had influence.Thereby realized the single-electronic transistor of single quantum dot (promptly being quantum dot 13 oxide-semiconductor control transistors characteristics).Because this quantum dot and not exclusively by the photo etched mask dimension definitions, its size can be much smaller than the limit that photoetching limited, thereby these single-electronic transistors can at room temperature be worked.
Single-electronic transistor of the present invention is to adopt point-contact planar grid extruding narrow passage, and utilizes the principle of single quantum point control narrow passage transport property to prepare, thereby the big I of quantum dot reaches atomic scale, and its single-electronic transistor can at room temperature be worked.It can satisfy two primary conditions of single-electronic transistor regular event: the resistance between (1) source, drain electrode is greater than the quantum resistance R
qThe enough little e that makes of electric capacity of=h/e2 ≈ 26k Ω (2) quantum dot
2/ 2C＞＞k
BT.
The quantum dot of single-electronic transistor of the present invention is by self-assembling method, form naturally from just thermal oxidation (thermal oxidation that figure relies on) or by the fluctuation of unordered gesture, thereby is easy to form the quantum dot of nanoscale, that is to say its working temperature height.Guarantee the transistorized electrical characteristics of single quantum point control in the narrow passage by the extruding of the back bias voltage on point-contact planar grid narrow passage, overcome the shortcoming of the complicated difficult control of conventional high-temperature single-electronic transistor.Thereby single-electronic transistor of the present invention is a kind of desirable, stable high-temperature single electron transistor.The more important thing is that it can adopt conventional photolithographic nanofabrication technique to prepare.In addition, it is also wide to the range of choice of making device material, has universality, and can be used to prepare biomolecular device.
The more traditional single-electronic transistor of single-electronic transistor of the present invention has following advantage: 1) preparation is simple, and 2) stable performance, 3) the working temperature height.
The present invention is described in detail below in conjunction with drawings and Examples:
The structural representation of Fig. 1 single-electronic transistor of the present invention.
Narrow passage in Fig. 2 single-electronic transistor of the present invention and the many quantum dots in the passage thereof.
The conventional photoetching process of Fig. 3 prepares the principle technical process of narrow passage and quantum dot.
Fig. 4 represents the narrow passage single-electronic transistor that 70 nanometers are wide, the coulomb oscillations characteristic outside not having on the point-contact planar grid under the bias voltage.
Fig. 5 represents the narrow passage single-electronic transistor that 70 nanometers are wide, is adding on the point-contact planar grid-coulomb oscillations characteristic under the 116mV bias voltage.
Fig. 6 represents the narrow passage single-electronic transistor that 30 nanometers are wide, is adding on the point-contact planar grid-coulomb oscillations characteristic under the 60mV bias voltage.
The single quantum dot characteristics of Fig. 7 single-electronic transistor of the present invention.
Indicate among the figure:
1. source electrode 2. drain electrode 3. narrow passages 4. point-contact planar grid 5. surperficial grid
6. insulating barrier 7. conductive material layers 8. substrates 9,10,11,12. quantum dots
13. the single quantum dot 14. figure photoresist masks of control single-electronic transistor ideal characterisitics
Embodiment 1:
Select the P type SOI substrate of (001) orientation for use, the oxygen buried layer among the SOI is the substrate 8 of preparation single-electronic transistor of the present invention, and the Si single crystal film on the SOI is conductive material layer 7.After known SOI substrate cleaning method cleaning,, make its thickness reach 70 nanometers by oxidation repeatedly, corroding method attenuate conduction Si single crystal film 7.Described oxidation is dry-oxygen oxidation (dry oxidation), at N
2: O
2Oxidation in=1: 1 the mixed atmosphere, its oxidizing temperature are 850 ℃.In volume ratio, use corrosive liquid HF: H
2O=1: 10 remove oxide layer.
Utilize the electron beam lithography method on the Si single crystal film 7 behind the attenuate, the photoresist PMMA mask of preparation band "+" word figure, with the low-priced method depositing metallic films of penetrating, its metal film is 50 nanometer Cr/300 nanometer W on band photoresist figure PMMA mask.Taking-up is made device and is put into solvent and soak.Remove Cr/W outside the mask pattern through technology such as peeling off, the Cr/W in the mask pattern that stays is the overlay mark of "+" word figure.The width of forming two lines of "+" word figure all is 1 micron, and length all is 2000 microns.
Having deposition 20 nanometer SiO on the Si single crystal film 7 of overlay mark
2With 120 nanometer Si
3N
4Film.Utilize known reactive ion etching method to remove the Si of 120 outer nanometer thickness of active area
3N
4Film is used HF: H
2O=1: 10 corrosive liquids remove the 20 nanometer thickness SiO that expose
2Film, the Si single crystal film 7 that utilizes known wet-oxygen oxidation (wet oxidation) method oxidation to expose is realized the isolation of device and the table top of making device.
Having deposition 20 nanometer SiO on the Si single crystal film 7 of overlay mark
2With 120 nanometer Si
3N
4Film.Utilize the overlay mark location, by the 20 nanometer SiOs of photoetching process in deposition
2With 120 nanometer Si
3N
4Preparation is used for the mask that arsenic ion injects on the film, injects the 100keV arsenic ion to mask, and dosage is 8 * 10
15Cm
-2Arsenic ion is used undiluted H after injecting
3PO
4Boil the Si that removed 120 nanometer thickness in 38 minutes at 80 ℃
3N
4Film is used HF: H
2O=1: 10 corrosive liquids remove 20 nanometer thickness SiO
2Film.At N
2: H
2Anneal in=2: 1 the mixed atmosphere, its temperature is 1080 ℃, and the annealing temperature time is 7 seconds.
Utilize the overlay mark location, adopt the electron beam lithography method directly the figure mask for preparing on the Si single crystal film 7 of overlay mark in order to making narrow passage 3 being arranged, its mask material is the PMMA film of 120 nanometers.The etching method of utilizing the electron cyclotron resonace dry method is at SF
6Atmosphere and 120 ℃ of etchings have the Si single crystal film 7 of figure mask, to there be the partial etching of mask to fall on the Si single crystal film 7, realize connecting the narrow passage 3 of source electrode 1 and drain electrode 2 on Si single crystal film 7, its etching depth is 70 nanometers, and the width of formed narrow passage 3 is 80 nanometers.Further reduce the width of narrow passage and form quantum dot with dry-oxygen oxidation method at narrow passage.The gas that feeds during dry-oxygen oxidation is O
2: N
2=1: 3, the temperature of oxidation is 780 ℃, and oxidization time is 3 minutes.
Utilize the autoregistration metaliding to prepare point-contact planar grid 4.Utilize electron beam evaporation equipment and adopt the multi-angle evaporation to deposit 15 nanometer Cr/30 nanometer W, soaked 200 minutes in acetone, its soaking temperature is 60 ℃.Take out from acetone and put as in the water 10 minutes, dry up with nitrogen, the flow of nitrogen and pressure are respectively 100mL/min and 1 * 10
5Pa.
Utilize electron beam evaporation equipment evaporation, deposition SiO
2 Insulation material layer 6, its thickness are 80 nanometers.
Adopt known alignment means and HF buffered etch liquid to carve opening contact hole.Utilize electron beam evaporation equipment to evaporate the Al of 1 μ m, at N
2: H
2Annealed alloy in=3: 1 the mixed atmosphere, temperature are 450 ℃.
Adopt the Al surface grid preparation method of known MOS device to prepare the transistorized surperficial grid 5 of the present invention.Lead-in wire connects, and just prepares Si single-electronic transistor of the present invention.Shown in Fig. 1-2.Positive bias by surperficial grid causes the inversion layer two-dimensional electron gas, and to regulate its concentration be electron number in the quantum dot, and the point-contact planar grid make the characteristic that single quantum dot in the narrow passage can oxide-semiconductor control transistors.
Embodiment 2:
Select the P type SOI substrate of (001) orientation for use, the oxygen buried layer among the SOI is the substrate 8 of preparation single-electronic transistor of the present invention, and the Si single crystal film on the SOI is conductive material layer 7.After known SOI substrate cleaning method cleaning, lead Si single crystal film 7 by oxidation repeatedly, corroding method attenuate, make its thickness reach 120 nanometers.Described oxidation is a dry-oxygen oxidation, at N
2: O
2Oxidation in=2: 1 the mixed atmosphere, its oxidizing temperature are 890 ℃.In volume ratio, use corrosive liquid HF: H
2O=1: 20 remove oxide layer.
Utilize conventional photoetching process on the Si single crystal film 7 behind the attenuate, the square photoresist AZ1400 mask of preparation belt length, with the low-priced method depositing metallic films of penetrating, its metal film is 50 nanometer Cr/300 nanometer W on band photoresist figure AZ1400 mask.Taking-up is made device and is put into solvent and soak.Remove Cr/W outside the mask pattern through technology such as peeling off, the Cr/W in the mask pattern that stays is rectangular overlay mark.Its rectangular length be 100 microns, wide be 20 microns.
Having deposition 25 nanometer SiO on the Si single crystal film 7 of overlay mark
2Film and 130 nanometer Si
3N
4Film.Utilize known reactive ion etching method to remove the Si of 130 outer nanometer thickness of active area
3N
4Film is used HF: H
2O=1: 20 corrosive liquids remove the SiO of 25 nanometer thickness of exposing
2Film, the Si single crystal film 7 that utilizes known wet-oxygen oxidation method oxidation to expose is realized the isolation of device and the table top of making device.
Having deposition 26 nanometer SiO on the Si single crystal film 7 of overlay mark
2Film and 136 nanometer Si
3N
4Film.Utilize the overlay mark location, by the 26 nanometer SiOs of photoetching process in deposition
2Film and 136 nanometer Si
3N
4Preparation is used for the mask that arsenic ion injects on the film, injects the 100keV arsenic ion to mask, and dosage is 8 * 10
15Cm
-2Arsenic ion is used undiluted H after injecting
3PO
4Boil the Si that removed 136 nanometer thickness in 40 minutes at 80 ℃
3N
4Film is used HF: H
2O=1: 10 corrosive liquids remove 26 nanometer thickness SiO
2Film.At N
2: H
2Anneal in=5: 1 the mixed atmosphere, its temperature is 1080 ℃, and the annealing temperature time is 9 seconds.
Utilize the overlay mark location, adopt phase shift mask lithography method that the figure mask for preparing on the Si single crystal film 7 of overlay mark in order to making narrow passage 3 is being arranged, its mask material is AZ1400.The etching method of utilizing the electron cyclotron resonace method is at SF
6Atmosphere and 120 ℃ of etchings have the Si single crystal film 7 of figure mask, to there be the partial etching of mask to fall on the Si single crystal film 7, realize connecting the narrow passage 3 of source electrode 1 and drain electrode 2 on Si single crystal film 7, its etching depth is 120 nanometers, and the width of formed narrow passage 3 is 320 nanometers.Further reduce the width of narrow passage and form quantum dot with dry-oxygen oxidation method at narrow passage.The gas that feeds during dry-oxygen oxidation is O
2: N
2=1: 3, the temperature of oxidation is 780 ℃, and oxidization time is 12 minutes.
Utilize the autoregistration metaliding to prepare point-contact planar grid 4.Utilize electron beam evaporation equipment and deposit 20 nanometer Cr/100 nanometer W with the multi-angle evaporation mode, soaked 200 minutes in acetone, its soaking temperature is 60 ℃.Take out from acetone and put as in the water 10 minutes, dry up with nitrogen, the flow of nitrogen and pressure are respectively 160mL/min and 2 * 10
5Pa.
Utilize electron beam evaporation equipment evaporation, deposition SiO
2 Insulation material layer 6, its thickness are 100 nanometers.
Locate with overlay mark, on the Si single crystal film 7 after the annealing, prepare in order to make the AZ1400 figure mask of surperficial grid 5 by photoetching process and the known technology that hollows out, utilize electron-beam vapor deposition method on its mask, to deposit the thick Al film of 1 μ m, remove Al film outside the mask pattern through technology such as peeling off, the Al film in the mask pattern that stays is surperficial grid 5
Lead-in wire connects, and just prepares Si single-electronic transistor of the present invention.
Embodiment 3:
The also available following method of narrow passage 3 among embodiment 1 and the embodiment 2 realizes:
With conventional photoetching process and SiO
2Deposition process preparation in order to make the SiO of narrow passage 3
2Mask is as among Fig. 3 14.The SiO of definition
2The narrow passage of mask is along [110] crystal trend of Si single crystal film 7, and its thickness is 90 nanometers.
Adopt KOH: H2O=1: 3 corrosive liquid is to having the SiO that makes narrow passage 3 figures
2Mask carries out incorgruous selective etching.In this corrosive liquid, { the 111} crystal face is the corrosion stop surface.When the both sides of narrow passage { when the 111} crystal face intersected, corrosion stopped automatically.
Because the thickness of the Si single crystal film 7 on the oxygen buried layer 8 can accurately be controlled, the geometric widths of narrow passage can be repeated fully, be controlled.The physical dimension of narrow passage not influenced by the mask pattern size and the controllable thickness of Si single crystal film built in dust (A °) magnitude, thereby the single-electronic transistor of the present invention of the method preparation can be operated in room temperature.
Embodiment 4:
Original Si single crystal film 7 among the embodiment 3 is thinned to 20 nanometers, presses the preparation method of the narrow passage 3 among the embodiment 3, utilize known back of the body grid preparation method, preparation back of the body grid on substrate 8.These back of the body grid substitute the effect of surperficial grid 5.The dry-oxygen oxidation method of saving among the embodiment 3 of utilizing further reduces the step of narrow passage width, also saves the insulating barrier 6 among the embodiment 3 and the preparation process of surperficial grid 5.
Thereby realized single-electronic transistor of the present invention.This is actually a kind of distortion of single-electronic transistor of the present invention.
Embodiment 5:
The also available following method of narrow passage 3 among embodiment 1 and the embodiment 2 realizes:
Utilize overlay mark location, adopt go up the preparation method of " nano-electrode to " of report the 1st phase of calendar year 2001 " physics ", realize the point-contact planar grid 4 and the narrow passage 3 of single-electronic transistor of the present invention.Utilize this " nano-electrode to " and adopt the step of preparation process of describing in embodiment 1,2 and 3, can prepare very desirable high-temperature single electron transistor.
Feature, behavior below in conjunction with the actual measured results explanation single-electronic transistor of the present invention of the single-electronic transistor of present embodiment preparation.
Fig. 4 has represented the coulomb oscillations characteristic of 70 nanometer width passage single-electronic transistors.With bias voltage (V on the surperficial grid 5
5) reduce the electric current (I of drain electrode on 2
2) reduce and shown acyclic vibration.What must emphasize is that it reduces and increase on D1, D2, D3 and great-jump-forward ground, D4 place.This behavior has just reflected the behavior of many quantum dots in the narrow passage.Increase the back bias voltage (V on the point-contact planar grid 4 gradually
4), the effective width of extruding narrow passage also exhausts the quantum dot region of channel edge gradually.Work as V
4During＜-114mV, it is the electrical characteristics of having only quantum dot 3 oxide-semiconductor control transistors in the narrow passage that the electron number in all the other quantum dots does not change with the variation in outfield.At this moment transistor shows rational cycle coulomb oscillations, as shown in Figure 5.The observed cycle is 0.64V, that is to say, the electric capacity between surperficial grid 5 and the quantum dot 13 is 0.25aF.The test shows of a plurality of devices: defined narrow passage width is more little, and the coulomb oscillations in this cycle is easy more to be observed.Fig. 6 has represented that 30 nanometer width passage single-electronic transistors are at V
4Coulomb oscillations characteristic during＜-60mV.This coulomb oscillations curve more becomes idealized, and its cycle is 0.55V.With the raising of experimental temperature, coulomb oscillations dies down, but the cycle is constant, as shown in Figure 7.As can be seen from Figure, this transistor can be operated in more than the 90K.
Embodiment 6:
Select the P type SOI substrate of (001) orientation for use, the oxygen buried layer among the SOI is the substrate 8 of preparation single-electronic transistor of the present invention, and the Si single crystal film on the SOI is conductive material layer 7.After known SOI substrate cleaning method cleaning,, make its thickness reach 120 nanometers by oxidation repeatedly, corroding method attenuate conduction Si single crystal film 7.Described oxidation is a dry-oxygen oxidation, at N
2: O
2Oxidation in=2: 1 the mixed atmosphere, its oxidizing temperature are 880 ℃.In volume ratio, use corrosive liquid HF: H
2O=1: 20 remove oxide layer.
Utilize the electron beam lithography method on the Si single crystal film 7 behind the attenuate, the photoresist PMMA mask of preparation band "+" word figure, with the low-priced method depositing metallic films of penetrating, its metal film is 30 nanometer Cr/200 nanometer W on band photoresist figure PMMA mask.Taking-up is made device and is put into solvent and soak.Remove Cr/W outside the mask pattern through technology such as peeling off, the Cr/W in the mask pattern that stays is the overlay mark of "+" word figure.The width of forming two lines of "+" word figure all is 2 microns, and length all is 2000 microns.
Having deposition 30 nanometer SiO on the Si single crystal film 7 of overlay mark
2With 120 nanometer Si
3N
4Film.Utilize known reactive ion etching method to remove the Si of 120 outer nanometer thickness of active area
3N
4Film is used HF: H
2O=1: 20 corrosive liquids remove the 30 nanometer thickness SiO that expose
2Film, the Si single crystal film 7 that utilizes known wet-oxygen oxidation method oxidation to expose is realized the isolation of device and the table top of making device.
Having deposition 30 nanometer SiO on the Si single crystal film 7 of overlay mark
2With 120 nanometer Si
3N
4Film.Utilize the overlay mark location, by the 30 nanometer SiOs of photoetching process in deposition
2With 120 nanometer Si
3N
4Preparation is used for the mask that arsenic ion injects on the film, injects the 100keV arsenic ion to mask, and dosage is 6 * 10
15Cm
-2Arsenic ion is used undiluted H after injecting
3PO
4Boil the Si that removed 120 nanometer thickness in 42 minutes at 80 ℃
3N
4Film is used HF: H
2O=1: 20 corrosive liquids remove 30 nanometer thickness SiO
2Film.At N
2: H
2Anneal in=3: 1 the mixed atmosphere, its temperature is 1060 ℃, and the annealing temperature time is 8 seconds.On conductive material layer 7, prepare in order to make the figure AZ1400 photoresist mask of source electrode 1 and drain electrode 2, the Al film of deposition 1 micron thickness on band photoresist figure mask with conventional photoetching process again.Taking-up is made device and is put into solvent and soak.Remove metal film outside the mask pattern through technology such as peeling off, the metal film ECDC annealing of gold in the mask pattern that stays is source electrode 1 and drain electrode 2, and its annealing temperature is 450 ℃.
Utilize the overlay mark location, adopt the electron beam lithography method directly the figure mask for preparing on the Si single crystal film 7 of overlay mark in order to making narrow passage 3 being arranged, its mask material is the PMMA film of 160 nanometers.Utilize the etching method of electron cyclotron resonace dry method, at SF
6Atmosphere and 120 ℃ of etchings have the Si single crystal film 7 of figure mask, to there be the partial etching of mask to fall on the Si single crystal film 7, realize connecting the narrow passage 3 in source electrode 1 district and 2 districts that drain on Si single crystal film 7, its etching depth is 120 nanometers, and the width of formed narrow passage 3 is 12 nanometers.The fluctuation of the width of narrow passage 3 causes forming in the narrow passage quantum dot.
Utilize the autoregistration metaliding to prepare point-contact planar grid 4.Utilize electron beam evaporation equipment and adopt the multi-angle evaporation to deposit 15 nanometer Cr/30 nanometer W, soaked 200 minutes in acetone, its soaking temperature is 60 ℃.Take out from acetone and put as in the water 10 minutes, dry up with nitrogen, the flow of nitrogen and pressure are respectively 100mL/min and 1 * 10
5Pa.
Utilize electron beam evaporation equipment evaporation, deposition SiO
2 Insulation material layer 6, its thickness are 120 nanometers.
Adopt the Al surface grid preparation method of known MOS device to prepare the transistorized surperficial grid 5 of the present invention.Lead-in wire connects, and just prepares Si single-electronic transistor of the present invention.Shown in Fig. 1-2.Positive bias by surperficial grid causes the inversion layer two-dimensional electron gas, and to regulate its concentration be electron number in the quantum dot, and the point-contact planar grid make the characteristic that single quantum dot in the narrow passage can oxide-semiconductor control transistors.
Claims (30)
1. the preparation method of a point-contact planar grid type single-electronic transistor, it is characterized in that: preparation process comprises:
1) selects the material that on substrate (8), has been coated with conductive material layer (7) for use, by oxidation repeatedly, corroding method attenuate conductive material layer (7); Thickness up to conductive material layer (7) reaches the 2-300 nanometer;
2) conductive material layer behind attenuate (7) is gone up the preparation overlay mark, and the film of the part table top that the utilization corrosion forms, the groove of corrosion or deposition is as overlay mark;
3) utilize the overlay mark location, the preparation mask, corrosion has the conductive material layer (7) of overlay mark, wherein, erode the part in conductive material layer (7) mask pattern, the outer conductive material layer (7) of mask pattern is the table top of making device, and described corrosion is dry etching or wet etching;
4) utilize overlay mark location, go up preparation and be used for the mask that ion injects having the conductive material layer of overlay mark (7), inject ion to mask, after ion injects, remove the mask that is used for the ion injection, the element that the high-temperature annealing activation ion injects, its annealing temperature is 500-1200 ℃;
5) utilize the overlay mark location, go up preparation in order to make the figure photoresist mask of source electrode (1) and drain electrode (2) at accurately machined conductive material layer (7) by photoetching; Depositing metallic films on band photoresist figure mask, alloy annealing; Its thickness of metal film is the 50-900 nanometer; Taking-up is made device and is put into solvent and soak, and removes the outer metal film of mask pattern, and the metal film ECDC annealing of gold in the mask pattern that stays is source electrode (1) and drain electrode (2), and its annealing temperature is 300-800 ℃;
6) utilize the overlay mark location, directly go up preparation figure mask at conductive material layer (7), utilize dry corrosion method or wet corrosion method corrosion conductive material layer (7), to there be the partial corrosion of mask to fall on the conductive material layer (7), go up the narrow passage (3) that preparation connects source electrode (1) district and drain electrode (2) district at conductive material layer (7), to the conductive material layer (7) that does not comprise the self assembly quantum dot, adopt excessive erosion or lateral encroaching process in narrow passage (3), to form quantum dot again;
7) utilize the overlay mark location, go up preparation in order to make the photoresist figure mask of point-contact planar grid (4) at the conductive material layer (7) of the narrow passage that has prepared (3), and depositing metallic films thereon, or with being in harmony directly depositing metallic films on the photoresist figure mask of preparation narrow passage (3) of sedimentation certainly, taking-up is made device and is put into solvent and soak, remove the outer metal film of mask pattern, the metal film on the narrow passage in the mask pattern (3) both sides is point-contact planar grid (4);
8) go up covering insulating material layer (6) at conductive material layer (7); Its thickness is 10 nanometers～800 nanometers, and the underlayer temperature during deposition is 10-400 ℃;
9) utilize the overlay mark location, go up preparation surperficial grid (5) at insulation material layer (6); At first go up preparation in order to make the mask of surperficial grid (5), then depositing metallic films on mask at insulation material layer (6); Remove the outer metal film of mask pattern, the metal film in the mask pattern that stays is metal surface grid (5); Or utilize surperficial grid (5) on the polysilicon gate fabrication techniques insulation material layer (6);
10) just prepared point-contact planar grid type single-electronic transistor through perforation, lead-in wire.
2. the preparation method of single-electronic transistor as claimed in claim 1, it is characterized in that: the oxidizing gas of described step 1) (with volume ratio) is N
2: O
2The gaseous mixture of=0-900: 1-500; Oxidizing temperature is 350-1200 ℃; The corrosive liquid (with volume ratio) of corrosion usefulness is HF: H
2O=1-100: 1-5000 or HCl: H
2The solution of O=1-100: 1-5000.
3. the preparation method of single-electronic transistor as claimed in claim 1, it is characterized in that: the width of described narrow passage (3) is 3 nanometers-800 nanometers.
4. the preparation method of single-electronic transistor as claimed in claim 1, it is characterized in that: the thickness of described insulation material layer (6) is 10 nanometers～800 nanometers.
5. the preparation method of single-electronic transistor as claimed in claim 1, it is characterized in that: described substrate is 1) silicon on the semiconducting insulation body; 2) oxide material; 3) glass, SiC, Ge, silicon or the monocrystalline silicon of one deck oxide is arranged on silicon face; Or 4) semi-conducting material of semi-conducting material of Can Zaing or non-doping.
6. the preparation method of single-electronic transistor as claimed in claim 5, it is characterized in that: described oxide material is Al
2O
3, silica, magnesium oxide or strontium titanates.
7. the preparation method of single-electronic transistor as claimed in claim 5, it is characterized in that: the semi-conducting material of described non-doping is GaAs, Cr-GaAs, Si or InP; The semi-conducting material that mixes is N
+-GaAs, N
+-InP or N
+-GaN.
8. the preparation method of single-electronic transistor as claimed in claim 1, it is characterized in that: described electric conducting material comprises 1) Si, Ge or SiGe semiconductor element cellulosic material, 2) GaN, NAlGaAs, NInGaAs, NInAlGaAs, GaAs, AlGaAs, InGaAs or InAlGaAs semiconducting compound, or 3) by silicon, magnesium, phosphonium ion, nitrogen ion, arsenic ion, oxonium ion or the boron fluoride ion doping composite material in Si, Ge, SiGe, GaN, NAlGaAs, NInGaAs, NInAlGaAs, GaAs, AlGaAs, InGaAs or the InAlGaAs semi-conducting material.
9. the preparation method of single-electronic transistor as claimed in claim 1, it is characterized in that: described insulating material comprises silica, aluminium oxide, silicon nitride or titanium oxide.
10. the preparation method of single-electronic transistor as claimed in claim 1, it is characterized in that: described mask material comprises 1) PMMA, ZEP, AZ or SAL photoresist, 2) Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta or Mo metal level and any composite bed between them, or 3) silica, aluminium oxide, silicon nitride or titanium oxide insulating material.
11. the preparation method of single-electronic transistor as claimed in claim 1 is characterized in that: described surperficial grid are deposited metal films, or the N through depositing, injecting and anneal
+The doped polycrystalline silicon fiml.
12. the preparation method of single-electronic transistor as claimed in claim 1 is characterized in that: described metal film is Pd, Zr, Ag, Gd, Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta, In or Mo metal level and the composite bed arbitrarily between them.
13. the preparation method of single-electronic transistor as claimed in claim 1 is characterized in that: the corrosive liquid that described wet etching is used is (by volume) H
2SO
4: H
2O
2: H
2O=1-100: 1-60: 1-500, NH
4OH: H
2O
2: H
2O=1-100: 1-60: 1-5000, H
3PO
4: H
2O
2: H
2O=1-100: 1-60: 1-500, H
2SO
4: H
3PO
4: H
2O=1-100: 1-60: 0-500, KOH: H
2O=1-100: 1-5000, NaOH: H
2O=1-100: 1-5000, HF: H
2O=1-100: 1-5000 or HCl: H
2The solution of O=1-100: 1-5000.
14. the preparation method of single-electronic transistor as claimed in claim 1 is characterized in that: the element of described injection comprises silicon, phosphonium ion, nitrogen ion, arsenic ion, oxonium ion, nitrogen ion or boron fluoride ion.
15. the preparation method of a point-contact planar grid type single-electronic transistor, it is characterized in that: preparation process comprises:
1) selects the material that on substrate (8), has been coated with conductive material layer (7) for use, by oxidation repeatedly, corroding method attenuate conductive material layer (7); Thickness up to conductive material layer (7) reaches the 2-300 nanometer;
2) conductive material layer behind attenuate (7) is gone up the preparation overlay mark, and the film of the part table top that the utilization corrosion forms, the groove of corrosion or deposition is as overlay mark;
3) utilize the overlay mark location, the preparation mask, corrosion has the conductive material layer (7) of overlay mark, wherein, erode the part in conductive material layer (7) mask pattern, the outer conductive material layer (7) of mask pattern is the table top of making device, and described corrosion is dry etching or wet etching;
4) utilize overlay mark location, go up preparation and be used for the mask that ion injects having the conductive material layer of overlay mark (7), inject ion to mask, after ion injects, remove the mask that is used for the ion injection, the element that the high-temperature annealing activation ion injects, its annealing temperature is 500-1200 ℃;
5) utilize the overlay mark location, directly go up preparation figure mask at conductive material layer (7), utilize dry corrosion method or wet corrosion method corrosion conductive material layer (7), to there be the partial corrosion of mask to fall on the conductive material layer (7), go up the narrow passage (3) that preparation connects source electrode (1) district and drain electrode (2) district at conductive material layer (7), to the conductive material layer (7) that does not comprise the self assembly quantum dot, adopt the dry-oxygen oxidation process in narrow passage (3), to form quantum dot again;
6) utilize the overlay mark location, go up preparation in order to make the photoresist figure mask of point-contact planar grid (4) at the conductive material layer (7) of the narrow passage that has prepared (3), and depositing metallic films thereon, or with being in harmony directly depositing metallic films on the photoresist figure mask of preparation narrow passage (3) of sedimentation certainly, taking-up is made device and is put into solvent and soak, remove the outer metal film of mask pattern, the metal film on the narrow passage in the mask pattern (3) both sides is point-contact planar grid (4);
7) go up covering insulating material layer (6) at conductive material layer (7); Its thickness is 10 nanometers～800 nanometers, and the underlayer temperature during deposition is 10-400 ℃;
8) utilize the overlay mark location, go up preparation surperficial grid (5) at insulation material layer (6); At first go up preparation in order to make the mask of surperficial grid (5), then depositing metallic films on mask at insulation material layer (6); Remove the outer metal film of mask pattern, the metal film in the mask pattern that stays is metal surface grid (5); Or utilize surperficial grid (5) on the polysilicon gate fabrication techniques insulation material layer (6);
9) utilize the overlay mark location, go up preparation in order to make the figure photoresist mask of source electrode (1) and drain electrode (2) at accurately machined conductive material layer (7) by photoetching; Depositing metallic films on band photoresist figure mask, its thickness of metal film is the 50-900 nanometer; The electrode in alloy annealing preparation source and drain region;
10) just prepared point-contact planar grid type single-electronic transistor through perforation, lead-in wire.
16. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: the oxidizing gas of described step 1) (with volume ratio) is N
2: O
2The gaseous mixture of=0-900: 1-500; Oxidizing temperature is 350-1200 ℃; The corrosive liquid (with volume ratio) of corrosion usefulness is HF: H
2O=1-100: 1-5000 or HCl: H
2The solution of O=1-100: 1-5000.
17. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: the width of described narrow passage (3) is 3 nanometers-800 nanometers.
18. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: the thickness of described insulation material layer (6) is 10 nanometers～800 nanometers.
19. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: described substrate is 1) silicon on the semiconducting insulation body; 2) oxide material; 3) glass, SiC, Ge, silicon or the monocrystalline silicon of one deck oxide is arranged on silicon face; Or 4) semi-conducting material of semi-conducting material of Can Zaing or non-doping.
20. the preparation method of single-electronic transistor as claimed in claim 19 is characterized in that: described oxide material is Al
2O
3, silica, magnesium oxide or strontium titanates.
21. the preparation method of single-electronic transistor as claimed in claim 19 is characterized in that: the semi-conducting material of described non-doping is GaAs, Cr-GaAs, Si or InP; The semi-conducting material that mixes is N
+-GaAs, N
+-InP or N
+-GaN.
22. the preparation method of single-electronic transistor as claimed in claim 15, it is characterized in that: described electric conducting material comprises 1) Si, Ge or SiGe semiconductor element cellulosic material, 2) GaN, NAlGaAs, NInGaAs, NInAlGaAs, GaAs, AlGaAs, InGaAs or InAlGaAs semiconducting compound, or 3) by silicon, magnesium, phosphonium ion, nitrogen ion, arsenic ion, oxonium ion or the boron fluoride ion doping composite material in Si, Ge, SiGe, GaN, NAlGaAs, NInGaAs, NInAlGaAs, GaAs, AlGaAs, InGaAs or the InAlGaAs semi-conducting material.
23. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: described insulating material comprises silica, aluminium oxide, silicon nitride or titanium oxide.
24. the preparation method of single-electronic transistor as claimed in claim 15, it is characterized in that: described mask material comprises 1) PMMA, ZEP, AZ or SAL photoresist, 2) Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta or Mo metal level and any composite bed between them, or 3) silica, aluminium oxide, silicon nitride or titanium oxide insulating material.
25. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: described surperficial grid are deposited metal films, or the N through depositing, injecting and anneal
+The doped polycrystalline silicon fiml.
26. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: described metal film is Pd, Zr, Ag, Gd, Al, Ge, Ni, Au, W, Cr, Ti, Ni, Pt, Ta, In or Mo metal level and the composite bed arbitrarily between them.
27. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: the corrosive liquid that described wet etching is used is (by volume) H
2SO
4: H
2O
2: H
2O=1-100: 1-60: 1-500, NH
4OH: H
2O
2: H
2O=1-100: 1-60: 1-5000, H
3PO
4: H
2O
2: H
2O=1-100: 1-60: 1-500, HSO
4: H
3PO
4: H
2O=1-100: 1-60: 0-500, KOH: H
2O=1-100: 1-5000, NaOH: H
2O=1-100: 1-5000, HF: H
2O=1-100: 1-5000 or HCl: H
2The solution of O=1-100: 1-5000.
28. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: described step 9) annealing conditions is at N
2: H
2Alloy annealing in the mixed atmosphere of=1-900: 0-500, its annealing temperature is 300-800 ℃.
29. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: the element of described injection comprises silicon, phosphonium ion, nitrogen ion, arsenic ion, oxonium ion, nitrogen ion or boron fluoride ion.
30. the preparation method of single-electronic transistor as claimed in claim 15 is characterized in that: the gas that feeds during described dry-oxygen oxidation is O
2: N
2=1-4: 0-20, the temperature of oxidation is 500-980 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011008342A CN1160797C (en) | 2001-01-15 | 2001-01-15 | Point-contact planar grid type single-electron transistor and its preparing process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011008342A CN1160797C (en) | 2001-01-15 | 2001-01-15 | Point-contact planar grid type single-electron transistor and its preparing process |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1366345A CN1366345A (en) | 2002-08-28 |
| CN1160797C true CN1160797C (en) | 2004-08-04 |
Family
ID=4651927
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011008342A Expired - Fee Related CN1160797C (en) | 2001-01-15 | 2001-01-15 | Point-contact planar grid type single-electron transistor and its preparing process |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1160797C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100625999B1 (en) | 2004-02-26 | 2006-09-20 | 삼성에스디아이 주식회사 | Donor sheet, manufacturing method of the donor sheet, manufacturing method of TFT using the donor sheet, and manufacturing method of flat panel display using the donor sheet |
| CN108682668B (en) * | 2018-06-28 | 2024-06-14 | 厦门市三安集成电路有限公司 | High-temperature-resistant metal alignment mark and preparation method and application thereof |
| CN112563246B (en) * | 2020-12-18 | 2022-06-24 | 河源市众拓光电科技有限公司 | Photoetching overlay mark and preparation method thereof |
-
2001
- 2001-01-15 CN CNB011008342A patent/CN1160797C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1366345A (en) | 2002-08-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102576726B (en) | Tunnel field effect transistor and method for manufacturing same | |
| WO2019154385A1 (en) | High-density three-dimensional nanowire channel array and fabrication method thereof | |
| EP0881691B1 (en) | Quantum dot device | |
| CN108807553B (en) | Homogeneous PN junction based on two-dimensional semiconductor material and preparation method thereof | |
| JP3761319B2 (en) | Manufacturing method of semiconductor device | |
| WO2002018266A1 (en) | Single molecule array on silicon substrate for quantum computer | |
| CN114566544A (en) | High-mobility spin field effect transistor and preparation method thereof | |
| CN1160797C (en) | Point-contact planar grid type single-electron transistor and its preparing process | |
| US20150179583A1 (en) | Semiconductor devices comprising edge doped graphene and methods of making the same | |
| CN103928342B (en) | A kind of silicon nanowires tunneling field-effect transistor and preparation method thereof | |
| CN1160798C (en) | Point contact planar grid type single-electronic transistor and its preparing process | |
| JP4309869B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN105304501A (en) | Preparation method of semiconductor field effect transistor device with three-dimensional gate-all-around structure | |
| JP2002223016A (en) | Method for manufacturing quantum device | |
| KR100810983B1 (en) | Vertical Nanowire Growth Method at Selectve Locations, Semiconductor Nanodevice comprising Vertical Nanowire, and Fabrication Method thereof | |
| CN110491940B (en) | Nanowire transistor based on resonant tunneling and preparation method thereof | |
| CN2496135Y (en) | Point-contact plane grid type electronic transistor | |
| CN107919400B (en) | InSe transistor and preparation method thereof | |
| CN1170318C (en) | Coulometer with supersensitivity to charge and its preparing process | |
| CN111403290A (en) | Method for reducing channel length of field effect transistor by laser shock | |
| JPH0897398A (en) | Quatum effect device and its manufacture | |
| Rai et al. | Devices and defects in two-dimensional materials: outlook and perspectives | |
| KR100276436B1 (en) | Method for manufacturing single-temperature device | |
| CN1170319C (en) | Coulometer with self calibration function and supersensitivity to charge and its preparing process | |
| CN117316773B (en) | Preparation method of palladium/tungsten diselenide Schottky transistor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040804 Termination date: 20120115 |