KR100276565B1 - Method of forming a metal wiring in a semiconductor device - Google Patents
Method of forming a metal wiring in a semiconductor device Download PDFInfo
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- KR100276565B1 KR100276565B1 KR1019970081164A KR19970081164A KR100276565B1 KR 100276565 B1 KR100276565 B1 KR 100276565B1 KR 1019970081164 A KR1019970081164 A KR 1019970081164A KR 19970081164 A KR19970081164 A KR 19970081164A KR 100276565 B1 KR100276565 B1 KR 100276565B1
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- contact hole
- metal layer
- alignment key
- metal
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 50
- 239000002184 metal Substances 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000010410 layer Substances 0.000 claims abstract description 54
- 239000011229 interlayer Substances 0.000 claims abstract description 16
- 230000001678 irradiating effect Effects 0.000 claims abstract description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 8
- 238000005240 physical vapour deposition Methods 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000001816 cooling Methods 0.000 claims 1
- 239000007769 metal material Substances 0.000 abstract description 9
- 238000000151 deposition Methods 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 235000012054 meals Nutrition 0.000 abstract 1
- 239000011800 void material Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 단 파장의 레이저 빔(laser beam)을 선택적으로 조사하여 콘택홀 부분의 금속층만을 리플로우(reflow) 시키므로써, 콘택홀이 양호하게 매립되어 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE
일반적으로, 반도체 소자가 고집적화 되어감에 따라 콘택홀의 사이즈가 줄어들고 있다. 이에 따라 금속 콘택 공정시 콘택홀을 양호하게 채우기가 어려워 콘택 저항이 증가되는 요인으로 작용한다. 금속 배선은 텅스텐(W), 알루미늄(Al), 티타늄(Ti), 코발트(Co), 아연(Zn), 구리(Cu), 실리콘(Si), 백금(Pt), 금(Au) 등의 전도성 금속 물질을 사용하여 물리적 기상 증착(PVD) 또는 화학적 기상 증착(CVD) 방법에 의해 형성된다.In general, as semiconductor devices are highly integrated, the size of contact holes is reduced. Accordingly, it is difficult to fill the contact holes well in the metal contact process, which acts as a factor of increasing the contact resistance. Metal wires are conductive such as tungsten (W), aluminum (Al), titanium (Ti), cobalt (Co), zinc (Zn), copper (Cu), silicon (Si), platinum (Pt), and gold (Au). Metallic materials are used to form by physical vapor deposition (PVD) or chemical vapor deposition (CVD) methods.
도 1(a) 및 도 1(b)는 종래 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1 (a) and 1 (b) are cross-sectional views of a device for explaining a metal wiring formation method of a conventional semiconductor device.
도 1(a)를 참조하면, 하부층(1)상에 층간 절연막(2)이 형성된다. 하부층(1)은 반도체 기판이거나 반도체 소자의 구성 요소중 전극 또는 배선을 이루는 도전층이며, 이러한 하부층(1)의 선택된 부분을 일정 깊이 식각하여 얼라인먼트 키(alignment key; 4)가 형성된다. 층간 절연막(2)의 선택된 부분을 식각 하여 하부층(1)이 노출되는 콘택홀(3)이 형성되며, 이때 얼라인먼트 키(4) 부분도 노출된다. 콘택홀(3) 및 얼라인먼트 키(4)를 포함한 층간 절연막(2)상에 금속 물질을 증착 하여 금속층(5)이 형성된다.Referring to FIG. 1A, an
상기에서, 금속층(5)은 전도성 금속 물질을 사용하여 물리적 기상 증착(PVD) 또는 화학적 기상 증착(CVD) 방법에 의해 형성되는데, 금속 물질의 스텝 커버리지 불량으로 콘택홀(3)이 완전히 매립되지 않으며, 이로 인하여 콘택홀(3) 측면부 및 저면부에서 금속층(5)이 얇게 되고, 이러한 현상이 심할 경우 단락 현상이 발생된다.In the above, the
도 1(b)를 참조하면, 금속층(5)의 콘택 매립 특성 및 단락 현상 등을 줄이기 위해, 전면 열처리 공정을 실시하여 금속층(5)을 리플로우(reflow) 시킨다.Referring to FIG. 1B, in order to reduce contact embedding characteristics, short-circuit phenomenon, and the like of the
상기에서, 전면 열처리 리플로우 공정 동안 금속층(5)은 리플로우 되어 콘택홀(3)을 어느 정도 매립시킬 수 있으나, 콘택홀(3)을 완전히 매립시키기지 못해 콘택홀(3) 부분에 보이드(void; 6) 등을 남기게 되어 콘택 저항을 증가시키게 된다. 또한 전면 열처리 리플로우 공정 동안 얼라인먼트 키(4) 부분에도 금속층(5)이 리플로우 되므로 인하여, 금속 배선 형성을 위한 노광 공정시 금속층(5)의 리플로우된 부분(A)에서 얼라인먼트 에러(alignment error)가 발생하게 되어 스텝퍼(stepper) 노광의 정확한 설정을 어렵게 한다.In the above, the
따라서, 본 발명은 콘택홀을 양호하게 매립시켜 안정된 콘택 저항을 확보하므로, 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device which can improve contact reliability by filling contact holes with good contact resistance and improving the reliability of the device.
이러한 목적을 달성하기 위한 본 발명의 금속 배선 형성 방법은 얼라인먼트 키를 갖는 하부층상에 층간 절연막을 형성한 후, 상기 층간 절연막의 선택된 부분을 식각하여 상기 얼라인먼트 키 부분을 노출시키면서 상기 하부층의 선택된 부분이 노출되는 콘택홀을 형성하는 단계; 상기 얼라인먼트 키 및 상기 콘택홀을 포함한 상기 층간 절연막 상에 금속층을 형성하는 단계; 및 상기 얼라인먼트 키 부분을 제외한 적어도 콘택홀 부분이 포함된 금속층에 레이저 빔을 선택적으로 조사하여 상기 금속층의 선택된 부분을 리플로우 시켜 상기 콘택홀을 매립하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the metal wiring forming method of the present invention forms an interlayer insulating film on the lower layer having the alignment key, and then selects the selected portion of the lower layer while exposing the alignment key portion by etching the selected portion of the interlayer insulating film. Forming an exposed contact hole; Forming a metal layer on the interlayer insulating film including the alignment key and the contact hole; And selectively irradiating a laser beam to the metal layer including at least the contact hole portion except for the alignment key portion to reflow the selected portion of the metal layer to fill the contact hole.
도 1(a) 및 도 1(b)는 종래 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1 (a) and 1 (b) are cross-sectional views of a device for explaining a metal wiring formation method of a conventional semiconductor device.
도 2(a) 및 도 2(b)는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.2 (a) and 2 (b) are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for main parts of the drawings>
1 및 11: 하부층 2 및 12: 층간 절연막1 and 11:
3 및 13: 콘택홀 4 및 14: 얼라인먼트 키3 and 13:
5 및 15: 금속층 6: 보이드5 and 15: metal layer 6: void
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2(a) 및 도 2(b)는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.2 (a) and 2 (b) are cross-sectional views of a device for explaining a method for forming metal wirings of a semiconductor device according to an embodiment of the present invention.
도 2(a)를 참조하면, 하부층(11)상에 층간 절연막(12)이 형성된다. 하부층(11)은 반도체 기판이거나 반도체 소자의 구성 요소중 전극 또는 배선을 이루는 도전층이며, 이러한 하부층(11)의 선택된 부분을 일정 깊이 식각하여 얼라인먼트 키(14)가 형성된다. 층간 절연막(12)의 선택된 부분을 식각 하여 하부층(11)이 노출되는 콘택홀(13)이 형성되며, 이때 얼라인먼트 키(14) 부분도 노출된다. 콘택홀(13) 및 얼라인먼트 키(14)를 포함한 층간 절연막(12)상에 금속 물질을 증착 하여 금속층(15)이 형성된다.Referring to FIG. 2A, an
상기에서, 하부층(11)은 반도체 기판, 워드 라인, 비트 라인, 캐패시터의 전극, 다층 금속 배선 구조일 경우 하부 금속 배선 등이다. 금속층(15)은 텅스텐(W), 알루미늄(Al), 티타늄(Ti), 코발트(Co), 아연(Zn), 구리(Cu), 실리콘(Si), 백금(Pt), 금(Au) 등의 전도성 금속 물질을 사용하여 물리적 기상 증착(PVD) 또는 화학적 기상 증착(CVD) 방법에 의해 형성되는데, 금속 물질의 스텝 커버리지 불량으로 콘택홀(13)이 완전히 매립되지 않으며, 이로 인하여 콘택홀(13) 측면부 및 저면부에서 금속층(15)이 얇게 되고, 이러한 현상이 심할 경우 단락 현상이 발생된다.In the above, the
도 2(b)를 참조하면, 금속층(15)의 콘택 매립 특성 및 단락 현상 등을 줄이기 위해, 단 파장의 레이저 빔(laser beam)을 콘택홀(13) 부분만을 선택적으로 조사하므로, 이 부분의 금속층(15)이 국부적으로 가열되어 콘택홀(13) 부분의 금속층(15)이 리플로우 되어 콘택홀(13)이 매립된다. 금속층(15)은 레이저 빔이 조사된 부분과 조사되지 않은 부분에 두께 차이가 생기게 되는데, 이러한 두께 차이를 줄여 금속층(15)의 표면 평탄화를 이루기 위해 리플로우 공정후에 화학적 기계적 연마(CMP) 공정을 실시할 수도 있다.Referring to FIG. 2B, in order to reduce the contact embedding characteristics and the short-circuit phenomenon of the
상기에서, 조사되는 레이저 빔은 웨이퍼면에 대하여 수직으로 조사하거나, 수직면에 대하여 경사 각도를 주어 좌측 및 우측에서 각각 조사하거나, 경사 각도를 주어 좌측 및 우측에서 각각 조사한 후 수직으로 조사할 수 있다. 레이저 빔이 조사되는 부분은 전술한 바와 같이 콘택홀(13) 부분에만 선택적으로 조사되게 할 수 있고, 얼라인먼트 키(14) 부분을 제외한 모든 부분 또는 선택된 부분(콘택홀 부분 포함)에 조사되게 할 수 있다.In the above, the irradiated laser beam may be irradiated vertically with respect to the wafer surface, or may be irradiated from the left and right by giving an inclination angle with respect to the vertical surface, or may be irradiated vertically after irradiating from the left and right with the inclination angle respectively. The portion to which the laser beam is irradiated may be selectively irradiated only to the
한편, 선택적 레이저 빔 리플로우 공정시, 웨이퍼를 가열하면서 실시할 수 있고, 웨이퍼를 실온보다 낮은 온도로 냉각하면서 실시할 수도 있다.In the selective laser beam reflow step, the wafer may be heated while being heated, or the wafer may be cooled to a temperature lower than room temperature.
상술한 바와 같이, 본 발명은 콘택홀을 포함한 전체 구조상에 금속 물질을 증착한 후에 단 파장의 레이저 빔을 선택적으로 조사하여 콘택홀 부분의 금속층만 리플로우 되어 콘택홀이 양호하게 매립되고, 또한 얼라인먼트 키 부분의 금속층은 리플로우 되지 않아 얼라인먼트 에러가 방지되어 스텝퍼 노광을 정확히 설정할 수 있으므로, 소자의 신뢰성을 향상시킬 수 있다.As described above, in the present invention, after depositing a metal material on the entire structure including the contact hole, the laser beam of short wavelength is selectively irradiated to reflow only the metal layer of the contact hole portion, so that the contact hole is well filled and the alignment is performed. Since the metal layer of the key portion does not reflow, alignment errors are prevented and the stepper exposure can be set accurately, so that the reliability of the device can be improved.
Claims (9)
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| KR1019970081164A KR100276565B1 (en) | 1997-12-31 | 1997-12-31 | Method of forming a metal wiring in a semiconductor device |
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| KR1019970081164A KR100276565B1 (en) | 1997-12-31 | 1997-12-31 | Method of forming a metal wiring in a semiconductor device |
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| KR19990060918A KR19990060918A (en) | 1999-07-26 |
| KR100276565B1 true KR100276565B1 (en) | 2001-02-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7498064B2 (en) | 2004-08-02 | 2009-03-03 | Samsung Electronics Co., Ltd. | Laser reflowing of phase changeable memory element to close a void therein |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06169020A (en) * | 1992-12-01 | 1994-06-14 | Nec Corp | Manufacture of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06169020A (en) * | 1992-12-01 | 1994-06-14 | Nec Corp | Manufacture of semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7498064B2 (en) | 2004-08-02 | 2009-03-03 | Samsung Electronics Co., Ltd. | Laser reflowing of phase changeable memory element to close a void therein |
| US7575776B2 (en) | 2004-08-02 | 2009-08-18 | Samsung Electronics Co., Ltd. | Reflowing of a phase changeable memory element to close voids therein |
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| KR19990060918A (en) | 1999-07-26 |
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