KR100274750B1 - method for operating of non-volatile memory device - Google Patents

Abstract

PURPOSE: A method for driving a non-volatile semiconductor memory(NVM) device is provided to easily form a circuit for generating a high voltage and to reduce the area occupied by the circuit, by applying a low voltage to a control gate in an erase operation. CONSTITUTION: A well of the first conductivity type is formed on a semiconductor substrate of the second conductivity type. A source/drain junction of the second conductivity type is separately formed in the first conductive well to form a channel between the source/drain junction. A floating gate is formed on the channel by interposing the first insulation layer. A control gate is formed on the floating gate by interposing the second insulation layer, connected to a word line. A plurality of flash memory cells have the first conductive well, the source/drain junction, the floating gate and the control gate. An inner source line connecting respective sources of the cells is connected to a common source line by the second select transistor. An inner bit line connecting respective drains of the cells is connected to a main bit line through the first select transistor.

Description

Method for operating of non-volatile memory device

The present invention relates to a nonvolatile memory device that can be electrically programmed and erased, and more particularly to a method of driving a flash memory (Flash memory or Flash EEPROM) which is a nonvolatile semiconductor memory device.

1A shows the configuration of a conventional nonvolatile flash memory. This configuration was published in 1991 on pages 991 to 993 of the International Electron Devices Meeting (IEDM), in which nonvolatile memory cells with floating gates are arranged in parallel between an internal source line and an internal bit line. As shown in the cross-sectional view of the conventional cell of FIG. 2, the unit memory cell has a structure in which control gates are stacked on the floating gate, and the n-type drain and source electrodes of the n-type conductivity type connected to the bit line and the source line and the p-type conductivity type, respectively. The channel is formed on the P-type well (hereinafter P-Well), and has a structure overlapping the floating gate with a gate insulator interposed therebetween. The internal source lines are connected to the common source line by the second select transistor ST2 and the internal bit lines are connected to the main bit line by the first select transistor ST1. These memory cells are programmed or erased by applying a predetermined voltage to the bit line, the source line and the control gate. The cell conditions according to the program and erase of the conventional structure are as follows.

The output of data stored in a program or erased state in a conventional flash memory is performed by setting a threshold voltage of a memory cell as a read condition. The read operation is performed by applying a voltage of about 3 volts to the control gate and sensing a current flowing between the bit line and the source line through the cell to detect the threshold voltage of the cell. That is, the threshold voltage of the erased cell is equal to or greater than the voltage applied to the control gate during the read operation, and the programmed cell has a threshold voltage less than or equal to the control gate voltage. The flash memory structure of FIG. 1 has a read operation characteristic as described above, and is referred to as an "AND type" flash memory because cells are disposed in parallel between an internal source line and an internal bit line.

Since the erase operation of the flash memory is performed in units of selected blocks, sectors, or entire chips, a voltage is applied to the memory array of FIG. 1A under the erase condition of FIG. 1B during the erase operation. Since the program operation is performed in units of bits, bytes, or words, a cell programmed and a cell not programmed under the conventional operating conditions of FIG. 1B are distinguished from conditions of an applied voltage.

In FIG. 2, a cross-sectional structure of a conventional flash memory cell and a voltage applied to each electrode during erase and program operations are shown. During erasing, a high voltage of about 13 volts is applied to the control gate and 0 volts is applied to the drain, source, and P-well electrodes so that electrons float from the channel by Fouler-Nordhein Tunneling. Is injected into the gate. In the program condition, a negative voltage of about -9 volts is applied to the control gate, 3 volts or VCC is applied to the selected bit line, and 0 volts is applied to the bit line to the unselected cells. This applies a voltage of about 14 volts between the control gate and the drain of the cell selected to be programmed and causes electrons to escape from the floating gate toward the drain by Fowler-Nordheim tunneling. On the other hand, a cell that is not selected to be programmed has a voltage difference of 9 volts between the control gate and the drain, so that the field of the floating gate and drain is smaller than the threshold field to cause Fowler-nodeheim tunneling, so the electrons in the cell are not tunneled and erased. State is maintained.

In such a conventional erase operation condition, a high voltage of 13 volts is required at the time of erase. Since the power supply voltage VCC is gradually lowered from 5 volts to 3.3 volts and 2.7 volts, it is increasingly difficult to generate such a high voltage of 13 volts or more from a low power supply. Moreover, as the minimum line width of the design rule of the manufacturing process becomes smaller, the devices and processes of the memory peripheral circuits to withstand the high voltage become increasingly difficult and the cost of the design and manufacturing process of such devices increases. In addition, where a small sized device such as a row decoder is required, the device must be designed with a transistor having a large channel length that can withstand high voltages in the design, thereby increasing the area, which leads to an unnecessary increase in the overall chip area. In addition, due to the high applied voltage, the device deteriorates, which reduces the reliability of the flash memory chip.

Disclosure of Invention The present invention has been made to solve the above problems, and the object of the present invention is to provide a method of driving a flash memory which operates smoothly even at a low supply voltage by increasing the reliability of a chip by lowering a control gate applied voltage during an erase operation. .

1A is a block diagram of a conventional flash memory cell array.

1B is a table showing the operating conditions of a conventional flash memory.

2 is a cross-sectional view showing the structure and operating conditions of a conventional flash memory.

3A is a block diagram of a flash memory cell array of the present invention.

3B is a table showing an operating condition of a flash memory according to an embodiment of the present invention.

Fig. 3C is a diagram showing another operating condition of the flash memory according to another example of the present invention.

4 is a cross-sectional view illustrating a flash memory structure and operating conditions according to an embodiment of the present invention.

5 is a cross-sectional view illustrating a flash memory structure and operating conditions according to another embodiment of the present invention.

A method of driving a flash memory cell of the present invention for achieving the above object is a first conductive well formed in a semiconductor substrate, and the first conductive semiconductor substrate is formed separately from each other for forming a channel therebetween A method of driving a flash memory cell having a source / drain junction of a two-conductor type, a floating gate positioned through a first insulating layer on the channel, and a control gate positioned through a second insulating layer on the floating gate. For the erase driving, a pumped positive voltage or higher than a supply voltage is applied to the control gate, the drain junction is floated, and a negative voltage is applied to the well and source junctions, respectively.

The flash memory driving method of the present invention includes a first conductive well formed in a semiconductor substrate and a second conductive source / drain junction formed separately from each other in the first conductive semiconductor substrate to form a channel therebetween. And a plurality of flash memory cells having a floating gate positioned on the channel via a first insulating layer, and a control gate positioned on the floating gate via a second insulating layer and connected to a word line. A flash having an internal source line connecting the respective sources of the plurality of sources to a common source line by a second selection transistor, and an internal bit line connecting the respective drains of the cells connected to the main bit line through the first selection transistor. In the driving method of a memory, a negative voltage is applied to a gate of the first selection transistor for an erase driving operation. And applying a ground voltage to a gate of the second select transistor, applying a pumped positive voltage greater than a supply voltage to a selected word line, applying a ground voltage to the main bit line, and applying the ground voltage to the common source line and the well. It is characterized by applying a negative voltage to each.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3A, 3B and 3C show the flash memory array and operating conditions of the present invention. Figure 4 shows a cross section of the EEPROM cell required for the present invention and its operation method. 5 shows a cross section of a required EEPROM cell and its operation method according to another embodiment of the present invention.

In the memory array configuration of the present invention, a plurality of nonvolatile memory cells having floating gates are disposed in parallel between an internal source line and an internal bit line, and the internal bit line is connected to the main bit line through the first selection transistor ST1. And an internal source line is connected to a common source line by a second selection transistor ST2, the internal bit line is connected to a drain electrode of the cell, and the internal source line is connected to a source electrode of the cell. The source, drain, and channel of the cell are formed on a P-Well, and the P-Well is formed on an N-type well or an N-type substrate.

The memory array configuration of the present invention has the same configuration as the conventional " AND " flash memory of Fig. 1, but the biggest feature in contrast to the conventional cell structure and operation method is the triple p-Well structure (triple p-Well, Hereinafter, a bias is applied to the well using TP-Well. As a result, the voltage of the control gate is reduced in the erase condition than in the conventional method. The program can also reduce the leakage current by reducing the voltage between the drain and the well. In the following examples, the configuration of the invention will be described in detail.

(First embodiment)

1) Erase operation

Referring to the configuration of the memory array of FIG. 3A, the bias condition of FIG. 3B, and the cell cross-section and operation of FIG. 4, −4 V is applied to the TP-Well and a control gate voltage is about 10 V during erasing. At this time, the source voltage is also -4V so that an inversion layer is formed under the channel. This causes electrons in the channel to be injected into the floating gate by Fowler-Nordheim tunneling. Under the erase condition, the drain of the cell, which is an internal bit line, is in a floating state. In order to block a connection path between the internal bit line and the main bit line, -4 V is applied to the gate of the second selection transistor ST1 and the main bit line is applied to the drain. Apply 0V. The internal source line is supplied with a potential from the common source line to supply a voltage of -4V, and the internal source line and the common source line apply 0V to the first selection transistor ST1 for connecting the current path, and-to the common source line. Apply 4 V. A power supply voltage VCC is applied to the n-type well or n-type substrate surrounding the TP-Well, so that the TP-Well and the n-type well or n-type substrate are in a reverse biased state so that they do not conduct.

This lowers the control gate voltage from 13V to 10V, which simplifies the design and process of the device to be used in the peripheral circuit of the chip, and particularly facilitates the configuration of the column decoder.

2) Program operation

A voltage of -9V is applied to the control gate of the selected cell and the first selection transistor ST1 is conducted to the internal bit line so that the potential of the main bit line is transferred. When the VCC, which is about 3 V or the power supply voltage, is applied to the main bit line and the first select transistor ST1 is 5 V, the main bit line voltage is transferred to the internal bit line. At this time, a voltage of 0 to VCC is applied to the TP-WELL. Under this condition, a voltage difference of about 14 V occurs between the control gate and the drain, and electrons are released from the floating gate to the drain by Fowler-nodeheim tunneling. The internal source line is in a floating state by setting the second select transistor ST2 to 0 V so that a current path from the internal source line side to the common source line is not formed. The internal bit line of the cell that is not selected to be programmed is set to 0V so that the voltage difference between the drain and the control gate is less than 9V and no tunneling occurs from the floating gate toward the drain.

3) read operation

The read operation of the present invention is the same as the conventional structure. It is performed by applying a voltage of about 3 volts to the control gate and sensing the current flowing between the main bit line and the common source line through the cell to detect the threshold voltage of the cell. At this time, the first select transistor ST1 and the second select transistor ST2 are supplied with a power supply voltage or a voltage of 5 V or more to create a conduction state, and an internal source line is connected to the common source line, and an internal bit line is connected to the main bit line. To be connected. That is, the main bit line, the first selection transistor, the internal bit line, the memory cell, the internal source line, the second selection transistor, and the common source line form a current path, and sense the current flowing in the path to detect the threshold voltage of the memory cell. To detect.

(2nd Example)

The cell bias of the second embodiment according to the present invention is shown in FIGS. 3C and 5. The erase operation and the read operation of the second embodiment are the same as in the first embodiment.

The program operation is similar to the method of the first embodiment, except that 0 to power supply voltage is applied without making the internal source line float. To this end, a voltage of 0 to a power source is applied to the common source line, and the second selection transistor is in a conductive state.

The difference between the method of the first embodiment and the present embodiment is that the bias conditions of the TP-Well and the internal source lines are always the same under the erase and program operating conditions. In the present embodiment, since the source line and the TP-Well can be decoded at the same time, there is an advantage that voltage can be simultaneously applied to the source and the TP-Well with only one decoding circuit.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the present invention without departing from the technical idea. It will be evident to those who have knowledge of.

Since the present invention applies a low voltage to the control gate during the erase operation, it is easy to configure a circuit for generating a high voltage, the area is reduced, and the chip reliability is improved.

Claims (6)

A first conductive well formed on a second conductive semiconductor substrate, a source / drain junction of a second conductive type formed separately from each other in the first conductive well and for forming a channel in the well between them; A plurality of flash memory cells having a floating gate formed on the channel via a first insulating film, and a control gate formed on the floating gate via a second insulating film and connected to a word line, An internal source line connecting the respective sources is connected to the common source line by a second selection transistor, and an internal bit line connecting the drains of the cells is connected to the main bit line through the first selection transistor. In the driving method of, For erasing driving, a negative voltage is applied to the gate of the first select transistor, a ground voltage is applied to the gate of the second select transistor, and a pumped positive voltage equal to or greater than a supply voltage is applied to the selected word line. And applying a ground voltage to the main bit line, and applying the same negative voltage to the common source line and the well through the same decoder. The method of claim 1, To drive a program, a positive voltage is applied to a gate of the first select transistor, a ground voltage is applied to a gate of the second select transistor, a negative voltage is applied to a selected word line, and the selected main bit line is applied. Applying a voltage near a supply voltage to the common source line, floating the common source line, and applying a ground or supply voltage to the well. The method of claim 1, To drive a program, a positive voltage is applied to a gate of the first select transistor, a ground voltage is applied to a gate of the second select transistor, a negative voltage is applied to a selected word line, and the selected main bit line is applied. And applying a voltage near the supply voltage to the common source line and the well through a same decoder to the common source line and the well. The method according to any one of claims 1 to 3, And a voltage of about 10 volts is applied to the selected word line, and a voltage of about -4 volts is applied to the well and the common source line for the erase driving. The method according to claim 2 or 3, And a voltage of about -9 volts is applied to the selected word line, and a voltage of about 3 volts is applied to the main bit line for driving the program. The method according to claim 2 or 3, And a supply voltage is applied to the semiconductor substrate for the erasing and the program driving.

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