KR20110043941A - Bias circuit of flash memory - Google Patents

Abstract

PURPOSE: A bias circuit of a flash memory is provided to perform a program operation and an erase operation through a hot carrier by supplying a first type positive high voltage, a second type negative high voltage, and a pass voltage. CONSTITUTION: In a bias circuit of a flash memory, a DC-DC converter(100) forms a positive DC current signal and a negative DC current signal. A cell gate switch(200) is connected to the DC-DC converter. The cell gate switch outputs one of the positive DC current signal and the negative DC current signal as a word line signal controlling a cell transistor. A p- well switch(300) receives the specific signal of the DC current signals and generates a p-well signal, which is supplied to the p-well in the lower part of the cell transistor.

Description

Bias Circuit of Flash Memory

The present invention relates to a flash memory, and more particularly, to a bias circuit of a flash memory for applying a predetermined voltage to the flash memory.

The nonvolatile memory has a characteristic of retaining stored information even when power is removed. Flash memory is a typical nonvolatile memory, and has a structure in which two gate layers are stacked on one cell transistor, or a charge storage layer is interposed between two dielectric layers.

The flash memory performs program and erase operations through Fowler-Nordheim (F-N) tunneling or hot carrier injection (Hot Carrier Injection).

F-N tunneling is an operation in which charge is moved by the voltage difference between the voltage in the channel region and the charge storage layer. This has the disadvantage that the operating time is slow.

Hot carrier injection is a phenomenon in which charge accelerated by a voltage difference in a source or drain region passes through a tunneling oxide film by a voltage applied to a gate electrode.

The NAND flash memory has a feature of reading data in units of pages, and mainly performs F-N tunneling during an erase operation. Therefore, slow operation speed becomes a problem.

Recently, a technique for flash memory that performs a NOR operation while arranging cells in the form of a NAND type has been disclosed. In US 2007-236994, a high voltage is applied between a p-well and a source / drain region to collect charge around a depletion region, and then a high voltage is applied between the p-well and the gate electrode to transfer charge into a channel region. Move, and take a program operation to capture charge into the charge storage layer.

In addition, the erase operation takes a complementary operation as compared with the program operation.

In addition, Korean Patent Application No. 2008-89407 by the present applicant discloses a technology for configuring a NAND type flash memory using the above-mentioned United States United States Patent Publication. The normal operation of the above-described techniques requires voltages of various levels, such as a high voltage applied to the gate electrode and the p-well, a negative high voltage applied to the gate electrode, and a pass voltage for turning on the cell transistor included in the string.

Disclosure of Invention An object of the present invention to solve the above-mentioned problem is to collect charges accumulated around a depletion region between a source / drain region or a p-well in a charge storage layer of a cell transistor, or to tunnel the collected charges into a channel region. It is to provide a bias circuit.

The present invention for achieving the above object, DC-DC converter for forming a positive DC signal and a negative DC signal in accordance with the reference voltage and the oscillation signal; A cell gate switch connected to the DC-DC converter and configured to select one of the positive DC signals and the negative DC signal to output a word line signal for controlling a cell transistor; And a p-well switch for receiving and selecting a specific one of the positive DC signals according to a p-well control signal to generate a p-well signal supplied to a p-well under the cell transistor. Provide a bias circuit for the memory.

According to the present invention described above, one kind of high voltage, one kind of negative high voltage and a pass voltage can be supplied to the word line through the bias circuit. In addition, it is possible to supply the ground level and one kind of high voltage to the word line. This enables program and erase operations through hot carrier injection without using F-N tunneling.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

Example

1 is a block diagram illustrating a bias circuit according to a preferred embodiment of the present invention.

Referring to FIG. 1, the bias circuit according to the present embodiment has a DC-DC converter 100, a cell gate switch 200, and a p-well switch 300.

The DC-DC converter 100 forms the positive DC signals HV_A, HV_B, HV_C, HV_D and the negative DC signal VEEI according to the reference voltage Vref and the oscillation signal OSC. Positive DC signals HV_A, HV_B, HV_C, and HV_D are input to the cell gate switch 200, and the third DC signal HV_C which is a specific DC signal among the positive DC signals is input to the p-well switch 300. .

The enable signal EN, the reference voltage Vref, and the oscillation signal OSC are input to the DC-DC converter 100. The DC-DC converter 100 receives the reference voltage Vref and the oscillation signal OSC to generate five first DC signals HV_A, second DC signals HV_B, third DC signals HV_C, fourth DC signals HV_D, and negative DC signals. Output VEEI. In particular, the DC-DC converter is activated by the enable signal EN.

The cell gate switch 200 is connected to the DC-DC converter 100 and selects any one of four positive DC signals HV_A, HV_B, HV_C, HV_D, and the negative DC signal VEEI to form a NAND flash memory. To the gate electrode of the cell transistor.

The cell gate switch 200 receives the DC signals HV_A, HV_B, HV_C, HV_D and VEEI of the DC-DC converter 100, and receives the first voltage control signal IN_A, the second voltage control signal IN_B, and the third voltage control signal. Receives H_pass and receives decode control signal GWL and negative voltage control signal VEEXIN. The cell gate switch 200 selects a specific signal from a plurality of control signals among the DC signals applied to form a word line signal WL for applying to a gate electrode of the cell transistor.

The p-well switch 300 receives the p-well control signal PW_IN and the sync control signal SINK_IN. In addition, the third DC signal HV_C is applied to the p-well switch 300.

The p-well switch 300 is connected to the DC-DC converter 100, receives a third DC signal HV_C, and selects one of a ground level and a third DC signal HV_C to form a p-well signal Pwell. do. The formed p-well signal Pwell is supplied to a p-well located under the cell transistor. This results in the accumulation of charge between the p-well and the source / drain regions and the tunneling operation through the tunneling oxide.

The word line signal WL, which is the output of the cell gate switch 200, is used for the program and erase operations of the cell transistors of the flash memory disclosed in US 2007-236994. That is, a high voltage must be applied to the gate electrode to collect charges provided in the floated source / drain region and the depletion region with the p-well through the tunneling oxide film and into the charge storage layer represented by the nitride film. The high voltage required for the program uses the third DC signal HV_C in this embodiment. In addition, a high negative voltage is required for the erase operation. This uses the negative DC signal VEEI in this embodiment.

In addition, a high voltage must be applied to the p-well in order to form charge around the depletion region with the source / drain region and the p-well, which uses the third DC signal HV_C in this embodiment.

FIG. 2 is a block diagram illustrating the DC-DC converter shown in FIG. 1.

Referring to FIG. 2, the DC-DC converter has a first regulator 110, a second regulator 130, and a third regulator 150.

Each regulator is supplied with an enable signal EN, a reference voltage Vref and an oscillation signal OSC.

The first regulator 110 outputs the first DC signal HV_A and the second DC signal HV_B. The second DC signal HV_B is set higher than the first DC signal HV_A, and is set to have a difference greater than or equal to a threshold voltage of the transistor compared to the first DC signal HV_A. In particular, the first DC signal HV_A turns on a cell transistor and is supplied as a pass voltage of the transistor during a read operation. That is, the pass voltage supplied to the gate electrode of the cell transistor is set to a level at which the cell transistor is turned on. Accordingly, the first DC signal HV_A may have a level of 3.5V to 4.5V, and the second DC signal HV_B may have a level of 4.5V to 5.5V.

The second regulator 130 outputs the third DC signal HV_C and the fourth DC signal HV_D. In particular, the fourth DC signal HV_D is set higher than the third DC signal HV_C and is set to have a higher value than the third DC signal HV_C above the threshold voltage of the transistor. The third DC signal HV_C is set to a level suitable for tunneling charge accumulated in the channel region through the gate electrode of the cell transistor through the tunneling oxide film. For example, the third DC signal HV_C may be set to 8.5V to 9.5V. Therefore, the fourth DC signal HV_D may be set to 9.5V to 10.5V.

The third regulator 150 outputs a negative DC signal VEEI. The negative DC signal VEEI is used to form a negative high voltage required for the erase operation of the cell transistor. For example, the negative DC signal VEEI may have a level of -9.5V to -8.5V.

3 is a block diagram illustrating the cell gate switch illustrated in FIG. 1.

Referring to FIG. 3, the cell gate switch has a high voltage selector 210, a high voltage switch 230, a negative high voltage switch 250, and a decoder 270.

The high voltage selector 210 receives the first DC signal HV_A, the second DC signal HV_B, the third DC signal HV_C, and the fourth DC signal HV_D, and receives the first voltage control signal IN_A and the second voltage control signal IN_C. The high voltage selector 210 outputs the selection voltage signal VPPX under the control of the first voltage control signal IN_A and the second voltage control signal IN_C. The selection voltage signal VPPX is set to any one of the first DC signal HV_A and the third DC signal HV_C. That is, the high voltage selector 210 selects one of the first DC signal HV_A and the third DC signal HV_C by controlling two voltage control signals. The selected DC signal VPPX is input to the high voltage switch 230.

The high voltage switch 230 receives the third voltage control signal H_pass and the selection voltage signal VPPX. The high voltage switch 230 outputs a selection voltage signal VPPX or outputs a ground level according to whether the third voltage control signal H_pass is activated. For example, when the third voltage control signal H_pass is high level, the switching output signal HXT is the selection voltage signal VPPX, and when the third voltage control signal H_pass is low level, the switching output signal HXT may be the ground level.

The negative high voltage switch 250 receives the negative DC signal VEEI and the negative voltage control signal VEEXIN, and outputs the negative switching output signal VEEX. The negative high voltage switch selects one of the negative DC signal VEEI and the ground level according to the negative voltage control signal VEEXIN. For example, when the negative voltage control signal VEEXIN is at a high level, the negative switching output signal VEEX becomes a negative DC signal VEEI. In addition, when the negative voltage control signal VEEXIN is at a low level, the negative switching output signal VEEXIN is at a ground level.

The decoder 270 receives the output HXT of the high voltage switch, the output VEEX of the negative high voltage switch, and the decoder control signal GWL. The output of the decoder 270 becomes the word line signal WL. The decoder 270 selects and outputs any one of the switching output signal HXT and the negative switching output signal VEEX under the control of the decoder control signal GWL.

4 is a block diagram illustrating the high voltage selector illustrated in FIG. 3.

Referring to FIG. 4, the high voltage selector is composed of four high voltage switches 211, 213, 215, and 217 and two switching transistors Q1 and Q2. In addition, the high voltage switches 211, 213, 215, and 217 shown in FIG. 4 have the same configuration, but only different input signals. In addition, the high voltage switches 211, 213, 215, and 217 illustrated in FIG. 4 have the same configuration as the high voltage switch 230 illustrated in FIG. 3.

A first DC signal HV_A and a first voltage control signal IN_A are input to the first high voltage switch 211. The first high voltage switch 211 selects one of the first DC signal HV_A and the ground level under the control of the first voltage control signal IN_A and outputs the selected voltage to the first switching transistor Q1.

A second DC signal HV_B and a first voltage control signal IN_A are input to the second high voltage switch 213. The second high voltage switch 213 selects one of the second DC signal HV_B and the ground level according to the control of the first voltage control signal IN_A and outputs it to the gate terminal of the first switching transistor Q1.

For example, when the first voltage control signal IN_A has a high level, the first high voltage switch 211 selects and outputs the first DC signal HV_A, and the second high voltage switch 213 selects the second DC signal HV_B. Output Since the second DC signal HV_B has a value greater than the threshold voltage of the transistor compared to the first DC signal HV_A, the first selection transistor Q1, which is an NMOS transistor, is turned on. Therefore, the first DC signal HV_A is output as the selection voltage signal VPPX through the first selection transistor Q1.

For example, when the first voltage control signal IN_A has a low level, the first high voltage switch 211 selects and outputs a ground level, and the second high voltage switch 213 also selects and outputs a ground level. Thus, the first select transistor Q1 is turned off.

A third DC signal HV_C and a second voltage control signal IN_C are input to the third high voltage switch 215. The third high voltage switch 215 selects and outputs any one of the third DC signal HV_C and the ground level according to the control of the second voltage control signal IN_C. The output signal of the third high voltage switch 215 is input to the second switching transistor Q2.

The fourth DC signal HV_D and the second voltage control signal IN_C are input to the fourth high voltage switch 217. The fourth high voltage switch 217 selects and outputs one of the fourth DC signal HV_D and the ground level according to the control of the second voltage control signal IN_C. The output signal of the fourth high voltage switch 217 is input to the gate terminal of the second switching transistor Q2.

For example, when the second voltage control signal IN_C has a high level, the third high voltage switch selects and outputs the third DC signal HV_C, and the fourth high voltage switch 217 selects and outputs the fourth DC signal HV_D. . Since the fourth DC signal HV_D has a value greater than the threshold voltage of the transistor compared to the third DC signal HV_C, the second selection transistor Q2, which is an NMOS transistor, is turned on. Therefore, the third DC signal HV_C is output as the selection voltage signal VPPX through the second selection transistor Q2.

For example, when the second voltage control signal IN_B has a low level, the third high voltage switch 215 selects and outputs a ground level, and the fourth high voltage switch 217 also selects and outputs a ground level. Thus, the second select transistor Q2 is turned off.

Preferably, the first voltage control signal IN_A and the second voltage control signal IN_B perform complementary operations with each other. Therefore, when the first DC signal HV_A is output through the first selection transistor Q1 by the operation of the first high voltage switch 211 and the second high voltage switch 213, the third high voltage switch 215 and the fourth high voltage switch 217 preferably outputs a ground level to turn off the second select transistor Q2. Therefore, the selection voltage signal VPPX, which is the output of the high voltage selector, has either one of the first DC signal HV_A and the third DC signal HV_C.

If the first voltage control signal IN_A and the second voltage control signal IN_C are inactive or have a low level, the selection voltage signal VPPX is in a floating state. This is a result of the off states of the first select transistor Q1 and the second select transistor Q2.

In addition, each of the high voltage switches 211, 213, 215, and 217 illustrated in FIG. 4 has the same configuration and function as the high voltage switch 230 illustrated in FIG. 3. For example, the selection voltage signal VPPX is applied to the terminal corresponding to the first DC signal HV_A in the first high voltage switch 211, and the third voltage control signal H_pass is applied to the terminal corresponding to the first voltage control signal IN_A.

FIG. 5 is a circuit diagram illustrating the high voltage switch illustrated in FIGS. 3 and 4.

Referring to FIG. 5, an input signal HV is applied and a control signal IN is applied. The input signal HV corresponds to the selection voltage signal VPPX of FIG. 3 and the first to fourth DC signals HV_A, HV_B, HV_C, and HV_D of FIG. 4. In addition, the control signal IN corresponds to the third voltage control signal H_pass of FIG. 3 and the first to second voltage control signals IN_A and INC of FIG. 4.

The high voltage switch has a selection controller 220 and a voltage selector 222.

The selection controller 220 includes four transistors T1, T2, T3, and T4 and an inverter. First, when the input signal IN is at a high level, the first transistor T1 is turned on and the second transistor T2 is turned off via the inverter. The first node N1 is set to a low level by the turned-on first transistor T1, and the third transistor T3 is turned on. Accordingly, the input signal HV appears at the second node N2. The fourth transistor T4 is turned off by the input signal HV set at the second node N2.

The voltage of the first node N1 having a low level is transferred to the voltage selector 222. The voltage selector 222 is configured as an inverter. The fifth transistor T5 is turned off and the sixth transistor T6 is turned on by the voltage of the first node N1 at the low level. Therefore, the input signal HV appears at the output terminal OUT.

When the input signal IN is at the low level, the first transistor T1 is turned off and the second transistor T2 is turned on via the inverter. Accordingly, a low level voltage is applied to the second node N2, and the fourth transistor T4 is turned on by the voltage applied to the second node N2. The input signal HV is applied to the first node N1 by the turned-on fourth transistor T4. In addition, the third transistor T3 is turned off by the voltage of the first node N1. The sixth transistor T6 of the voltage selector is turned off and the fifth transistor T5 is turned on by the voltage of the first node N1 to which the input signal HV is applied. Thus, the output of the ground level appears.

FIG. 6 is a circuit diagram illustrating the negative high voltage switch shown in FIG. 3.

Referring to FIG. 6, the negative high voltage switch has a control path forming unit 251, a path selecting unit 253, and an output unit 255.

The control path forming unit 251 performs a switching operation according to the negative voltage control signal VEEXIN and outputs a positive power supply voltage VDD. In addition, the path selector 253 receives the negative DC signal VEEI and outputs the negative DC signal VEEI through a switching operation, and the output unit 255 controls the positive power supply voltage VDD and the negative DC signal VEEI. Outputs a negative DC signal VEEI or ground level.

The control path forming unit 251 is composed of two inverters and two PMOS transistors T9 and T10, the path selector 253 is composed of two NMOS transistors T11 and T12, and the output unit 255 is It consists of two NMOS transistors T13 and T14.

First, when the negative voltage control signal VEEXIN has a high level, a low level appears at the third node N3 passing through the first inverter, and a high level appears at the fourth node N4 passing through the second inverter. The tenth transistor T10 is turned on by the low level third node N3, and the high level is set at the sixth node N6. In addition, the ninth transistor T9 is turned off by the voltage of the fourth node N4 at the high level.

As a result, a high level voltage is set at the sixth node N6 of the path selector 253, the eleventh transistor T11 is turned on, and a negative DC signal VEEI appears at the fifth node N5. Thus, the twelfth transistor T12 is turned off. As a result, only one of the two transistors T9 and T10 constituting the path selector 253 is turned on by the operation of the control path forming unit 251.

The thirteenth transistor T13 is turned off due to the negative DC signal VEEI level of the fifth node N5. This is because the negative DC signal VEEI may have a level of -8.5V to -9.5V as described above. Further, the fourteenth transistor T14 is turned on by the voltage of the high level sixth node N6, and the negative DC signal VEEI appears in the output signal VEEX.

If the negative voltage control signal VEEXIN has a low level, the third node N3 has a high level and the fourth node N4 has a low level. Thus, the ninth transistor T9 is turned on and the tenth transistor T10 is turned off. Therefore, a high level signal is set at the fifth node N5.

The twelfth transistor T12 is turned on by the voltage of the fifth node N5 having a high level, and the negative DC signal VEEI appears at the sixth node N6. As a result, the fifth node N5 is set to the high level, and the sixth node N6 is set to the negative DC signal VEEI.

The thirteenth transistor T13 is turned on by the fifth node N5 having the high level, and the fourteenth transistor T14 is turned off by the sixth node N6 having the negative DC signal VEEI level. Therefore, the voltage of the ground level is output to the output signal VEEX.

FIG. 7 is a circuit diagram illustrating the decoder illustrated in FIG. 3.

Referring to FIG. 7, the decoder has a configuration of an inverter. First, the switching output signal HXT is applied to the drain terminal of the fifteenth transistor T15 constituting the decoder, and the negative switching output signal VEEX is applied to the source terminal of the sixteenth transistor T16. The switching output signal HXT is an output signal of the high voltage switch shown in FIG. 5, and the negative switching output signal VEEX is an output signal of the negative high voltage switch shown in FIG. 6.

In addition, the gate terminals of the two transistors are commonly connected, and the decoder control signal GWL is applied.

When the decoder control signal GWL is at the low level, the fifteenth transistor T15 is turned on, and the switching output signal HXT is output to the wordline signal WL. In addition, when the decoder control signal GWL is at a high level, the sixteenth transistor T16 is turned on and a negative switching output signal VEEX is output to the wordline signal WL. That is, the decoder selectively outputs the switching output signal HXT or the negative switching output signal VEEX by the decoder control signal GWL.

FIG. 8 is a circuit diagram illustrating the p-well switch shown in FIG. 1.

Referring to FIG. 8, the p-well switch includes a control signal generator 310, an output signal generator 330, and a current sink 350. However, the current sink 350 may be omitted as necessary.

The control signal generator 310 selectively outputs the third DC signal HV_C according to the p-well control signal PW_IN, and the output signal generator 330 according to the p-well control signal PW_IN and the third DC signal HV_C. The third DC signal HV_C is selected. In addition, the current sink 350 is connected to the output terminal of the output signal generator 330 to force the output signal to the ground level.

The third DC signal HV_C and the p-well control signal PW_IN are applied to the control signal generator 310, and are composed of two inverters and four transistors T15, T16, T17, and T18. However, the inverter between the p-well control signal PW_IN and the seventh node N7 may be omitted.

The output signal generator 330 has two transistors T19 and T20, and the two transistors T19 and T20 perform complementary operations according to the signal generated at the ninth node N9 and the signal generated at the seventh node N7. do. Therefore, the p-well signal Pwell, which is an output signal, has a value of ground level or the third DC signal HV_C.

The current sinker 350 is used to forcibly set the voltage set at the output terminal to the ground level. This is to disable the p-well switch in special cases and to force the p-well signal Pwell to ground level. In addition, it may be used to ensure fast operation time when the output signal is switched from the third DC signal HV_C to the ground level.

First, when the p-well control signal PW_IN is at a high level, the seventh node N7 is at a low level. Thus, the fifteenth transistor T15 is turned off, and the sixteenth transistor T16 that has passed through the inverter is turned on. Therefore, the ninth node N9 is set at the low level. The eighteenth transistor T18 is turned on by the ninth node N9 of the low level, and the eighth node N8 is set to the third DC signal HV_C. Thus, the seventeenth transistor T17 is turned off.

Subsequently, the nineteenth transistor T19 is turned on by the voltage of the low level ninth node N9, and the twentieth transistor T20 is turned off by the voltage of the low level seventh node N7. Accordingly, the third DC signal HV_C appears at the tenth node N10. That is, the p-well signal Pwell becomes the third DC signal HV_C. At this time, the current sink is preferably off. Therefore, the sink control signal SINK_IN for controlling the twenty-first transistor T21 is set at a low level.

If the p-well control signal PW_IN is at a low level, the seventh node N7 is set to a high level and the fifteenth transistor T15 is turned on. The sixteenth transistor T16 that has passed through the inverter is turned off. The eighth node N8 is set to a low level by the turned on fifteenth transistor T15, and the seventeenth transistor T17 is turned on. The third DC signal HV_C is displayed at the ninth node N9 by the turned-on seventeenth transistor T17, thereby turning off the eighteenth transistor T18.

Since the level of the ninth node N9 is the third DC signal HV_C, the nineteenth transistor N19 is turned off, and the twentieth transistor T20 is turned on by the voltage of the seventh node N7 which is a high level. Thus, the ground level appears at the tenth node N10. At this time, in order to switch to the fast ground level at the output node of the tenth node N10, the current sink needs to be activated to quickly move the charge accumulated in the ninth node N9 to ground. Therefore, it is preferable that the sink control signal SINK_IN for controlling the twenty-first transistor T21 is set to a high level.

The bias circuit provided in accordance with the present invention described above supplies a predetermined voltage to the word line and p-well. The word line can be supplied with the high voltage required for the program operation and the pass voltage required for the read operation. In addition, a negative high voltage for the erase operation may be provided to the word line. In addition, by supplying a positive high voltage to the p-well, charge can be accumulated and a ground voltage necessary for program and erase operations can be provided.

1 is a block diagram illustrating a bias circuit according to a preferred embodiment of the present invention.

FIG. 2 is a block diagram illustrating the DC-DC converter shown in FIG. 1.

3 is a block diagram illustrating the cell gate switch illustrated in FIG. 1.

4 is a block diagram illustrating the high voltage selector illustrated in FIG. 3.

FIG. 5 is a circuit diagram illustrating the high voltage switch illustrated in FIGS. 3 and 4.

FIG. 6 is a circuit diagram illustrating the negative high voltage switch shown in FIG. 3.

FIG. 7 is a circuit diagram illustrating the decoder illustrated in FIG. 3.

FIG. 8 is a circuit diagram illustrating the p-well switch shown in FIG. 1.

Claims (10)

A DC-DC converter for forming positive DC signals and negative DC signals according to the reference voltage and the oscillation signal; A cell gate switch connected to the DC-DC converter and configured to select one of the positive DC signals and the negative DC signal to output a word line signal for controlling a cell transistor; And a flash memory including a p-well switch for receiving and selecting a specific one of the positive DC signals according to a p-well control signal to generate a p-well signal supplied to a p-well under the cell transistor Bias circuit. The method of claim 1, wherein the DC-DC converter, A first DC signal for receiving the reference voltage and the oscillation signal and for generating a first DC signal having a pass voltage level of a cell transistor and a second DC signal having a value greater than or equal to a threshold voltage of the transistor compared to the first DC signal; regulator;  A third DC signal having a control gate voltage level for receiving the reference voltage and the oscillation signal and tunneling charges formed around a depletion region of a cell transistor to a charge storage layer and a threshold voltage of a transistor compared to the third DC signal. A second regulator for generating a fourth DC signal having a large value; And And a third regulator for receiving the reference voltage and the oscillation signal and generating a negative DC signal having a control gate voltage level for moving charges stored in the charge storage layer to a channel region. Bias circuit in memory. 3. The cell gate switch of claim 2, wherein the cell gate switch comprises: a high voltage selector for selecting the first DC signal or the third DC signal; A high voltage switch for receiving an output of the high voltage selector and for determining a received high voltage selector or ground level; A negative high voltage switch for receiving the negative DC signal and for determining the received negative DC signal or ground level; And And a decoder for selecting one of an output of the high voltage switch and an output of the negative high voltage switch according to a decoder control signal to determine the word line signal. The method of claim 3, wherein the high voltage selector, A first high voltage switch for receiving the first DC signal and selecting the first DC signal or the ground level according to the control of the first voltage control signal; A second high voltage switch for receiving the second DC signal and selecting the second DC signal or the ground level according to the control of the first voltage control signal; A third high voltage switch configured to receive the third DC signal and select the third DC signal or the ground level according to the control of the second voltage control signal to perform a complementary operation with the first voltage control signal; A fourth high voltage switch for receiving the fourth DC signal and selecting the fourth DC signal or the ground level according to the control of the second voltage control signal; A first switching transistor configured to perform an on / off operation according to an output signal of the second high voltage switch to transfer the first DC signal selected by the first high voltage switch; And And a second switching transistor configured to transfer the third DC signal selected by the third high voltage switch by performing an on / off operation according to the output signal of the fourth high voltage switch. The bias circuit of claim 4, wherein the first switching transistor and the second switching transistor perform on / off operations complementary to each other. The method of claim 3 or 4, wherein the high voltage switch or the first to fourth high voltage switch, A selection controller for selectively setting a DC signal or a ground level according to the control signal; And And a voltage selector for receiving the DC signal or the ground level of the selection controller and selecting the DC signal or the ground level, wherein the output of the selection controller is complementary to the output of the voltage selector. Bias circuit. The method of claim 3, wherein the negative high voltage switch, A control path forming unit for outputting a positive power supply voltage through a switching operation according to a negative voltage control signal; A path selector for receiving the negative DC signal and outputting the negative DC signal through a switching operation; And And an output unit for outputting the negative DC signal or the ground level in accordance with the control of the positive power supply voltage and the negative DC signal. The method of claim 2, wherein the p-well switch, a control signal generator for selectively outputting the third DC signal according to a p-well control signal; And an output signal generator for selectively generating the third DC signal through a switching operation according to the control of the p-well control signal and the third DC signal. The bias circuit of claim 8, wherein the p-well switch further comprises a current sink connected to an output terminal of the output signal generator and forcing the output terminal to a ground level. The bias circuit of claim 9, wherein the current sink is activated when the output signal generator wants to output a ground level.

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