KR100271636B1 - Frequency detector for low power - Google Patents

Abstract

PURPOSE: A power-efficient frequency detector is provided to reduce power consumption by detecting the current input frequency and stopping counting action when the frequency detection is completed. CONSTITUTION: A counter(10) counts the currently-input oscillating signal(fs) using a reference clock(clk) and determines whether the counting action will be continued according to the feedback frequency. A frequency detector(20) detects the corresponding frequency using the output count value from the counter(10) and is initialized by the reset signal(reset_) from outside. A consumption power regulator outputs a signal(confirm) that determines the continuation of the counting action according to the detection frequency from the frequency detector(20).

Description

Low Power Frequency Detectors {FREQUENCY DETECTOR FOR LOW POWER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low power frequency detector for identifying a frequency currently input within a chip itself, and more particularly to a low power frequency detector for reducing power consumption.

FIG. 1 is a conventional frequency selection circuit diagram. As shown therein, a first oscillation signal (crystal 1) and a second oscillation signal (crystal 2) having different frequencies are received as inputs, and a selection signal from an external source (sel) is shown. And a multiplexer (MUX) for selecting and outputting the first oscillation signal (crystal 1) or the second oscillation signal (crystal 2).

2 is a conventional frequency supply circuit diagram. As shown in FIG. 2, a counter 1 for counting an oscillation signal crystal having no frequency using a reference clock clk and outputs the counter 2 are outputted. It is composed of a frequency detector (2) for receiving the frequency detected.

Looking at the prior art configured as described above is as follows.

FIG. 1 is a method of selecting internally two or more frequencies and their frequencies by simply using a multiplexer (MUX) without any hardware for detecting frequencies.

Herein, a case in which one of two frequencies is selected and outputted will be described with reference to FIG. 1. The first oscillation signal crystal 1 and the second oscillation signal crystal 2 having different frequencies are respectively provided to the multiplexer MUX. Is entered.

Then, the multiplexer MUX selects and outputs the first oscillation signal crystal 1 or the second oscillation signal crystal 2 by the selection signal sel input from the outside.

FIG. 2 is a method of detecting and receiving various frequencies in one mode. Referring to this, when an oscillation signal (crystal) of a specific frequency is input, the counter 1 receives a reference clock clk input to another input terminal. Counting the oscillation signal (crystal) currently being input by using and provide the counting value to the frequency detector (2).

The frequency detector 2 then determines a frequency corresponding to the counting value and outputs the determined frequency.

Each time a new frequency is input to the frequency detector 2, a reset signal is input to initialize the frequency detector 2.

At this time, the frequency detector 2 is initialized by a reset signal.

However, in the prior art as described above, since the counting operation must be continued by using a clock when frequency is detected, power consumption is severe because power is continuously consumed, and when the frequency is changed, there is a problem of causing inconvenience.

Accordingly, an object of the present invention for solving the conventional problems as described above is to provide a low power frequency detector for determining the frequency of the oscillation signal currently input in the chip itself.

It is another object of the present invention to provide a low power frequency detector for eliminating unnecessary power consumption by stopping the operation by itself when the frequency detection operation is completed.

1 is a conventional frequency selection circuit diagram.

2 is a conventional frequency detection circuit diagram.

Figure 3 is a block diagram of a low power frequency detector of the present invention.

4 is a detailed circuit diagram of the counter unit in FIG. 3;

FIG. 5 is a detailed circuit diagram of a frequency detector in FIG. 3. FIG.

FIG. 6 is a detailed circuit diagram of a power consumption controller of FIG. 3. FIG.

*** Explanation of symbols for main parts of drawing ***

10: counter 20: frequency detector

30: power consumption control unit

According to an aspect of the present invention, a counter unit for counting an oscillation signal having a specific frequency using a reference clock, a frequency detector for determining a corresponding frequency using a count value output from the counter unit, and the frequency detector It is characterized in that the power consumption control unit for reducing the power consumption by controlling the operation of the counter unit to determine whether the operation.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram illustrating a low power frequency detector of the present invention. As shown in FIG. 3, a counter unit 10 for counting an oscillation signal fs having a specific frequency as a reference clock clk and the counter The frequency detector 20 that determines the frequency from the count value output from the unit 10, and the power consumption controller 30 that controls the operation of the counter unit 10 by determining whether the frequency detector 20 is operated. ).

As illustrated in FIG. 5, the frequency detector 20 receives an output of the counter 10 and determines an amplitude of the frequency, and an output of the AND gate 21. A multiplexer 22 which selects and outputs any one signal according to the selection signal and the input frequency fs is inverted and the inverted signal is used as the input terminal and the signal fed back as the other input terminal and as a selection signal. The inverter 24 outputs the frequency fs_b, and the multiplexer 22 inputs the output signal of the inverter 24 to the clock input terminal cp to the data input terminal d when the rising edge of the signal is received. The output is shifted one by one to output the detected frequency, and configured as a de-flip flop 23 initialized by an externally reset signal reset_.

In addition, as shown in FIG. 5, the power consumption controller 30 shifts the detection frequency input to the data input terminal d one by one in synchronization with the reference clock clk input to the clock input terminal cp. A reference for inputting the first reset flip-flop 31 initialized by the reset signal reset_ input from the outside and the output of the flip-flop 31 input to the data input terminal to the clock input terminal cp. Each of the preset deflip-flops 32, which are shifted one by one in synchronization with the clock clk and set by the reset signal reset_ input from the outside, and the preset deflip-flops 32 input to the data input terminal. A second reset flip-flop 33 which is shifted one by one in synchronization with the reference clock clk inputted to the clock input terminal cp and initialized by a reset signal reset_ input from the outside; Output terminal of flip-flops 31-33 ( an AND gate 34 for ANDing the value output through q), an AND gate 35 for ANDing the value output through the inverting output terminal qn of the deflip-flops 31 to 33, and The output of the AND gates 34 and 35 is composed of an ora gate 36 that outputs a signal for determining whether or not a counting operation is performed.

Referring to the operation and effect of the present invention configured as described in detail as follows.

When an oscillation signal of a specific frequency fs is initially input, the counter unit 10 counts using the reference clock clk, and outputs the counted value to the frequency detector 20.

Here, the operation of the counter unit 10 will be described in more detail with reference to FIG. 4. The oscillation signal of a specific frequency fs is clocked by the first to eighth counters cnt1 to cnt8 constituting the counter unit 10. The input signal is input to the pulse input terminal cp, and the reference clock clk is input to the reset terminal cdn, respectively.

At this time, the signal confirmation fed back from the power consumption controller 30 is inverted through the inverter I1 and input to the input terminal ci of the first counter cnt1.

When the feedback signal confirm is inverted through the inverter I1 and is inverted and the level input to the input terminal ci of the first counter cnt1 is "0", the counter does not operate and is "1". In this case, up counting is performed at the rising edge of the reference clock clk inputted to the clock pulse input terminal cp.

The output value q <0> is output through the output terminal q of the first counter cnt1, and the carry output terminal co of the first counter cnt1 is the input terminal ci of the second counter cnt2. Is counted and the output value is output through the output terminal q thereof to output an output value q &lt;

In this method, the first counters cnt1 to eighth counters cnt8 output the counted values q <0> to q <7>, respectively, through the output terminal q thereof.

Then, the output of the counter 10 is input from the frequency detector 20 to detect the frequency. The detection method will be described with reference to FIG. 5 as follows.

The output values q <1> and q <7> respectively output from the second counter cnt2 and the eighth counter cnt8 among the counted values of the counter unit 10 are the AND gate 21 of the frequency detector 20. Is inputted and outputted to the input terminal i0 of the multiplexer 22.

If the output of the AND gate 21 is high, the frequency detection operation is performed. If the output of the AND gate 21 is low, the frequency detection operation is stopped and the previous frequency is fed back and output.

If the input of the AND gate 21 is adjusted here, the number to be detected can be changed.

In other words, when a new frequency is inputted, it is reset by the reset signal so that the output of the flip-flop 23 (detect_384fs) goes low.

When the low signal is input to the selection terminal SEL of the multiplexer 22, the multiplexer 22 receives the output of the AND gate 21 as an input io and provides the output to the deflip-flop 23.

Then, the deflip-flop 23 detects a frequency by synchronizing an input to the data input terminal d with a reference clock clk inputted to the clock pulse input terminal cp and adjusting the detection frequency detect_384fs. Output to the unit 30.

Until the new frequency is input, the detection signal of the high state output from the flip-flop 23 is input to the selection terminal SEL of the multiplexer 22.

Accordingly, the multiplexer 22 receives the input i1 fed back and inputs it to the deflip-flop 23.

As a result, until there is a new input, the output of the deflip-flop 23 is continuously fed back to the power consumption controller 30.

The detected frequency detector_384fs is input to the data input terminal d of the first reset de-flop 31 of FIG. 6 constituting the power consumption control unit 30, and the first reset de-flop ( A reference clock clk is input to the clock input terminal of 31).

Initially, the first and second reset flip-flops 31 and 33 are reset to "0" by the reset signal reset_, and the preset flip-flop 32 is reset by the reset signal reset_. Is set to 1 ".

As a result, the flip-flops 31 to 33 are set to "10".

Accordingly, since the first and second reset flip-flops 31 and 33 are initially reset, the value output through the output terminal q of the first reset flip-flop 31 becomes 0, so that the AND gate ( 34) outputs 0 regardless of the type force, and the value output through the inverted output terminal qn of the preset flip-flop 32 also becomes 0, so the AND gate 35 also outputs 0 regardless of the type force. do.

Therefore, the oragate 36 that receives the output values of the AND gates 34 and 35 also outputs zero.

After the rising edge of the reference clock clk inputted to the clock pulse input terminal cp, the first reset flip-flop 31 receives the frequency detection value detector_384fs through the input terminal d. Are sequentially shifted, and this shifted value is again sent to deflip-flops 32,33.

In this way, if all of the deflip-flops 31 to 33 have the same value, the AND gates 34 and 35 output "1", and the oragate 36 also outputs "1". do.

The output value "1" is fed back to the "confirm" signal of the counter unit 10 to stop counting.

That is, since the same frequency is output until a new frequency is input, the frequency detector 20 receives the output of its own feedback and outputs the feedback so that the counter unit 10 does not need to operate.

The confirm time for stopping the operation of the counter unit 10 may be set by adjusting the number of arrangements of the reset de-flip flop and the preset de-flip flop of the power consumption controller 30 according to system specifications.

As such, when the counter unit 10 does not operate with a constant constant value by the power consumption controller 30, there is no power consumption.

This operation reduces power consumption.

Therefore, the present invention has the effect of determining the frequency currently input in the chip itself, and eliminating unnecessary power consumption by not performing any further counting operation after the frequency determination is completed.

Claims (3)

A frequency detecting circuit comprising a counter unit for counting an oscillation signal currently input using a reference clock and a frequency detector for detecting a frequency by receiving a count value output from the counter unit, wherein the detected frequency output from the frequency detector is And a power consumption control unit for controlling the counter unit to stop the counting operation, and if the detection frequency is changed, controlling the counter unit to execute the counting operation to reduce power consumption. 2. The frequency detector of claim 1, wherein the frequency detector selects and outputs an AND gate that receives the frequency output from the counter, and an output of the AND gate when an initial state or a new frequency input is present. A multiplexer for receiving feedback and outputting, a de-flop flop for synchronizing the data output from the multiplexer with a reference clock, and an inverter for inverting the reference clock to provide the clock input terminal of the flip-flop. Frequency detector. The first reset deflip-flop of claim 1, wherein the power consumption controller shifts the detection frequency input to the data input terminal one by one in synchronization with a reference clock input to the clock input terminal and is initialized by a reset signal input from the outside. And shifting the output of the deflip-flop input to the data input terminal one by one in synchronization with the reference clock input to the clock input terminal, the preset flip-flop set by a reset signal input from the outside, and inputting the data to the data input terminal. A second reset flip-flop which is shifted one by one in synchronization with a reference clock input to a clock input terminal and initialized by a reset signal input from the outside; A first end gate for ANDing the value output through the output terminal, and all of the deflip-flops A low power, comprising: a second and gate for ANDing values output through all output stages; and an oragate for outputting signals for determining a counting operation by outputting the outputs of the first and second AND gates Frequency detector.

Images