KR100269335B1 - Method of manufacturing semiconductor material - Google Patents
Method of manufacturing semiconductor material Download PDFInfo
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- KR100269335B1 KR100269335B1 KR1019980036993A KR19980036993A KR100269335B1 KR 100269335 B1 KR100269335 B1 KR 100269335B1 KR 1019980036993 A KR1019980036993 A KR 1019980036993A KR 19980036993 A KR19980036993 A KR 19980036993A KR 100269335 B1 KR100269335 B1 KR 100269335B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000000463 material Substances 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 48
- 238000005530 etching Methods 0.000 claims abstract description 13
- 238000002955 isolation Methods 0.000 claims abstract description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000001301 oxygen Substances 0.000 claims abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims description 22
- 238000005498 polishing Methods 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 11
- 239000012298 atmosphere Substances 0.000 claims description 7
- 239000004642 Polyimide Substances 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims 4
- 229910052757 nitrogen Inorganic materials 0.000 claims 2
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 2
- 238000006073 displacement reaction Methods 0.000 description 13
- 239000012535 impurity Substances 0.000 description 6
- 239000000969 carrier Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000011856 silicon-based particle Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 웨이퍼를 깊이 식각하는 식각공정을 포함하여 제조된 반도체 소자의 누설전류 특성을 개선하기 위한 반도체 소자의 제조방법에 관한 것이다. 셀로우 트렌치 아이솔레이션(STI) 공정을 포함하여 웨이퍼 상에 반도체 소자를 완료한다. 웨이퍼 뒷면을 연마한다. 그 뒷면이 연마된 웨이퍼를 산소 또는 질소 분위기, 130℃에서 72시간 동안 열처리한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device for improving leakage current characteristics of a manufactured semiconductor device including an etching process of deeply etching a wafer. Complete the semiconductor device on the wafer, including a shallow trench isolation (STI) process. Polish the back side of the wafer. The wafer whose back side is polished is heat-treated at 130 ° C. for 72 hours in an oxygen or nitrogen atmosphere.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 웨이퍼를 깊이 식각하는 식각공정을 포함하여 제조된 반도체 소자의 누설전류 특성을 개선하기 위한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device for improving leakage current characteristics of a manufactured semiconductor device including an etching process of deeply etching a wafer.
반도체 소자를 제조하는데 있어 신뢰도를 유지한 채 집적도를 향상시키는 것은 중요하다. 반도체 소자의 집적도 향상을 위해 여러 가지 제조 기술이 도입되고 있으며, 그 중, 대표적인 것은 셀로우 트렌치 아이솔레이션(Shallow Trench Isolation; STI) 공정이다. 셀로우 트렌치 아이솔레이션은 웨이퍼 내에 깊은 트렌치를 건식식각으로 형성한 후 이 트렌치에 절연물을 채워넣어 소자분리막을 형성하는 기술로, 선택 산화(LOCal Oxidation of Silicon) 방식보다 활성영역의 크기를 넓힐 수 있고, 소자 간 분리를 신뢰도 높게 할 수 있다는 장점이 있다. 그러나, 셀로우 트렌치 아이솔레이션을 위한 식각공정 시, 웨이퍼 내에 변위(dislocation)가 발생하여 반도체 소자의 누설전류를 증가시키게 된다는 단점이 있다.In manufacturing a semiconductor device, it is important to improve the degree of integration while maintaining reliability. Various fabrication techniques have been introduced to improve the degree of integration of semiconductor devices, and a representative one is a shallow trench isolation (STI) process. Crow trench isolation is a technique for forming a device isolation film by forming a deep trench in a wafer by dry etching and then filling an insulating material in the trench, which can increase the size of the active region rather than the LOCal Oxidation of Silicon method. The advantage is that the isolation between the devices can be made high. However, there is a disadvantage in that during the etching process for the shallow trench isolation, a displacement occurs in the wafer to increase the leakage current of the semiconductor device.
이를 상세하게 설명하면, 반도체 소자 제조를 위한 웨이퍼는 예컨대 초크라스키(Czochralski) 성장 방식으로 실리콘을 성장시켜 제조하는데, 이때 성장 과정에서 산소(O2) 입자가 유입되어 웨이퍼 내에 이산화실리콘(SiO2)과 같은 불순물 입자가 국부적으로 존재하게 된다. 이러한 존재는 반도체 소자의 기능을 향상시키기 위해 사용되기도 하지만, 한편 여러 가지 문제를 발생시키는 원인이 되기도 한다.In detail, a wafer for manufacturing a semiconductor device is manufactured by growing silicon, for example, by a Czochralski growth method, wherein oxygen (O 2 ) particles are introduced during the growth process, and silicon dioxide (SiO 2 ) is introduced into the wafer. Impurity particles such as) will be present locally. Such a presence may be used to improve the function of the semiconductor device, but may also cause various problems.
즉, 셀로우 트렌치 아이솔레이션을 위해 웨이퍼에 깊은 트렌치를 형성할 경우, 언급한 국부적인 존재가 있는 영역에 까지 식각이 진행되어 트렌치와 인접하는 웨이퍼 내에 변위를 발생시킨다. 이러한 변위는 그 자체적인 존재만으로는 반도체 소자의 신뢰도에 크게 영향을 미치지 않는다. 그러나, 웨이퍼 내에 반도체 소자를 구성하는 불순물 확산영역을 형성한 후 소자를 동작시킬 경우, 이러한 불순물 확산영역 내에 주입되어 있는 불순물로부터 발생하는 캐리어(carrier)들은 평이하게 결합된 실리콘 입자들의 결합 부분에서 보다 상기와 같은 변위 부분에 더 빨리 유입되어 결과적으로 원하지 않는 전류 통로를 만들게 되고, 이러한 전류 통로에 의해 반도체 소자의 누설전류는 증가하게 된다.In other words, when a deep trench is formed in the wafer for shallow trench isolation, etching proceeds to the region where the local presence is mentioned, causing displacement in the wafer adjacent to the trench. This displacement alone does not significantly affect the reliability of the semiconductor device. However, when the device is operated after the impurity diffusion region constituting the semiconductor device is formed in the wafer, carriers generated from impurities implanted in the impurity diffusion region are more likely to be formed than in the bonding portion of the silicon particles which are smoothly bonded. The faster the flow in the displacement portion, the more likely to create an unwanted current path, which leads to an increase in the leakage current of the semiconductor device.
언급한 바와 같이, 변위에 의해 발생하는 누설전류는, 예컨대 다이나믹 랜덤 억세스 메모리 (Dynamic Random Access Memory; DRAM) 소자의 경우 불량 비트(fail bit)를 유발시키게 되고, 다른 소자, 예컨대 스태틱 랜덤 억세스 메모리(Static Random Access Memory; SRAM) 소자의 경우 대기 상태(Stand-by state)와 활성 상태(Active stast)에서 발생하는 누설전류의 레벨을 더욱 증가시킨다.As mentioned, leakage current caused by displacement causes, for example, a dynamic bit in the case of a dynamic random access memory (DRAM) device, and another device, such as a static random access memory (DRAM). In the case of static random access memory (SRAM) devices, the leakage currents in the stand-by state and the active state are further increased.
본 발명의 목적은 웨이퍼를 깊이 식각하는 식각공정을 포함하여 제조된 반도체 소자의 누설전류 특성을 개선할 수 있는 방법을 제공한다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for improving leakage current characteristics of a manufactured semiconductor device, including an etching process of deeply etching a wafer.
도 1은 반도체 소자의 누설전류 특성을 개선하기 위한 본 발명의 일 실시예에 의한 반도체 소자 제조방법의 공정단계를 보여주는 공정흐름도이다.1 is a process flow diagram showing the process steps of the semiconductor device manufacturing method according to an embodiment of the present invention for improving the leakage current characteristics of the semiconductor device.
도 2는 반도체 소자의 누설전류 특성을 개선하기 위한 본 발명의 다른 실시예에 의한 반도체 소자 제조방법의 공정단계를 보여주는 공정흐름도이다.2 is a process flow diagram showing the process steps of the semiconductor device manufacturing method according to another embodiment of the present invention for improving the leakage current characteristics of the semiconductor device.
도 3의 (a),(b) 및 (c)는 각각 웨이퍼 뒷면을 연마하기 전과, 웨이퍼 뒷면을 연마한 후와, 웨이퍼 뒷면을 연마한 후 열처리까지 행했을 경우의 누설전류의 특성을 보여주는 그래프들이다.3 (a), 3 (b) and 3 (c) are graphs showing the characteristics of the leakage current before polishing the back side of the wafer, after polishing the back side of the wafer, and performing heat treatment after polishing the back side of the wafer, respectively. admit.
도 4의 (a) 및 (b)는 각각 웨이퍼 뒷면을 연마하지 않았을 때와, 웨이퍼 뒷면을 연마한 후 열처리까지 행한 본 발명의 일 실시예의 경우의 불량 비트의 분포를 도시한 평면도이다.4 (a) and 4 (b) are plan views showing the distribution of defective bits when the back side of the wafer is not polished, and in the case of one embodiment of the present invention, which is performed until the heat treatment after the back side of the wafer is polished.
도 5는 웨이퍼 뒷면을 연마하지 않았을 때와, 웨이퍼 뒷면을 연마한 후 열처리까지 행한 본 발명의 경우의 C 모드에서의 불량 비트의 수를 나타내는 그래프이다.Fig. 5 is a graph showing the number of defective bits in the C mode when the back surface of the wafer is not polished and in the case of the present invention performed after the back surface of the wafer is polished.
상기 목적을 달성하기 위한, 본 발명에 의한 반도체 소자의 제조방법은, 반도체 소자 제조를 위한 제조 라인에서 셀로우 트렌치 아이솔레이션 공정을 포함하여 웨이퍼 상에 최종적인 금속 배선까지 형성한 후, 산소 분위기에서 결과물 기판을 열처리하고, 이어서 반도체 소자를 보호하기 위한 폴리이미드 공정을 행하는 단계와, 웨이퍼 뒷면을 연마하는 단계와, 그 뒷면이 연마된 웨이퍼를 산소 또는 질소 분위기, 130℃에서, 72시간 동안 열처리하는 단계를 포함하는 것을 특징으로 한다. 바람직하게, 상기 반도체 소자는 다이나믹 랜덤 억세스 메모리 소자이다.In order to achieve the above object, the method of manufacturing a semiconductor device according to the present invention includes a trench trench isolation process in a manufacturing line for manufacturing a semiconductor device, and then forms a final metal wiring on a wafer, and then results in an oxygen atmosphere. Heat treating the substrate, and then performing a polyimide process to protect the semiconductor device, polishing the back side of the wafer, and heat treating the back side polished wafer at an oxygen or nitrogen atmosphere at 130 ° C. for 72 hours. Characterized in that it comprises a. Preferably, the semiconductor device is a dynamic random access memory device.
따라서, 본 발명에 의하면, 반도체 소자 제조 후 웨이퍼 뒷면 연마과 열처리 공정을 진행하여 변위 내에 유입되어 있던 캐리어를 웨이퍼 하단부로 제거함으로써 반도체 소자의 누설전류를 감소시킬 수 있다.Therefore, according to the present invention, the leakage current of the semiconductor device can be reduced by removing the carrier introduced into the displacement to the lower end of the wafer by performing a wafer back polishing and heat treatment after fabricating the semiconductor device.
이하, 첨부한 도면을 참조하여, 본 발명에 의한 반도체 소자의 제조방법을 더욱 상세하게 설명하고자 한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in more detail with reference to the accompanying drawings.
도 1은 반도체 소자의 누설전류 특성을 개선하기 위한 본 발명의 일 실시예에 의한 반도체 소자 제조방법의 공정단계를 보여주는 공정흐름도이다.1 is a process flow diagram showing the process steps of the semiconductor device manufacturing method according to an embodiment of the present invention for improving the leakage current characteristics of the semiconductor device.
본 발명의 일 실시예에 의한 제조방법은, 웨이퍼 상에 최종적인 금속 배선까지 형성하는 제조공정 완료 단계 (Fab Out 단계)와, 상기 금속 배선을 보호하기 위한 폴리이미드 공정을 진행하는 단계와, 상기 웨이퍼의 뒷면을 연마하는 단계와, 산소(O2) 또는 질소(N2) 분위기에서 열처리하는 단계 (Anneal 단계)로 진행한다.According to an embodiment of the present invention, there is provided a manufacturing method of forming a final metal wiring on a wafer (Fab Out step), a polyimide process for protecting the metal wiring, and The back surface of the wafer is polished, and heat treatment is performed in an oxygen (O 2 ) or nitrogen (N 2 ) atmosphere (Anneal step).
웨이퍼 상에 최종적인 금속 배선까지 형성하는 상기 제조 공정은 일반적인 반도체 소자 제조공정을 의미하며, 특히 웨이퍼를 깊이 식각하는 공정, 예컨대 셀로우 트렌치 아이솔레이션 공정을 포함하는 일반적인 DRAM 또는 SRAM 소자 제조 공정을 의미한다. 상기 열처리 단계는, 예컨대 130℃ 정도의 온도에서 72시간 정도 행한다. 이때, 상기 열처리는 튜브(tube) 또는 오븐(oven)을 사용하여 행할 수도 있고, 고속 열처리(Rapid Thermal Process) 방식 또는 진공 어닐(vacuum annealing) 등의 다양한 방법으로 행할 수 있다.The manufacturing process of forming a final metal wiring on a wafer refers to a general semiconductor device manufacturing process, and in particular, refers to a general DRAM or SRAM device manufacturing process including a deep etching process such as a shallow trench isolation process. . The heat treatment step is performed for about 72 hours at a temperature of, for example, about 130 ° C. In this case, the heat treatment may be performed using a tube or an oven, or may be performed by various methods such as a rapid thermal process method or a vacuum annealing method.
변위 내에 응집되어 존재하는 캐리어에 의해 누설전류가 증가되는 문제점을 해결하기 위해, 본 발명의 일 실시예에서는, 웨이퍼 뒷면을 연마한 후 열처리하는 단계를 추가하였다.In order to solve the problem that the leakage current is increased by the carriers aggregated in the displacement, in one embodiment of the present invention, a step of grinding the back surface of the wafer and then performing a heat treatment is added.
도 3의 (a),(b) 및 (c)를 참조하면, 소자의 누설전류는 웨이퍼 뒷면을 연마했을 때(b)가 연마하지 않았을 경우(a)보다 작고, 웨이퍼 뒷면을 연마한 후 열처리까지 했을 때(c)가 단순히 웨이퍼 뒷면을 연마한 경우(b)보다 작음을 알 수 있다.Referring to (a), (b) and (c) of FIG. 3, the leakage current of the device is smaller than that when (b) is not polished when the back side of the wafer is polished (a), and heat treatment after polishing the back side of the wafer. As can be seen that (c) is smaller than the case of simply polishing the back side of the wafer (b).
변위 내에 존재하여 전류통로가 되는 캐리어들은 웨이퍼 뒷면 연마시 많은 부분이 웨이퍼 뒷면으로 이동하게 되며, 이 후, 열처리까지 행하게 되면 더 많은 부분이 웨이퍼 뒷면으로 이동하게 된다 (게더링(gathering effect) 효과). 따라서, 상기 변위 내에 응집되어 존재하던 캐리어들이 거의 없어지게 되어 누설전류의 통로가 없어지게 되므로 결과적으로 소자의 누설전류 특성을 향상시킨다.Carriers which are present in the displacement and become current paths move a large portion to the back side of the wafer during polishing of the back side of the wafer, and then, when heat treatment is performed, more parts move to the back side of the wafer (gathering effect). Therefore, carriers that have been agglomerated in the displacement are almost eliminated, so that the passage of the leakage current is lost, resulting in improved leakage current characteristics of the device.
바람직하게는, 웨이퍼 내에 형성되어 있는 변위 자체를 웨이퍼 뒷면으로 이동시켜 식각부위에 발생하던 변위와 같은 손상을 근본적으로 없애는 것이 마땅하나, 이를 위해서는 700℃ 이상에서 고온에서 열처리를 행해야하는데, 이 경우, 웨이퍼 표면 근방에 형성되어 있는 불순물 확산영역의 불순물 프로파일(profile) 등을 변형시켜 결과적으로 반도체 소자의 기능을 저하시키게 된다. 본 발명의 일 실시예에서는 130℃ 정도의 저온에서 열처리를 행하여 변위 내에 존재하던 캐리어만을 없애므로 언급한 바와 같은 반도체 소자의 기능 저하 문제는 발생하지 않는다.Preferably, the displacement itself formed in the wafer is moved to the back side of the wafer to fundamentally eliminate damage such as displacement occurring in the etching region, but for this, heat treatment must be performed at a high temperature of 700 ° C. or higher. The impurity profile of the impurity diffusion region formed in the vicinity of the wafer surface is modified, and as a result, the function of the semiconductor device is degraded. In one embodiment of the present invention, the heat treatment is performed at a low temperature of about 130 ° C. to remove only the carriers that existed in the displacement.
도 2는 반도체 소자의 누설전류 특성을 개선하기 위한 본 발명의 다른 실시예에 의한 반도체 소자 제조방법의 공정단계를 보여주는 공정흐름도로서, 최종적인 금속 배선까지 형성하는 제조 공정 후, 산소(O2) 분위기에서 1차적으로 웨이퍼를 열처리하는 단계를 추가한다는 점이 상기 일 실시예와 다르다. 이때, 1차적으로 웨이퍼를 열처리하는 단계는 금속 배선 내의 뭉쳐짐(aggregation)을 방지하여 금속 배선의 신뢰도를 높이기 위하여 행한다.2 is a process flow diagram showing the process steps of the semiconductor device manufacturing method according to another embodiment of the present invention for improving the leakage current characteristics of the semiconductor device, after the manufacturing process to form the final metal wiring, oxygen (O 2 ) It differs from the above embodiment in that it adds a step of heat-treating the wafer primarily in the atmosphere. At this time, the heat treatment of the wafer is performed in order to prevent aggregation of the metal wirings and to increase the reliability of the metal wirings.
도 3의 (a),(b) 및 (c)는 각각 웨이퍼 뒷면을 연마하기 전과, 웨이퍼 뒷면을 연마한 후와, 웨이퍼 뒷면을 연마한 후 열처리까지 행했을 경우의 PN 정션에서의 누설전류의 특성을 보여주는 그래프들이다.3 (a), 3 (b) and 3 (c) show the leakage currents at the PN junction when the back surface of the wafer is polished, the back surface of the wafer is polished, and the back surface of the wafer is polished until the heat treatment. These graphs show characteristics.
도 3를 참조하면, 웨이퍼 뒷면을 연마하기 전의 PN 정션의 누설전류는 763.73㎂ 정도이고 (a의 경우), 웨이퍼 뒷면을 연마한 후의 PN 정션의 누설전류는 645.8㎂ 정도이며 (b의 경우), 웨이퍼 뒷면을 연마한 후 열처리까지 행한 후의 PN 정션의 누설전류는 296.65㎂ 정도임을 알 수 있다. 즉, 반도체 소자의 누설전류는 웨이퍼 뒷면을 연마하지 않았을 때보다 연마한 후 더 작아지며, 웨이퍼 뒷면을 단순히 연마했을 때 보다 연마한 후 열처리까지 행했을 때 가장 작다.Referring to FIG. 3, the leakage current of the PN junction before polishing the back side of the wafer is about 763.73 ((for a), and the leakage current of the PN junction after polishing the back of the wafer is about 645.8 ㎂ (for b). It can be seen that the leakage current of the PN junction after polishing the back side of the wafer and performing heat treatment is about 296.65 mA. In other words, the leakage current of the semiconductor element is smaller after grinding than when the back side of the wafer is not polished, and is smaller than when the back side of the wafer is simply polished and then subjected to heat treatment.
도 4의 (a) 및 (b)는 각각 웨이퍼 뒷면을 연마하지 않았을 때와, 웨이퍼 뒷면을 연마한 후 열처리까지 행한 본 발명의 일 실시예의 경우의 불량 비트의 분포를 도시한 평면도이다.4 (a) and 4 (b) are plan views showing the distribution of defective bits when the back side of the wafer is not polished, and in the case of one embodiment of the present invention, which is performed until the heat treatment after the back side of the wafer is polished.
도 4의 (a)는 웨이퍼 뒷면을 연마하지 않은 상태에서 실 런(run)에 적용하여 테스트(test)한 결과이고, 도 4의 (b)는 웨이퍼 뒷면을 연마한 후 열처리한 상태에서 실 런에 적용하여 테스트한 결과이다. 웨이퍼 뒷면을 연마한 후 열처리한 경우 (b의 경우) 웨이퍼 뒷면을 연마하지 않은 경우 (a의 경우) 보다 싱글 비트(single bit)의 불량이 줄어듬을 확인할 수 있다.Figure 4 (a) is a test result by applying the test (run) in the state in which the wafer back surface is not polished, Figure 4 (b) is a seal run in the heat treatment state after polishing the back surface of the wafer The test result is applied to. In the case of heat treatment after polishing the back side of the wafer (b), the defect of the single bit is reduced compared to the case of not polishing the back side of the wafer (a).
도 5는 웨이퍼 뒷면을 연마하지 않았을 때와, 웨이퍼 뒷면을 연마한 후 열처리까지 행한 본 발명의 경우의 C 모드에서의 불량 비트의 수를 나타내는 그래프로서, 256M DRAM 제조 공정에 본 발명을 적용한 후 리프레쉬 데이타(refresh data)를 나타내고 있다.Fig. 5 is a graph showing the number of bad bits in the C mode when the back side of the wafer was not polished and after the back side of the wafer was polished and then subjected to heat treatment. The data is shown as refresh data.
도 5의 그래프를 참조하면, 본 발명을 적용한 경우, 본 발명을 적용하지 않은 경우 (종래)보다 C-모드에서 리프레쉬 불량 비트의 수가 급격하게 감소하는 경향이 있음을 확인할 수 있다. 보통 C-모드에서 PN 정션의 누설 전류가 있을 경우 불량 비트가 나타나는 것으로 알려져 있다.Referring to the graph of FIG. 5, it can be seen that when the present invention is applied, the number of refresh bad bits tends to decrease sharply in the C-mode than when the present invention is not applied. Normally, it is known that a bad bit appears when there is a leakage current of a PN junction in C-mode.
본 발명은 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당 분야에서 통상의 지식을 가진 자에 의하여 가능함은 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by one of ordinary skill in the art within the technical idea of the present invention.
본 발명에 의한 반도체 소자의 제조방법에 의하면, 웨이퍼를 깊이 식각하는 공정을 포함하는 반도체 소자 제조 후, 웨이퍼 뒷면 연마과 열처리 공정을 진행하여 변위 내에 유입되어 있던 캐리어를 웨이퍼 하단부로 제거함으로써 반도체 소자의 누설전류를 감소시킬 수 있다.According to the method of manufacturing a semiconductor device according to the present invention, after fabricating a semiconductor device including a step of deeply etching a wafer, polishing of the wafer backside and heat treatment are performed to remove the carrier introduced into the displacement to the lower end of the wafer, thereby leaking the semiconductor device. Can reduce the current.
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