KR100269207B1 - A single transistor type ferroelectric random access memory and an operating method thereof - Google Patents

Abstract

PURPOSE: A single transistor ferroelectric random access memory having common word line and method for operating the same are provided to make an ideal common word line by interconnecting a gate and a source of a single transistor through a word line in each memory cell. CONSTITUTION: A ferroelectric random access memory includes a single transistor and a ferroelectric capacitor in each memory cell of a substrate. An upper electrode(103) of the ferroelectric capacitor is arranged on a channel of the single transistor in order to be functioned as a gate of the single transistor. The upper electrode is connected to a source of the single transistor thereby making a common word line(102). A bit line(101) is formed by connecting a drain of the single transistor to the upper electrode. A plate line corresponds to the bit line.

Description

Single Transistor Ferroelectric Random Access Memory with Common Wordline and Its Operation Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric random access memory, and more particularly, to a single transistor ferroelectric random access memory having non-destructive read and each memory cell having a common word line consisting of one transistor and a ferroelectric capacitor, and a method of operating the same. .

Ferroelectric memories, which are non-destructive read out (NDRO) and each memory cell consists of a single transistor, have been considered virtually impossible in the form of random access memory (RAM). To overcome this problem, the structure and operation method of NDRO 1T-1CC TFT-FRAM and NDRO 1T-1C FRAM are described as follows.

1 is a schematic vertical cross-sectional view of a ferroelectric random access memory of the conventional 1T-1C structure. As shown, the 1T-1C structure connects a CMOS transistor (10, 14b, 15, 16, 17) and ferroelectric capacitors (11, 12, 13) to an electrode (18b) to connect one cell. Forming. That is, the insulating layer 14b is formed on the channel 19 of the silicon substrate 10 on which the source 15 and the drain 17 are formed by impurity doping, and the gate 16 is formed in the insulating layer 14b. The formed CMOS transistor and the lower electrode 11, the ferroelectric layer 12, and the upper electrode 13 have a structure in which the ferroelectric capacitors 11, 12, 13, which are sequentially stacked, are connected. This is called a 1T-1C structure, where 1T-1C becomes one cell. Here, an insulating layer is opened on the top of the source 15 and the drain 17 of the CMOS transistor to form a source electrode 18a and a drain electrode 18b. A ferroelectric capacitor is fabricated on the CMOS substrate 10 and surrounded by a periphery. The electrode 18c is connected to the transistor of the upper portion of the transistor through an opening of the insulating layer.

2 is a schematic vertical cross-sectional view of a ferroelectric random access memory of the conventional 1T-CC structure. As shown, a thin film transistor ferroelectric random access memory having a 1 transistor-common capacitor (1T-CC) structure has a structure in which thin film transistors are integrated on a common ferroelectric capacitor. That is, the lower electrode 1 of the ferroelectric capacitor is first deposited and used as a common electrode. The ferroelectric material 2 is deposited on the common lower electrode 1 and used as the common ferroelectric layer 2. At this time, there is no limitation of the ferroelectric layer deposition temperature for the semiconductor. Next, the upper electrode 3 is deposited for each memory cell to form each memory cell. Then, an insulator 4a is deposited on the upper electrode 3, but leaves a window in which the upper electrode 3 and the thin film transistor are in contact. A thin film transistor (TFT) is formed thereon.

As described above, the conventional ferroelectric random access memory of the 1T-1C structure or the ferroelectric random access memory of the 1T-CC structure have a word line, a bit line, and a plate line in a layer structure. In addition, a sensing bitline is added to keep the four lines in use.

The present invention has been made to solve the above problems, and each memory cell is composed of a single transistor and a ferroelectric capacitor, and the gate and the source of the single transistors are connected by a word line to write or read using the word line. It is an object of the present invention to provide a single transistor ferroelectric random access memory having an ideal common word line and a method of operating the same.

1 is a schematic vertical cross-sectional view of a ferroelectric random access memory of a conventional 1T-1C structure;

2 is a schematic vertical cross-sectional view of a ferroelectric random access memory of the conventional 1T-CC structure;

3 is an excerpt vertical cross-sectional view of a single transistor ferroelectric random access memory having a common word line in accordance with the present invention;

4 is a schematic plan view of a single transistor ferroelectric random access memory having a common wordline of FIG.

5A and 5B illustrate a " write " operation of a single transistor ferroelectric random access memory having a common wordline of FIG.

6A and 6B are diagrams for describing a "read" operation of a single transistor ferroelectric random access memory having a common word line of FIG.

<Explanation of symbols for the main parts of the drawings>

101.Bit line (B)

102. Common Word Line (W)

103. Top electrode of ferroelectric capacitor

104. Ferroelectric

105. Diffusion layer

106. Well

107. Conductive diffusion line (plate line)

108. Substrate

109. Insulation layer

In order to achieve the above object, a single transistor ferroelectric random access memory having a common word line according to the present invention is a ferroelectric random access memory having a single transistor and a ferroelectric capacitor provided in a substrate and each memory cell on the substrate. The upper electrode of the capacitor is disposed above the channel of the single transistor to serve as a gate of the single transistor, and the upper electrode and the source of the single transistor are connected together to form a common word line, and the drain of the single transistor is connected. By forming a bit line, a plate line is formed to correspond to the bit line.

In the present invention, an insulating layer is formed on the bottom surface of the substrate to float the substrate, and the plate line is embedded in the substrate to correspond to the bit line, and the plate line is the same as the source and drain of the single transistor. Doped with unique impurities, wherein the plate line is doped with n ⁺ , the channel of the single transistor is formed as a p-well, or the plate line is doped with p ⁺ , and the channel of the single transistor is n-well It is preferable that it is formed.

In addition, in order to achieve the above object, a method of operating a single transistor ferroelectric random access memory having a common word line according to the present invention includes a single transistor and a ferroelectric capacitor in a substrate and each memory cell on the substrate, wherein the ferroelectric capacitor An upper electrode of the transistor is disposed on a channel of the single transistor to serve as a gate of the single transistor, the upper electrode and the source of the single transistor are connected together to form a common word line, and the drain of the single transistor is connected to A method of operating a single transistor ferroelectric random access memory having a common word line forming a bit line and having a plate line corresponding to the bit line, the method comprising: (a) the common word line as a reference for addressing; word By applying a potential difference between the phosphorus and the plate line writing step of writing information; And (b) reading information through a sense amplifier connected to the bit line by a voltage applied to the common word line.

Hereinafter, a single transistor ferroelectric random access memory having a common word line according to the present invention will be described in detail with reference to the drawings.

The single transistor ferroelectric random access memory having a common word line according to the present invention is a non-destructive read type (NDRO type), which is the most ideal form of operation in FRAM, and each memory cell is composed of a single transistor and a ferroelectric capacitor. At this time, the gate and the source of the transistor of each cell are connected to the word line as a reference for addressing, the information is written into the word line and the plate, and the word line and the sense line Read with). A memory structure for implementing this is shown in FIGS. 3 and 4.

3 is an excerpt vertical cross-sectional view of a single transistor ferroelectric random access memory having a common word line according to the present invention, and FIG. 4 is a schematic plan view of a single transistor ferroelectric random access memory having a common word line of FIG. As shown, a single transistor ferroelectric random access memory having a common wordline in accordance with the present invention is a common word line (102), plate line (107), bit line (101) ) And all of the cells are separated by the insulating plate 109. A single transistor constituting each memory cell connects the gate 103 (corresponding to the upper electrode of the ferroelectric capacitor) and the source 105 to form a word line 102. The drains of the single transistors are connected to each other to form a bit line 101, but are connected to a sensor amplifier (not shown, see FIGS. 6A and 6B). The plate line 107 is composed of a highly doped layer of impurities, ^and is selected from n ⁺ and p ⁺ . If plate line 107 is n ⁺ type well 106 and substrate 108 are p type and diffusion layer 105 is n ⁺ type. If plate line 107 is of p ⁺ type, well 106 and substrate 108 are of n type and diffusion layer 105 is of p ⁺ type. In the embodiment of the figure an n ⁺ type plate line, ie a p-well, is shown by way of example.

The operation method of the single transistor ferroelectric random access memory having the common word line configured as described above is as follows.

First, FIGS. 5A and 5B are diagrams for describing a " write " operation of a single transistor ferroelectric random access memory having a common word line of FIG. As shown, when writing to a memory cell, word line 102 is first taken and addressed and a potential difference is applied between word line 102 and plate line 107. This potential difference determines the charge polarity induced in the p-well. As shown in FIG. 5A, when the voltage Vw of the word line 102 is smaller than the voltage Vb of the plate line 107, between the diffusion layers of the cell or between the word line 102 and the bit line 101. A positive charge is induced in the p-well, which is balanced by the domain of the ferroelectric 104 and becomes a bound charge so that it does not disappear. Assign this as recorded as "0". As shown in FIG. 5B, when the voltage Vw of the word line 102 is greater than the voltage Vb of the plate line 107, negative charge is induced in the p-well of the corresponding cell. Assign this as recorded as "1". Of course, it can also be set as opposed to the above case.

6A and 6B are diagrams for explaining the " read " operation of the single transistor ferroelectric random access memory having the common word line of FIG. As shown, when reading the recorded information, the word line 102 is first selected and addressed, the read voltage Vr is applied, and the bit line 101 to which the sensor amplifier 110 is connected is selected to detect the memory state. can do. That is, as shown in FIG. 6A, a cell written as "0" is detected as "off", and as shown in FIG. 6B, a cell recorded as "1" is detected as "on". .

As described above, the single transistor ferroelectric random access memory having a common word line according to the present invention is non-destructive read type (NDRO type) and each memory cell is composed of a single transistor and a ferroelectric capacitor, but the gate and source of the transistor of each cell Is connected to a word line as a reference for addressing, information is written into the word line and a plate, and read into the word line and the sense amplifier line, so that one common word line is used. FRAM fabrication is easy because of the reference, and the NDRO method can be maintained, reducing the burden of fatigue, and the single transistor type increases the integration.

Claims (7)

In a ferroelectric random access memory having a substrate and a single transistor and a ferroelectric capacitor in each memory cell on the substrate, The upper electrode of the ferroelectric capacitor is disposed above the channel of the single transistor to serve as a gate of the single transistor, the upper electrode and the source of the single transistor are connected together to form a common word line, and the drain of the single transistor. And forming a bit line, and forming a plate line corresponding to the bit line, wherein the single transistor ferroelectric random access memory has a common word line. The method of claim 1, A single transistor ferroelectric random access memory having a common word line, wherein the substrate is floated by forming an insulating layer on a bottom surface of the substrate. The method according to claim 1 or 2, And the plate line is buried in the substrate so as to correspond to the bit line. The method of claim 3, And the plate line is doped with impurities of the same kind as the source and drain of the single transistor. The single transistor ferroelectric random access memory having a common word line. The method of claim 4, wherein Wherein the plate line is doped with n ⁺ , and the channel of the single transistor is formed of p-well. The method of claim 4, wherein Wherein the plate line is doped with p ⁺ , and the channel of the single transistor is formed of n-wells. A single transistor and a ferroelectric capacitor are provided in a substrate and each memory cell on the substrate, wherein the upper electrode of the ferroelectric capacitor is disposed on the channel of the single transistor so that the upper electrode serves as a gate of the single transistor, and the upper electrode and the single transistor. A source of the single transistor ferroelectric random access memory having a common word line connected together to form a common word line, and a drain of the single transistor connected to form a bit line, and a plate line formed to correspond to the bit line. In the method of operation, By using the common word line as a reference for addressing, (A) writing information by applying a potential difference between the common word line and the plate line; And (B) reading information through a sense amplifier connected to the bit line by a voltage applied to the common word line; And operating a single transistor ferroelectric random access memory having a common word line.