KR19990015720A - Nondestructive read thin film transistor ferroelectric memory and its driving method - Google Patents

Abstract

The present invention relates to a non-destructive read thin film transistor ferroelectric random access memory formed by forming a thin film transistor on a ferroelectric capacitor to enable a non-destructive read and a driving method thereof. In the non-destructive read thin film transistor ferroelectric random access memory according to the present invention, each memory cell has a structure in which a thin film transistor is mounted on a ferroelectric capacitor, and the lower electrode has a stripe shape or an independent structure, and the upper electrode has a first channel. The second channel of the addressing thin film transistor is disposed on the first channel, the source of each memory cell is connected to one side of the upper electrode and the lower electrode, and the gates of the memory cells are connected to the word line. The first channel of each memory cell to form plate lines, the drain of each memory cell to form bit lines, and the other side of the upper electrode of each memory cell to form sensing lines By selectively operating each cell, they can be selectively read and need to be restored. A reference line capable of addressing at the same time that can realize a non-destructive read method without using can be commonly used for writing and reading.

Description

Nondestructive read thin film transistor ferroelectric memory and its driving method

The present invention relates to a non-destructive read thin film transistor ferroelectric random access memory (NDRO TFT FRAM), and more particularly, to a non-destructive read thin film transistor ferroelectric random access memory formed by forming a thin film transistor on a ferroelectric capacitor to enable non-destructive reading and a driving method thereof. It is about.

The thin film transistor ferroelectric random access memory (TFT-FRAM) is a structure in which a ferroelectric capacitor is integrated into a conventional bulk Si transistor. The most notable difference is that conventional FRAMs have ferroelectric capacitors on top of transistors, while TFT-FRAMs have transistors on ferroelectric capacitors.

As shown in FIG. 1, a conventional TFT-FRAM structure is formed by connecting CMOS transistors 10, 14b, 15, 16, and 17 and ferroelectric capacitors 11, 12, and 13 to electrodes 18b. Cells are formed. That is, the insulating layer 14b is formed on the channel 19 of the silicon substrate 10 on which the source 15 and the drain 17 are formed by impurity doping, and the gate 16 is formed in the insulating layer 14b. The formed CMOS transistor and the lower electrode 11, the ferroelectric layer 12, and the upper electrode 13 have a structure in which the ferroelectric capacitors 11, 12, 13, which are sequentially stacked, are connected. This is called a 1T-1C structure, where 1T-1C becomes one cell. Here, an insulating layer is opened on the top of the source 15 and the drain 17 of the CMOS transistor to form a source electrode 18a and a drain electrode 18b. A ferroelectric capacitor is fabricated on the CMOS substrate 10 and surrounded by a periphery. The electrode 18c is connected to the transistor of the upper portion of the transistor through an opening of the insulating layer.

The most issue in the fabrication of such a 1T-1C structure is the choice of ferroelectric materials for the CMOS fabrication process. First, the ferroelectric deposition temperature should be less than 700 ° C. Second, the ferroelectric should not be affected by hydrogen in the passivation process. The reason for the CMOS fabrication process is that the ferroelectric capacitor fabrication itself is performed on the CMOS substrate.

In addition, in order to maintain a speed and cell array comparable to DRAM in the FRAM technology trend, first there should be no restoration of the FRAM and there is no standard for addressing. The lines to be written must be the same lines during the write or read process. This is because a simple design is required for the overall memory design. However, the conventional nondestructive readout type (NDRO) TFT-FRAM or 1Tr TFT-FRAM has been proposed in a way that is not required for restoration, but it does not completely solve the addressing problem in actual commercialization. There is no suggestion on how to write and read by selecting only a specific cell.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a non-destructive read thin film transistor ferroelectric random access memory and a method of driving the thin film transistor connected to the upper electrode and the lower electrode of the ferroelectric capacitor, respectively, which do not cause information corruption during reading. The purpose is to provide.

1 is a schematic cross-sectional view of a conventional thin film transistor ferroelectric random access memory,

2 is a vertical cross-sectional view of a non-destructive read thin film transistor ferroelectric random access memory according to the present invention;

3 is a schematic perspective plan view of the non-destructive read thin film transistor ferroelectric random access memory of FIG. 2;

4A through 5B are explanatory diagrams for describing an operation of the non-destructive read thin film transistor ferroelectric random access memory cell of FIG. 2.

4A and 4B are vertical cross-sectional views for explaining the operation during writing;

5A and 5B are vertical cross-sectional views for explaining the operation during reading;

6 is an equivalent circuit diagram of a cell array of the non-destructive read thin film transistor ferroelectric random access memory of FIG.

Explanation of symbols for main parts of the drawings

10, silicon substrate 11.Bottom electrode

12. Ferroelectric layer 13. Upper electrode

14b. Insulation layer 15. Source

16.gate 17.drain

18a. Source electrode 18b. Drain electrode

18c. Electrode 19. Channel

20. Insulator or dielectric 21. Bottom electrode of ferroelectric capacitor

22. Ferroelectric 23. Electrode contact plug

24. Bulkhead

25. Channel portion of the upper electrode pad (2nd gate for TFT)

25a. Source portion of the upper electrode pad

26a, 26b, 26c. Insulator 27. Channel of TFT

27a. Source of TFT 27b. TFT drain

28. Gate (Wordline) 29. Bitline

30. Sensing Line

In order to achieve the above object, a non-destructive read thin film transistor ferroelectric random access memory according to the present invention includes a substrate; First electrodes formed of pads on the substrate; A ferroelectric layer deposited over the first electrodes and the substrate to a predetermined thickness or more; Second electrode pads having a first channel formed on the ferroelectric layer to intersect the first electrodes; And thin film transistors on the ferroelectric layer whose sources are simultaneously connected to one side of the second electrode pads and the first electrodes and for addressing the ferroelectric capacitors, respectively.

In the present invention, it is preferable that the first electrodes correspond one-to-one to the thin film transistor of each memory cell, and the thickness of the ferroelectric layer is a minimum thickness capable of forming polarization, and the second electrode pad. One side of the field and the first electrodes are each connected by a plug penetrating the ferroelectric layer, and a partition wall is further formed around the plug to prevent a reaction with the ferroelectric layer, and the first channel is the first channel. It is formed in the center portion of the two electrode pads to form a plate line, the drains of the thin film transistors are connected to the second electrode pads and the first electrode lines at the same time, the thin film transistors source and drain; A second channel formed between the source and the drain in the same layer as the source and the drain; And a gate stacked on the second channel with an insulating layer interposed therebetween, wherein the gates are connected to each other to form word lines on a stripe, and the first channels of the plate lines are formed in the thin film transistor. The bit lines are formed to correspond to each other with an insulating layer having a predetermined thickness and an insulating layer interposed therebetween, and the bit lines are formed on a stripe in a direction crossing the word line with the insulating layer interposed therebetween. And the sensing lines are formed to be connected to the drain and form sensing lines on a stripe in a direction crossing the bit lines with an insulating layer interposed therebetween, wherein the sensing lines are formed on the other side of the second electrode pads. And a stripe layer formed on the stripe with an insulating layer interposed therebetween. It is preferable to form sensing lines.

In addition, in order to achieve the above object, a method of driving a non-destructive read thin film transistor ferroelectric random access memory according to the present invention includes: first electrodes formed on a substrate; A ferroelectric layer deposited over the first electrodes and the substrate to a predetermined thickness or more; Second electrode pads having a first channel for forming ferroelectric capacitors corresponding to each memory cell on the ferroelectric layer corresponding to the first electrodes; And thin film transistors on the ferroelectric layer of each of the memory cells for addressing ferroelectric capacitors of the respective memory cells, having gates on top of the second channel, source and drain, and the second channel. A source of each memory cell is connected to one side of the second electrode pad and the first electrode, and gates of the memory cells are connected to form word lines, and the first channels of the memory cells are connected to each other to form a plate. A non-destructive read thin film transistor ferroelectric random access memory having lines formed therebetween, connecting bit lines to drains of the memory cells, and connecting the other side of the second electrode pad of the memory cells to form sensing lines. In the driving method, a voltage signal to the plate line and the bit line Applying writing step of polarizing the ferroelectric layer of the memory cell addressed; And applying a predetermined voltage signal to the word line and the bit line, respectively, through the bit line through the sensing line according to whether or not conduction is performed according to the polarity of the bond charge bound to the first channel of the addressed memory cell. And a reading step of sensing current due to the voltage signal to be detected by the polarization state of the ferroelectric layer.

In the present invention, the writing step may determine the polarization direction of the ferroelectric layer by the potential difference between the voltage signal applied to the plate line and the bit line, respectively, wherein the bit larger than the voltage applied to the plate line. 1 is applied to the line, and a voltage less than the voltage applied to the plate line is applied to the bit line to record 0. When the read of 0 is performed in the reading step, the first channel is bound. If it detects OFF because it is not energized by the charge, and reads what is written as 1, it is energized by the charge bound to the first channel and sensed as ON, and the standard for addressing a memory cell to be written or read in the write and read steps. It is preferable to set the voltage to a voltage applied to the bit line.

A non-destructive read ferroelectric random access memory according to the present invention, a manufacturing method thereof, and a driving method thereof will be described below with reference to the accompanying drawings.

The non-destructive read thin film transistor ferroelectric random access memory according to the present invention is a 1T-CC TFT-FRAM having a 1T-CC (1 transistor-common capacitor) structure in which thin film transistors, as disclosed in the prior art or in the prior art, are integrated on a common ferroelectric capacitor. A non-destructive read (NDRO) TFT-FRAM and a 1Tr TFT-FRAM have a complex structure, and the driving method can be nondestructive read (NDRO). Each cell structure of the non-destructive read thin film transistor ferroelectric random access memory according to the present invention will be described with reference to FIG.

First, the ferroelectric capacitor 22 and the lower electrode 21 (first electrode) coated on the lower electrode 21, the lower electrode 21, and the insulator 20 on the insulator or the dielectric 20 as a substrate. Ferroelectric capacitors are formed with upper electrode pads 25, 26a, 25b on corresponding stripes. Here, the lower electrode 21 is formed in a separate form for each memory cell, and the channel portion 25 (hereinafter referred to as the upper electrode channel (first channel)) in the upper electrode pads 25, 26a and 25b. It serves as a substantial upper electrode of this ferroelectric capacitor. In addition, the upper electrode pad 25b and the lower electrode 21 are electrically connected by a plug 23 penetrating through the ferroelectric layer 22. The plug 23 is surrounded by a partition wall 24 to prevent reaction with the ferroelectric layer 22 during manufacture.

Next, a thin film transistor is formed over the ferroelectric capacitor with the insulating layer 26a interposed therebetween. That is, the insulating layer 26a is laminated on the upper electrode pads 25, 26a and 25b and the ferroelectric layer 22. The semiconductor layer which forms the channel 27, the source 27a, and the drain 27b of a thin film transistor is formed on this insulating layer 26a. Here, source 27a and drain 27b are doped with n ⁺ -or p ⁺ -type materials, respectively, and channel 27 is doped with p- or n-type material. In addition, the source 27a is connected to the upper electrode pad 25b of the ferroelectric capacitor. An insulating layer 26b is provided on the semiconductor layer and the insulating layer 26a including the channel, and the gate 28 is provided on the channel 27 with the insulating layer 26b interposed therebetween to form a thin film transistor. . The gate 28 is connected to each cell and has a word line 28 on the stripe.

The bit line 29 is formed in a stripe shape in a direction crossing the word line 28 on the insulating layer 26b. These bit lines 29 are connected through holes formed in the drain 27b and the insulating layer 26b of the thin film transistor of each memory cell. The insulating layer 26c is stacked on the insulating layer 26b and the bit line 29, and a sensing line 30 is formed on the stripe in parallel with the word line 28. The sensing line 30 is connected to the upper electrode pads 25a of the ferroelectric capacitor through holes formed in the insulating layers 26a, 26b, and 26c for each memory cell.

The memory having the above structure is basically a 1T-CC TFT-FRAM structure. In particular, as in the 1T-CC FRAM, not only the TFT is connected to the upper electrode but also the source 27a of the TFT is connected to the lower electrode so that one TFT is connected to one ferroelectric capacitor. Can be. The channel 25 of the upper electrode serves as the original upper electrode of the ferroelectric capacitor. The plug 23 may use a barrier material to suppress the reaction with the ferroelectric 22 as much as possible. The upper electrode pads 25, 25a, 25b are divided into a portion 25a for sensing and a portion 25b connected to the channel 25 and the plug 23, and the end portion of the channel 25 is The plate line P (n) is formed to be in ohmic contact with an external input terminal (not shown), which serves as a word line of the TFT, in the same manner as the gate line. Therefore, the TFT is manufactured to be operated by the upper gate 1 (word line) and the channel 25 which is the upper electrode of the lower ferroelectric capacitor. FIG. 3 illustrates a planar view of only the lower electrode 21, the contact path 23 (plug, contact via), the upper electrode pads 25, 25a and 25b, and the TFTs. The upper electrode pads form a wide band and have a channel 25 in the middle.

A method of operating a non-destructive read thin film transistor ferroelectric random access memory fabricated as described above will be described with reference to FIGS. 4A, 4B, and 5A and 5B.

First, in the write operation, as shown in FIGS. 4A and 4B, voltages V _D and V ′ _D are applied to the bit line 29 and voltages V _P and V ′ are applied to the channel 25 of the upper electrode pad. By applying _P ), the ferroelectric 22 between the pad channel 25 and the lower electrode 21 is polarized. At this time, the polarization direction can be adjusted by using a difference between the voltages V _D and V ′ _D of the channel 25 and the voltages V _P and V ′ _P of the bit lines 29. That is, if V ₁ &gt; V _P , the write 1 becomes, and if V ′ _D &lt; V ' _P , the write 0 becomes vice versa. Since the lower electrode 21 is formed independently, each cell can be selected independently. During this write operation, charges to maintain balance with the ferroelectric polarization are induced on the channel 25 in the form of bound charges. In Figs. 4A and 4B and 5A and 5B, n-channels are taken as an example. Therefore, when a negative charge is induced, a depletion mode in which current flows without a gate voltage is obtained. When positive charge is induced, a channel is not formed without a gate voltage. If V ' _D <V' _P , the word line is also activated when there is a fear that the transistor will not operate.

Next, as shown in FIGS. 5A and 5B, when a read is to be performed, first, a voltage V _R is applied to the bit line 29 to perform addressing as in writing, and to perform a gate. When a memory cell is selected by applying a voltage V _G to the word line 28, current flows through the upper electrode pads 25, 25a, and 25b. At this time, since the bit line voltage and the lower electrode voltage are the same, the polarization of the ferroelectric is not affected. If the channel 25 of the upper electrode is in one state, current passes through the sensing circuit. If the channel 25 of the upper electrode is in one state, current is not detected.

6 shows an equivalent circuit of a non-destructive read thin film transistor ferroelectric random access memory cell array according to the present invention. The sensing line S / A is produced in parallel with the bit line B (n). The plate line P (n) is a kind of second word line for applying the voltages V _P and V ' _P during a write operation.

As described above, the non-destructive read thin film transistor ferroelectric random access memory according to the present invention has a structure in which each memory cell has a thin film transistor mounted on the ferroelectric capacitor, and the lower electrode is an independent structure, and the upper electrode is the first electrode. The second channel of the addressing thin film transistor is disposed on the first channel, the source of each memory cell is connected to one side and the lower electrode of the upper electrode, and the gates of the memory cells are connected to each other. Forming word lines, connecting first channels of each memory cell to form plate lines, connecting drains of each memory cell to form bit lines, and connecting the other side of the upper electrode of each memory cell to a sensing line By selectively operating each cell selectively to achieve the purpose of RAM. It is possible to realize non-destructive read (NDRO) method that does not need restoration, and at the same time, the reference line that can be addressed can be commonly used for writing and reading. It becomes possible.

Claims (18)

Board; First electrodes independently formed on the substrate; A ferroelectric layer deposited over the first electrodes and the substrate to a predetermined thickness or more; Second electrode pads having a first channel formed on the ferroelectric layer to intersect the first electrodes; And Thin film transistors whose sources are simultaneously connected to one side of the second electrode pads and the first electrodes on the ferroelectric layer, respectively for addressing the ferroelectric capacitors; Non-destructive read thin film transistor ferroelectric random access memory, characterized in that provided. The method of claim 1, And the first electrodes are separately formed to correspond one-to-one to the thin film transistors of each memory cell. The method of claim 1, The thickness of the ferroelectric layer is a non-destructive read thin film transistor ferroelectric random access memory, characterized in that the minimum thickness capable of forming a polarization. The method of claim 1, The non-destructive read thin film transistor ferroelectric random access memory of one side of the second electrode pads and the first electrodes are connected by plugs passing through the ferroelectric layer, respectively. The method of claim 4, wherein Non-destructive read thin film transistor ferroelectric random access memory, characterized in that the partition is further formed around the plug to prevent the reaction with the ferroelectric layer. The method according to any one of claims 1 to 5, And the first channel is formed in a band shape at the center of the second electrode pad, and is formed as a plate line having both ends thereof in ohmic contact with an external terminal. The method of claim 6, And non-destructive read thin film transistor ferroelectric random access memory, wherein drains of the thin film transistor are simultaneously connected to the second electrode pads and the first electrode lines. The method of claim 6, The thin film transistor includes a source and a drain; A second channel formed between the source and the drain in the same layer as the source and the drain; And A gate stacked on the second channel with an insulating layer interposed therebetween; Non-destructive read thin film transistor ferroelectric random access memory, characterized in that provided. The method of claim 6, And non-destructive read thin film transistor ferroelectric random access memory. The method of claim 6, And the first channels of the plate lines correspond to each other with the channel of the thin film transistor interposed therebetween with an insulating layer having a predetermined thickness therebetween. The method of claim 9, Non-destructive read thin film transistor ferroelectric random access characterized in that the bit line is formed on the stripe in the direction intersecting the word line with an insulating layer between the thin film transistor, the bit line is connected to the drain. Memory. The method of claim 10, Non-destructive sensing lines are formed on the bit lines with the insulating layer interposed therebetween in a direction parallel to the word line, wherein the sensing lines are formed to be connected to the other side of the second electrode pads. Read thin film transistor ferroelectric random access memory. The method of claim 10, Non-destructive sensing lines are formed on the bit lines with the insulating layer interposed therebetween in the direction parallel to the bit line, wherein the sensing lines are formed to be connected to the other side of the second electrode pads. Read thin film transistor ferroelectric random access memory. First electrodes formed on the substrate; A ferroelectric layer deposited on the first electrodes and the substrate to a predetermined thickness or more; Second electrode pads having a first channel for forming ferroelectric capacitors corresponding to each memory cell on the ferroelectric layer corresponding to the first electrodes; And thin film transistors on the ferroelectric layer of each of the memory cells for addressing ferroelectric capacitors of the respective memory cells, having gates on top of the second channel, source and drain, and the second channel. A source of each memory cell is connected to one side of the second electrode pad and the first electrode, and gates of the memory cells are connected to form word lines, and the first channels of the memory cells are connected to each other to form a plate. A non-destructive read thin film transistor ferroelectric random access memory having lines formed therebetween, connecting bit lines to drains of the memory cells, and connecting the other side of the second electrode pad of the memory cells to form sensing lines. In the driving method, Writing a polarization layer of the addressed ferroelectric layer by applying a voltage signal to the plate line and the bit line; And A predetermined voltage signal is applied to the word line and the bit line, respectively, and is applied through the bit line through the sensing line according to whether or not electrical conduction is performed according to the polarity of the bond charge bound to the first channel of the memory cell addressed. A reading step of sensing current by a voltage signal and sensing information by polarization state of the ferroelectric layer; And a method of driving a non-destructive read thin film transistor ferroelectric random access memory. The method of claim 14, The recording step, The polarization direction of the ferroelectric layer is determined by the potential difference between the voltage signal applied to the plate line and the bit line, respectively. The method of claim 15, In the writing step, a voltage greater than the voltage applied to the plate line is applied to the bit line to record 1, and a voltage less than the voltage applied to the plate line is applied to the bit line to record 0 or to a word line. A method for driving a non-destructive read thin film transistor ferroelectric random access memory, characterized by writing a voltage by applying a voltage. The method of claim 14, In the reading step, when reading the one written as 1, the first channel is not energized by the constrained charge and is sensed as OFF, and when the reading is written as 0, the first channel is energized by the charge constrained in the first channel. A method for driving a non-destructive read thin film transistor ferroelectric random access memory, characterized in that sensing by ON. The method of claim 14, And a reference voltage addressing a memory cell to be written or read in the write and read steps as a voltage applied to the bit line.