KR100269209B1 - A nondestructive read out tft ferroelectric random access memory and an operating method thereof - Google Patents

Abstract

PURPOSE: A nondestructive read out thin film transistor ferroelectric random access memory and a method for driving the same are provided to polarize the ferroelectric portion to prevent crosstalk while guaranteeing integrity density. CONSTITUTION: The nondestructive read out thin film transistor ferroelectric random access memory includes a plate line(110), a ferroelectric layer(109), the first semiconductor doping layer and the second semiconductor doping layer. The transistor further includes a read bit line(B), a match layer(108), a plug, a word line(102) and a write bit line(B). The read bit line is arranged in a direction parallel with that of the plate line to be coupled with the first drains electrically. The match layer couples the first channel with the first source. The plug coupled the match layer and the second source electrically. The word line is formed by coupling the gate in the direction normal to that of the plate line. The write bit line is formed by coupling the second drains in a direction same to that of the plate line.

Description

Nondestructive Read Thin Film Transistor Ferroelectric Random Access Memory and Its Operation Method

The present invention relates to nondestructive read out (NDRO) thin film transistor ferroelectric random access memory (TFT-FRAM) and methods of operation thereof.

1 is a schematic vertical cross-sectional view of a ferroelectric random access memory of the conventional 1T-1C structure. As shown, the 1T-1C structure connects a CMOS transistor (10, 14b, 15, 16, 17) and ferroelectric capacitors (11, 12, 13) to an electrode (18b) to connect one cell. Forming. That is, the insulating layer 14b is formed on the channel 19 of the silicon substrate 10 on which the source 15 and the drain 17 are formed by impurity doping, and the gate 16 is formed in the insulating layer 14b. The formed CMOS transistor and the lower electrode 11, the ferroelectric layer 12, and the upper electrode 13 have a structure in which the ferroelectric capacitors 11, 12, 13, which are sequentially stacked, are connected. This is called a 1T-1C structure, where 1T-1C becomes one cell. Here, an insulating layer is opened on the top of the source 15 and the drain 17 of the CMOS transistor to form a source electrode 18a and a drain electrode 18b. A ferroelectric capacitor is fabricated on the CMOS substrate 10 and surrounded by a periphery. The electrode 18c is connected to the transistor of the upper portion of the transistor through an opening of the insulating layer. As such, the 1T-1C, in which each memory cell is composed of one transistor and one ferroelectric capacitor, has a limit that cannot guarantee an integration degree equivalent to a single transistor FRAM.

2 is a schematic vertical cross-sectional view of a ferroelectric random access memory of the conventional 1T-CC structure. As shown, a thin film transistor ferroelectric random access memory having a 1 transistor-common capacitor (1T-CC) structure has a structure in which thin film transistors are integrated on a common ferroelectric capacitor. That is, the lower electrode 1 of the ferroelectric capacitor is first deposited and used as a common electrode. The ferroelectric material 2 is deposited on the common lower electrode 1 and used as the common ferroelectric layer 2. At this time, there is no limitation of the ferroelectric layer deposition temperature for the semiconductor. Next, the upper electrode 3 is deposited for each memory cell to form each memory cell. Then, an insulator 4a is deposited on the upper electrode 3, but leaves a window in which the upper electrode 3 and the thin film transistor are in contact. A thin film transistor (TFT) is formed thereon. As such, the 1T-CC TFT-FRAM in which the transistors corresponding to the respective memory cells are formed on one common ferroelectric layer may have a higher integration density than the 1T-1C FRAM, but still has a limitation in integration density.

In addition, the single transistor ferroelectric random access memory (Single transistor FRAM) is simple in structure, but the circuit formation for operation is still not established, and NonDesructive Read Out TFT-FRAM is not suitable for high integration, single transistor (single transistor) TFT-FRAM has a complicated structure and operation method.

The present invention was devised to improve the above-mentioned problems, while ensuring the density for nondestructive read out (NDRO) type ferroelectric memory and being subjected to crosstalk while selectively polarizing the ferroelectric region. To provide a non-destructive read thin film transistor ferroelectric random access memory and its operation method.

1 is a schematic vertical cross-sectional view of a ferroelectric random access memory of a conventional 1T-1C structure;

2 is a schematic vertical cross-sectional view of a ferroelectric random access memory of the conventional 1T-CC structure;

3 is an excerpted vertical sectional view of a non-destructive read thin film transistor ferroelectric random access memory according to the present invention;

4A and 4B are equivalent circuit diagrams of the non-destructive read thin film transistor ferroelectric random access memory of FIG. 3, respectively.

5A is a schematic perspective plan view taken along line A-A 'of the NDRO 1T-CC TFT-FRAM cell of FIG. 3;

5B is a schematic left side view taken along line B-B 'of the NDRO 1T-CC TFT-FRAM cell of FIG. 3;

FIG. 5C is a schematic right side view taken along the line CC ′ of the NDRO 1T-CC TFT-FRAM cell of FIG. 3;

6A and 6B are diagrams for describing the " write " operation in the non-destructive read thin film transistor ferroelectric random access memory of FIG.

7A and 7B are diagrams for describing the " read " operation in the non-destructive read thin film transistor ferroelectric random access memory of FIG.

8 is an equivalent circuit diagram of the non-destructive read thin film transistor ferroelectric random access memory of FIG. 3.

<Explanation of symbols for the main parts of the drawings>

101. Bit line (B) for "write"

102. Wordline (W)

103. Source of TFT

104. Second channel for TFT

105. Contact plug

106. Bitline for "Read" (B *)

107. First channel for ferroelectric capacitor upper electrode

108. Conductive contact barrier

109. Ferroelectric Layer

110. Plate pads (or plate lines)

In order to achieve the above object, the non-destructive read thin film transistor ferroelectric random access memory according to the present invention comprises: a plate line formed on a stripe in one direction to serve as a lower electrode of the ferroelectric capacitor; A ferroelectric layer formed on the plate line; A first semiconductor doping layer stacked with a first impurity doping layer and a second impurity doping layer on the ferroelectric to serve as an upper electrode of the ferroelectric capacitor corresponding to each memory cell and forming a first channel and a first source and a drain; A second semiconductor doping layer stacked on the first semiconductor doping layer with the first impurity doping layer and the second impurity doping layer to form a second channel and a second source and a drain, and a gate formed on the second channel. A read bit line formed in a direction parallel to the plate line such that the first drains are electrically connected to each other; A bonding layer connecting the first channel and the first source together; A plug electrically connecting the bonding layer and the second source; A word line formed by connecting the gate in a direction crossing the plate line; And a write bit line formed by connecting the second drains in a direction parallel to the plate line.

In the present invention, the thin film transistor is preferably manufactured by bonding using SOI or smart cut or by directly depositing a semiconductor.

In addition, to achieve the above object, a non-destructive read thin film transistor ferroelectric random access memory operating method according to the present invention, the plate line is formed in one direction of the stripe to serve as a lower electrode of the ferroelectric capacitor; A ferroelectric layer formed on the plate line; A first semiconductor doping layer stacked with a first impurity doping layer and a second impurity doping layer on the ferroelectric to serve as an upper electrode of the ferroelectric capacitor corresponding to each memory cell and forming a first channel and a first source and a drain; A second semiconductor doping layer stacked on the first semiconductor doping layer with the first impurity doping layer and the second impurity doping layer to form a second channel and a second source and a drain, and a gate formed on the second channel. A read bit line formed in a direction parallel to the plate line such that the first drains are electrically connected to each other; A bonding layer connecting the first channel and the first source together; A plug electrically connecting the bonding layer and the second source; A word line formed by connecting the gate in a direction crossing the plate line; 10. A method of operating a non-destructive read thin film transistor ferroelectric random access memory having a write bit line formed by connecting the second drain lines in a direction parallel to the plate line, wherein the word line is used as a reference. A write step of applying a voltage to the word line to address a memory cell, and writing information by applying a potential difference between the read bit line and the plate line; And (b) applying a voltage to the word line to address a memory cell and reading information through a sense amplifier connected to the write bit line by a voltage applied to the read bit line. It is characterized by.

Hereinafter, a non-destructive read thin film transistor ferroelectric random access memory and a method of operating the same will be described in detail with reference to the accompanying drawings.

According to the present invention, a non-destructive read thin film transistor ferroelectric random access memory uses a word line of a thin film transistor as a reference for an address, and writes a bit line B and a read bit line. Bit line (B ^* ) is a special feature. Thin film transistors (TFTs) formed on ferroelectric capacitors are fabricated using silicon on insulate (SOI) or smart cut or directly It is produced by vapor deposition.

3 is an excerpted vertical sectional view of a non-destructive read thin film transistor ferroelectric random access memory (NDRO 1T-CC TFT-FRAM) according to the present invention. As shown, the non-destructive read TFT FRAM according to the present invention deposits a ferroelectric 109 on a stripe-shaped plate pad 110, and a semiconductor thin film pad as an upper electrode corresponding to each memory cell thereon. form a pad. This semiconductor pad has the form of a TFT without a gate, the center of which is the first channel p (107) and the edges of which are the first source (n ⁺ ) and the first drain (n ⁺ ). One side of the semiconductor pad is connected to the plate line 110 in a parallel read-only bit line 106 (bit *), and the other side and the channel 107 are connected to the same conductive material to form a bonding layer 108. do. The bonding layer 108 of this conductive material is again connected to the contact plug 105 and the plug 105 is connected to the second source 103 of the TFT. The second drain of the TFT is connected to the write-only bit line 101. This structure is called NDRO 1T-CC TFT-FRAM. 4A and 4B show equivalent circuit diagrams of these nondestructive read thin film transistor ferroelectric random access memories, respectively.

FIG. 5A is a schematic perspective plan view taken along line A-A 'of the NDRO 1T-CC TFT-FRAM cell of FIG. 3, and FIG. 5B shows line B-B' of the NDRO 1T-CC TFT-FRAM cell of FIG. FIG. 5C is a schematic right side view taken along the line CC ′ of the NDRO 1T-CC TFT-FRAM cell of FIG. 3. As shown, the plate line 110, that is, the plate pad and the bit line 101, are parallel to each other and perpendicular to the word lines 102.

The operation method of the NDRO 1T-1CC TFT-FRAM having the above structure is as follows.

First, FIGS. 6A and 6B are diagrams for describing the " write " operation in the non-destructive read thin film transistor ferroelectric random access memory (NDRO 1T-1CC TFT-FRAM) of FIG. 3, respectively. In these figures, the case of an n-channel transistor is taken as an example. As shown in FIG. 6A, a voltage Vw is first applied to a gate line 102 to address a memory cell, and then a voltage Vb is applied to the bit line 101. When the voltage is transferred to the upper electrode of the ferroelectric capacitor via the junction layer 108, the ferroelectric is polarized as much as the upper electrode area. Specify this as "0". As shown in FIG. 6B, in the case of reverse polarization, the voltage Vw is applied to the gate line 102 to address the voltage Vp, and the ferroelectric capacitor is applied to the plate pad 110. The polarization is reversed by the first channel 107 and the first source portion constituting the upper electrode. Specify this as "1". If it is polarized to "0", positive bound charge is formed in the upper electrode first channel 107, and if it is polarized to "1", negative negative charge is formed in the upper electrode first channel 107. charge) is formed.

7A and 7B are diagrams for explaining the " read " operation in the non-destructive read thin film transistor ferroelectric random access memory (NDRO 1T-1CC TFT-FRAM) of Fig. 3, respectively. When reading the memory state, the voltage Vw is applied to the gate line 102 to address the cell to be read, and the voltage Vr is applied to the read-only bit line 106. First, as shown in FIG. 7A, when the channel is recorded as "0", no current flows because the channel 107 is in the "off" state, and as shown in FIG. 7B, the channel is recorded as "1". Since 107 is "on", current flows and is sensed by a sense amplifier (S / A) P-channel is the same principle as n-channel but "0" is "on" and "1" "Is off".

Such a write or read method is characterized in that the voltage is addressed by applying a voltage to a specific word line W (n) to select a memory cell to be written or read, especially at the start of operation, as shown in FIG. have. In this case, since a voltage is applied to the gate of the TFT, the corresponding TFT is operated so that current flows through the ferroelectric capacitor thereunder, thereby causing polarization or reading channel information by polarization.

As described above, the non-destructive read thin film transistor ferroelectric random access memory according to the present invention can maintain the same density as the conventional single transistor type FRAM because the cell size is determined by the upper electrode area. In addition, addressing can follow a conventional memory operation design since a single wordline is referenced. Therefore, it becomes FRAM having only the advantages of 1T-1C FRAM, NDRO FRAM, and TFT-FRAM.

Claims (3)

A plate line formed on one side of the stripe to serve as a lower electrode of the ferroelectric capacitor; A ferroelectric layer formed on the plate line; A first semiconductor doping layer stacked with a first impurity doping layer and a second impurity doping layer on the ferroelectric to serve as an upper electrode of the ferroelectric capacitor corresponding to each memory cell and forming a first channel and a first source and a drain; A second semiconductor doping layer stacked on the first semiconductor doping layer with the first impurity doping layer and the second impurity doping layer to form a second channel and a second source and a drain, and a gate formed on the second channel. And a thin film transistor, A read bit line formed in a direction parallel to the plate line such that the first drains are electrically connected to each other; A bonding layer connecting the first channel and the first source together; A plug electrically connecting the bonding layer and the second source; A word line formed by connecting the gate in a direction crossing the plate line; A write bit line formed by connecting the second drain lines in a direction parallel to the plate line; A non-destructive read thin film transistor ferroelectric random access memory, comprising: The method of claim 1, The thin film transistor is a non-destructive read thin film transistor ferroelectric random access memory, characterized in that fabricated by using a SOI or smart cut or by directly depositing a semiconductor. A plate line formed on one side of the stripe to serve as a lower electrode of the ferroelectric capacitor; A ferroelectric layer formed on the plate line; A first semiconductor doping layer stacked with a first impurity doping layer and a second impurity doping layer on the ferroelectric to serve as an upper electrode of the ferroelectric capacitor corresponding to each memory cell and forming a first channel and a first source and a drain; A second semiconductor doping layer stacked on the first semiconductor doping layer with the first impurity doping layer and the second impurity doping layer to form a second channel and a second source and a drain, and a gate formed on the second channel. A read bit line formed in a direction parallel to the plate line such that the first drains are electrically connected to each other; A bonding layer connecting the first channel and the first source together; A plug electrically connecting the bonding layer and the second source; A word line formed by connecting the gate in a direction crossing the plate line; 10. A method of operating a non-destructive read thin film transistor ferroelectric random access memory having a write bit line formed by connecting the second drain lines in a direction parallel to the plate line. With the word line as a reference for addressing, (A) writing a voltage by applying a voltage to the word line to address a memory cell, and writing information by applying a potential difference between the read bit line and the plate line; And (B) applying a voltage to the word line to address a memory cell and reading information through a sense amplifier connected to the write bit line by a voltage applied to the read bit line; And operating the non-destructive read thin film transistor ferroelectric random access memory.