KR100269208B1 - A thin film transistor ferroelectric random access memory with a common word line and an operating method thereof - Google Patents

Abstract

PURPOSE: A thin film transistor ferroelectric random access memory is provided to make each memory cell by using one TFT and one ferroelectric capacitor, and makes a common word line used as a reference of an addressing by interconnecting a gate and source of TFT with a common word line. CONSTITUTION: A lower electrode of a ferroelectric capacitor is formed in one-direction strip-shape in order to form a plate line(106). A channel(103) of the TFT is functioned as an upper electrode of the ferroelectric capacitor(105) corresponding to each memory cell. A gate and a source of the TFT are interconnected to form a strip-shape common word line crossed with the plate line. a bit line(101) is arranged parallel with plate line(106) by connecting a drain of the TFT.

Description

Thin Film Transistor Ferroelectric Random Access Memory with Common Wordline and Its Operation Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric random access memory, and more particularly, to a thin film transistor ferroelectric random access memory capable of nondestructive reading and each memory cell having a common word line consisting of one thin film transistor and a ferroelectric capacitor, and a method of operating the same. will be.

Ferroelectric memories, which are non-destructive read out (NDRO) and each memory cell consists of a single transistor, have been considered virtually impossible in the form of random access memory (RAM). To overcome this problem, the structure and operation method of NDRO 1T-1CC TFT-FRAM and NDRO 1T-1C FRAM are described as follows.

1 is a schematic vertical cross-sectional view of a ferroelectric random access memory of the conventional 1T-1C structure. As shown, the 1T-1C structure connects a CMOS transistor (10, 14b, 15, 16, 17) and ferroelectric capacitors (11, 12, 13) to an electrode (18b) to connect one cell. Forming. That is, the insulating layer 14b is formed on the channel 19 of the silicon substrate 10 on which the source 15 and the drain 17 are formed by impurity doping, and the gate 16 is formed in the insulating layer 14b. The formed CMOS transistor and the lower electrode 11, the ferroelectric layer 12, and the upper electrode 13 have a structure in which the ferroelectric capacitors 11, 12, 13, which are sequentially stacked, are connected. This is called a 1T-1C structure, where 1T-1C becomes one cell. Here, an insulating layer is opened on the top of the source 15 and the drain 17 of the CMOS transistor to form a source electrode 18a and a drain electrode 18b. A ferroelectric capacitor is fabricated on the CMOS substrate 10 and surrounded by a periphery. The electrode 18c is connected to the transistor of the upper portion of the transistor through an opening of the insulating layer.

2 is a schematic vertical cross-sectional view of a ferroelectric random access memory of the conventional 1T-CC structure. As shown, a thin film transistor ferroelectric random access memory having a 1 transistor-common capacitor (1T-CC) structure has a structure in which thin film transistors are integrated on a common ferroelectric capacitor. That is, the lower electrode 1 of the ferroelectric capacitor is first deposited and used as a common electrode. The ferroelectric material 2 is deposited on the common lower electrode 1 and used as the common ferroelectric layer 2. At this time, there is no limitation of the ferroelectric layer deposition temperature for the semiconductor. Next, the upper electrode 3 is deposited for each memory cell to form each memory cell. Then, an insulator 4a is deposited on the upper electrode 3, but leaves a window in which the upper electrode 3 and the thin film transistor are in contact. A thin film transistor (TFT) is formed thereon.

As described above, the conventional ferroelectric random access memory of the 1T-1C structure or the ferroelectric random access memory of the 1T-CC structure have a word line, a bit line, and a plate line in a layer structure. In addition, a sensing bitline is added to keep the four lines in use.

The present invention has been devised to improve the above problems, wherein each memory cell is composed of one thin film transistor and a ferroelectric capacitor, and the thin film transistors corresponding to each memory cell are formed on the entire ferroelectric capacitor, but the gate of the thin film transistor is used. It is an object of the present invention to provide a thin film transistor ferroelectric random access memory having a common word line, which is connected to a common word line and a source together to serve as a reference.

1 is a schematic vertical cross-sectional view of a ferroelectric random access memory of a conventional 1T-1C structure;

2 is a schematic vertical cross-sectional view of a ferroelectric random access memory of the conventional 1T-CC structure;

3 is an excerpt vertical cross-sectional view of a thin film transistor ferroelectric random access memory having a common word line according to the present invention;

4 is a schematic plan view of a thin film transistor ferroelectric random access memory having a common wordline of FIG.

5A and 5B are diagrams for describing the " write " operation of the thin film transistor ferroelectric random access memory having the common word line of FIG.

6A and 6B are diagrams for describing a “read” operation of the thin film transistor ferroelectric random access memory having the common word line of FIG. 3.

<Explanation of symbols for the main parts of the drawings>

101.Bit line (B)

102. Common Word Line (W)

103. TFT channel

104. Diffusion layer

105. Ferroelectric

106. Plate line

107. Sensor Amplifier

In order to achieve the above object, a thin film transistor ferroelectric random access memory having a common word line according to the present invention is a ferroelectric capacitor and a ferroelectric random access memory in which thin film transistors corresponding to each memory cell are disposed on the ferroelectric capacitor. And a lower electrode of the ferroelectric capacitor is formed in a stripe shape in one direction to form a plate line, and a channel of the thin film transistor serves as an upper electrode of a ferroelectric capacitor corresponding to each of the memory cells, and controls the gate and the source of the thin film transistor. By connecting together to form a common word line on the stripe in the direction crossing the plate line, the drain of the thin film transistor is connected to form a bit line parallel to the plate line.

In addition, in order to achieve the above object, a method of operating a thin film transistor ferroelectric random access memory having a common word line according to the present invention includes disposing a thin film transistor corresponding to each memory cell on a ferroelectric capacitor and the ferroelectric capacitor, The lower electrode of the ferroelectric capacitor is formed in a stripe shape in one direction to form a plate line, and the channel of the thin film transistor serves as the upper electrode of the ferroelectric capacitor corresponding to each memory cell, and the gate and the source of the thin film transistor are together. A thin film transistor ferroelectric having a common word line connected to form a common word line on a stripe in a direction crossing the plate line, and having a bit line parallel to the plate line by connecting a drain of the thin film transistor. A method of operating a random random access memory, comprising: (a) writing information by applying a potential difference between the common word line and a plate line by using the common word line as a reference; And (b) reading information through a sense amplifier connected to the bit line by a voltage applied to the common word line.

Hereinafter, a thin film transistor ferroelectric random access memory having a common word line and a method of operating the same will be described in detail with reference to the accompanying drawings.

The thin film transistor ferroelectric random access memory having a common word line according to the present invention is a non-destructive read type (NDRO type), which is the most ideal operation type in FRAM, and each memory cell is formed of thin film transistors formed on a substrate type ferroelectric capacitor. At this time, the gate and the source of each thin film transistor of each cell are connected to a word line as a reference for addressing, information is written into the word line and a plate, and a word line and a bit line are sense amplifiers. line). A TFT-FRAM structure for implementing this is shown in FIGS. 3 and 4.

3 is an excerpt vertical cross-sectional view of a thin film transistor ferroelectric random access memory having a common word line according to the present invention, and FIG. 4 is a schematic plan view of the thin film transistor ferroelectric random access memory having a common word line of FIG. As shown, the thin film transistor ferroelectric random access memory having a common word line according to the present invention is a common word line (102), plate line (106), bit line (101) ) And all of the cells are stacked on the ferroelectric 105. The thin film transistors constituting each memory cell connect a gate (corresponding to a word line) and a source 104 to form a common word line 102. The drains of the thin film transistors are connected to each other to form a bit line 101, but are connected to a sensor amplifier (not shown, see FIGS. 6A and 6B). Plate line 106 corresponds to the lower electrode of the ferroelectric capacitor and is composed of a pad made of a conductive material. If the source 104 is of type n ⁺ , the channel 103 is of type p. If the source 104 is of type p ⁺ , the channel 103 is of type n. In the embodiment of the figure, n ⁺ type source (drain) is shown as an example.

The operation method of the thin film transistor ferroelectric random access memory having the common word line configured as described above is as follows.

First, FIGS. 5A and 5B are diagrams for describing a " write " operation of the thin film transistor ferroelectric random access memory having the common word line of FIG. As shown, when writing to a memory cell, word line 102 is first taken and addressed and a potential difference is applied between word line 102 and plate line 106. This potential difference determines the charge polarity induced in the channel 103. As shown in FIG. 5A, when the voltage Vw of the word line 102 is greater than the voltage Vp of the plate line 106, a positive charge is induced in the channel 103 of the cell, which is the domain of the ferroelectric 105. It is balanced by (domain) and becomes bound charge, so it does not disappear. Assign this as recorded as "1". As shown in FIG. 5B, when the voltage V′w of the word line 102 is smaller than the voltage V′p of the plate line 106, negative charge is induced in the channel 103 of the corresponding cell. Assign this as recorded as "0". Of course, it can also be set as opposed to the above case.

6A and 6B are diagrams for explaining the " read " operation of the thin film transistor ferroelectric random access memory having the common word line of FIG. As shown, when reading the recorded information, the word line 102 is first selected and addressed, the read voltage Vr is applied, and the bit line 101 to which the sensor amplifier 107 is connected is selected. Can be detected. That is, as shown in Fig. 6A, a cell written as "1" is detected as "off", and as shown in Fig. 6B, a cell written as "0" is detected as "on". .

As described above, the thin film transistor ferroelectric random access memory having the common word line according to the present invention is a non-destructive read type (NDRO type) and forms a thin film transistor on the ferroelectric capacitor to form each memory cell, The gate and source are connected by word lines to serve as a reference for addressing, which simplifies the fabrication of TFT-FRAM by eliminating the need to stack silicon thin films in layers. In addition, the NDRO method can be maintained, reducing the burden of fatigue and increasing integration due to the single thin film transistor type.

Claims (2)

A ferroelectric random access memory in which a thin film transistor corresponding to each memory cell is disposed on a ferroelectric capacitor and the ferroelectric capacitor, The lower electrode of the ferroelectric capacitor is formed in a stripe shape in one direction to form a plate line, and the channel of the thin film transistor serves as the upper electrode of the ferroelectric capacitor corresponding to each memory cell, and the gate and the source of the thin film transistor are together. A thin film transistor ferroelectric having a common word line connected to form a common word line on a stripe in a direction crossing the plate line, and connecting a drain of the thin film transistor to form a bit line parallel to the plate line. Random access memory. A thin film transistor corresponding to each memory cell is disposed on the ferroelectric capacitor and the ferroelectric capacitor, and the lower electrode of the ferroelectric capacitor is formed in a stripe in one direction to form a plate line, and the channel of the thin film transistor is formed in each of the memory cells. It acts as an upper electrode of the corresponding ferroelectric capacitor, connects the gate and the source of the thin film transistor together to form a common word line on the stripe in the direction crossing the plate line, and connects the drain of the thin film transistor to the plate line. A method of operating a thin film transistor ferroelectric random access memory having a common word line having a bit line parallel to the By using the common word line as a reference for addressing, (A) writing information by applying a potential difference between the common word line and the plate line; And (B) reading information through a sense amplifier connected to the bit line by a voltage applied to the common word line; And operating a thin film transistor ferroelectric random access memory having a common word line.