JP3430117B2 - Ferroelectric memory, operation control method thereof, ferroelectric memory cell structure and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory, an operation control method thereof, a ferroelectric memory cell structure and a manufacturing method thereof, and more specifically, a plurality of ferroelectric capacitors for storing data and a switching operation. The present invention relates to a ferroelectric memory in which a memory cell is composed of a plurality of memory cell transistors that perform the above, an operation control method thereof, a ferroelectric memory cell structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art Semiconductor memory devices are roughly divided into two types: so-called volatile memory, which loses stored data when the power is turned off, and so-called non-volatile memory, which retains the stored data even when the power is turned off. It The former representative is RA
While known as M (Random Access Memory), a representative of the latter is known as ROM (Read Only Memory). Most of these memories are composed of MOS (Metal Oxide Semiconductor) type transistors which are excellent in terms of integration.

Further, the RAM is widely applied to various storage devices such as data equipment because the RAM can make the most of the advantage of high integration as described above as compared with the ROM so that the cost can be reduced. In addition, in a widely used D (Dynamic) RAM among RAMs, a capacitor is used to store data depending on the presence / absence of electric charge of the capacitor. In order to compensate for the decrease in memory capacity due to the restriction of the area occupied by the capacitor, various measures have been taken in the structure of the capacitor.

By the way, as one type of RAM, a ferroelectric memory using a ferroelectric material as a dielectric material forming the above-mentioned capacitor has been developed. In this ferroelectric memory, polarization of the ferroelectric material is used for storing data. By utilizing the phenomenon, it operates as a non-volatile RAM in which stored data is not erased even when the power is turned off.

FIG. 12 is a circuit diagram showing a conventional ferroelectric memory disclosed in, for example, Japanese Patent No. 2674775. As shown in the figure, the ferroelectric memory includes a ferroelectric capacitor 102 that holds a memory and a memory cell transistor 101 that is connected in series to perform a switching operation. A memory cell 104 that stores 1-bit data is provided.
The word line WL is connected to the gate electrode of the memory cell transistor 101, and the plate line PL is connected to the electrode of the ferroelectric capacitor 102 opposite to the side to which the memory cell transistor 101 is connected. Further, the bit line BL is connected to the electrode of the memory cell transistor 101 opposite to the side to which the ferroelectric capacitor 102 is connected, and further, the differential sense amplifier 103 is connected to this bit line BL. .. This ferroelectric memory is characterized in that a memory cell 104 is composed of one ferroelectric capacitor 102 and one memory cell transistor 101.

FIG. 13 shows another conventional example and is a circuit diagram showing a ferroelectric memory having two ferroelectric capacitors, which is disclosed in, for example, Japanese Patent No. 2736072. As shown in the figure, the ferroelectric memory includes a plurality of memory cells 120 and 12 each storing 1-bit data.
2, 124 and 126 are provided. Here, one memory cell 120 includes two ferroelectric capacitors 121A and 121B connected in series, and these series connected capacitors 121A and 121B.
A and 121B are constituted by the memory cell transistor 128 which is directly connected.

Similarly, the memory cell 122 is composed of two ferroelectric capacitors 123A and 123B connected in series and a memory cell transistor 129.
24 is two ferroelectric capacitors 125A connected in series.
And 125B and the memory cell transistor 131, and the memory cell 126 is constituted by two ferroelectric capacitors 127A and 127B and a memory cell transistor 133 which are connected in series.

The first word line 130 is connected to the memory cell 12
The second word line 132 is connected to the gate electrodes of the memory cell transistors 128 and 129 of 0 and 122, respectively, and the second word line 132 is connected to the gate electrodes of the memory cell transistors 131 and 133 of memory cells 124 and 126, respectively. Has been done. The first bit line 134 and the second bit line 136 are orthogonal to the first word line 130 and the second word line 132, respectively. In addition, the common lines 138 and 140 forming the first paired line 141 are connected to one electrodes of the ferroelectric capacitors 121A, 123A and 121B, 123B of the memory cells 120 and 122, respectively. The common lines 142 and 144 forming the second pair line 145 are ferroelectric capacitors 125A, 1A of the memory cells 124 and 126, respectively.
27A and 125B, 127B are connected to one electrode. In this ferroelectric memory, as described above, one memory cell, for example, the memory cell 120 is composed of two ferroelectric capacitors 121A and 121B connected in series and one memory cell transistor 128. Is a feature.

[0009]

By the way, Japanese Patent No. 26
In the conventional ferroelectric memory described in Japanese Patent No.
Since the ferroelectric memory is configured by using one ferroelectric capacitor, the reference potential is likely to change at the time of reading data, which causes a problem that a data identification error is likely to occur. That is, at the time of data reading, a reference potential that serves as a reference for discriminating between level 1 and level 0 is applied to the bit line. Since it affects and changes its value, the reference potential deviates from the optimum value. Then, in the worst case, it becomes difficult to identify 1 and 0, and a data identification error occurs. Further, in the conventional ferroelectric memory described in Japanese Patent No. 2736072, since the memory cell is configured by using two ferroelectric capacitors connected in series, the reference potential is fixed in principle. Although the above-mentioned drawbacks are prevented,
The occupied area of the memory cell per bit becomes large,
There is a problem. That is, since two ferroelectric memories are used to store 1-bit data, the memory cell needs an area for two ferroelectric capacitors, resulting in an area occupied by the memory cell. Will be increased.

The present invention has been made in view of the above circumstances, and an occupied area of a memory cell necessary for storing 1-bit data without causing a data identification error due to a change in reference potential. It is an object of the present invention to provide a ferroelectric memory, an operation control method thereof, a ferroelectric memory cell structure and a manufacturing method thereof, which are capable of reducing the above.

[0011]

[0012]

[0013]

In order to solve the above-mentioned problems, the invention according to claim 1 relates to a ferroelectric memory which stores data by utilizing a polarization phenomenon of a ferroelectric, and is connected in series. A memory cell is constituted by the first, second, and third three ferroelectric capacitors that have been formed, and the first and second two memory cell transistors, and among the above three ferroelectric capacitors, , The electrodes of the first and second ferroelectric capacitors, which are connected to each other, are both connected to the first bit line via the first memory cell transistor, and the second and third ferroelectric capacitors are connected. The electrodes on the mutually connected sides of the dielectric capacitor are both connected to the second bit line via the second memory cell transistor, and the first and second memory cell transistors are connected to a common word line. Is characterized by being .

[0014] a second aspect of the present invention, relates to a ferroelectric memory according to claim 1, wherein said the first ferroelectric side electrode bit line is not connected capacity first plate line A second plate line is connected to an electrode on the side that is connected and is not connected to the bit line of the third ferroelectric capacitor.

A third aspect of the present invention relates to the ferroelectric memory according to the first or second aspect, and relates to a first reference potential applying bit line corresponding to the first bit line and the second bit line. Corresponding to the second reference potential applying bit line is provided, the first bit line and the first reference potential applying bit line are connected to the first differential sense amplifier,
And the second reference potential applying bit line are connected to the second differential sense amplifier.

According to a fourth aspect of the present invention, there is provided a memory cell including three first, second and third ferroelectric capacitors connected in series and two first and second memory cell transistors. Of the three ferroelectric capacitors, the electrodes of the first and second ferroelectric capacitors which are connected to each other are both connected to the first memory cell transistor via the first memory cell transistor. The electrodes of the second and third ferroelectric capacitors which are connected to the bit line and are connected to each other are both the second electrodes.
Connected to the second bit line via the memory cell transistor, the first and second memory cell transistors are connected to a common word line, and the bit line of the first ferroelectric capacitor is connected. Ferroelectric memory in which a first plate line is connected to the electrode on the non-contact side, and a second plate line is connected to the electrode on the side to which the bit line of the third ferroelectric capacitor is not connected Storing the data read to the first bit line by setting the polarization direction of the first ferroelectric capacitor, and the polarization direction of the third ferroelectric capacitor. Is set to store the data to be read to the second bit line, and the data writing is performed.

A fifth aspect of the present invention relates to the operation control method of the ferroelectric memory according to the fourth aspect, wherein a voltage for turning on the first and second memory cell transistors is applied to the word line. In the state, the first plate line and the first plate line
Of the first and third ferroelectric capacitors are set by applying a voltage between the first bit line and the second bit line and between the second plate line and the second bit line. There is.

[0018] According to a sixth aspect of the invention relates to a control method for a ferroelectric memory according to claim 4, wherein, after the data read, the first and second memory cell transistor to said word line With the voltage to turn off,
By applying a voltage between the first plate line and the second plate line in the direction opposite to that at the time of reading data, the polarization directions of the first ferroelectric capacitor to the third ferroelectric capacitor are changed. After the step of changing the size, the polarization directions of the first and third ferroelectric capacitors are set by the method according to claim 5 .

According to a seventh aspect of the present invention, there is provided a memory cell including first, second and third ferroelectric capacitors connected in series and two first and second memory cell transistors. Of the three ferroelectric capacitors, the electrodes of the first and second ferroelectric capacitors which are connected to each other are both connected to the first memory cell transistor via the first memory cell transistor. The electrodes of the second and third ferroelectric capacitors which are connected to the bit line and are connected to each other are both the second electrodes.
Connected to the second bit line via the memory cell transistor, the first and second memory cell transistors are connected to a common word line, and the bit line of the first ferroelectric capacitor is connected. Ferroelectric memory in which a first plate line is connected to the electrode on the non-contact side, and a second plate line is connected to the electrode on the side to which the bit line of the third ferroelectric capacitor is not connected According to the operation control method, the one of the first and second plate lines is grounded, a voltage is applied between the first plate line and the second plate line, and the word line is applied to the word line. By applying a voltage for turning on the first and second memory cell transistors, a voltage change according to the written data is applied to the first memory cell transistor.
And reading the data including the step of generating the second bit line.

An eighth aspect of the present invention relates to the operation control method of the ferroelectric memory according to the seventh aspect , wherein the first and second aspects are the same.
It is characterized in that the voltage change occurring on the bit line is included in the step of detecting the potential difference between the bit line and another bit line which is precharged to a constant voltage by the differential sense amplifier.

The invention according to claim 9 relates to the operation control method of the ferroelectric memory according to claim 8, for detecting a potential difference from either one of the first and second bit lines. As the voltage value for precharging the bit line to be used, approximately 1/3 of the voltage applied between the first plate line and the second plate line is used, and it is used to detect the potential difference from the other bit line. As a voltage value for precharging the bit line, approximately 2/3 of the voltage applied between the first plate line and the second plate line is used.

According to a tenth aspect of the present invention, there is provided a memory cell including three first, second and third ferroelectric capacitors connected in series and two first and second memory cell transistors. Of the three ferroelectric capacitors, the electrodes of the first and second ferroelectric capacitors which are connected to each other are both connected to the first memory cell transistor via the first memory cell transistor. The electrodes of the second and third ferroelectric capacitors, which are connected to the bit line and are connected to each other, are both connected to the second bit line via the second memory cell transistor, and And the second memory cell transistor are connected to a common word line, the first plate line is connected to the electrode on the side where the bit line of the first ferroelectric capacitor is not connected, and the third memory cell transistor is connected to the common word line. The bit line of the ferroelectric capacitor is not connected The second plate line is connected to the side electrode according to the operation control method of the ferroelectric memory. One of the first and second plate lines which is grounded after the above-mentioned data reading is performed. The plate line of 1 is set to the same potential as the plate line which is not grounded, and then the first and second plate lines are grounded,
After that, rewriting of data is performed including the step of grounding the first and second bit lines.

According to an eleventh aspect of the present invention, a memory cell includes three ferroelectric capacitors of first, second and third connected in series and two memory cell transistors of first and second. Of the three ferroelectric capacitors, the electrodes of the first and second ferroelectric capacitors which are connected to each other are both connected to the first memory cell transistor via the first memory cell transistor. The electrodes of the second and third ferroelectric capacitors, which are connected to the bit line and are connected to each other, are both connected to the second bit line via the second memory cell transistor, and And the second memory cell transistor are connected to a common word line, the first plate line is connected to the electrode on the side where the bit line of the first ferroelectric capacitor is not connected, and the third memory cell transistor is connected to the common word line. The bit line of the ferroelectric capacitor is not connected According to an operation control method of a ferroelectric memory in which a second plate line is connected to a side electrode, the first and second memory cell transistors are connected to the word line after the data is read. When a voltage for turning off is applied, a voltage is applied between the first plate line and the second plate line in the direction opposite to that at the time of reading the data, so that the third ferroelectric capacitor is connected to the third plate capacitor. After the step of changing the polarization direction and the magnitude of the ferroelectric capacitor of (1), the grounded plate line of the first or second plate lines is the same as the non-grounded plate line. Rewriting of data is performed by including a step of setting the potential, a step of grounding the first and second plate lines after that, and a step of grounding the first and second bit lines afterwards. There is.

[0024]

According to a twelfth aspect of the present invention, there is provided a ferroelectric memory which stores data by utilizing a polarization phenomenon of a ferroelectric substance, comprising a plurality of memory cell transistors and one more memory cell transistor than the memory cell transistors. A memory cell is constituted by the ferroelectric capacitors connected in series, and among the ferroelectric capacitors, the kth (k is an integer) and the (k + 1) th ferroelectric capacitors connected to each other are connected. The electrodes are both connected to the kth bit line via the kth memory cell transistor, the common word line is connected to the gate electrode of the memory cell transistor, and the bit of the first ferroelectric capacitor is connected. The first plate line is connected to the electrode on the side not connected to the line, and the second plate line is connected to the electrode on the side not connected to the bit line of the final ferroelectric capacitor. It is characterized in that there.

According to a thirteenth aspect of the present invention, a memory cell is composed of a plurality of memory cell transistors and one more ferroelectric capacitor connected in series than the memory cell transistors, and the ferroelectric capacitor is provided. Among them, the electrodes of the k-th (k is an integer) and the (k + 1) -th ferroelectric capacitors connected to each other are both connected to the k-th bit line via the k-th memory cell transistor. , The common word line is connected to the gate electrode of the memory cell transistor, and the first plate line is connected to the electrode on the side where the bit line of the first ferroelectric capacitor is not connected, According to a method of controlling an operation of a ferroelectric memory, in which a second plate line is connected to an electrode of the ferroelectric capacitor on the side where a bit line is not connected, It is characterized in that the voltage is applied between all the plate lines and the bit lines while the voltage for turning on the transistor is applied to set the polarization direction of the ferroelectric capacitor to write data. ..

According to a fourteenth aspect of the present invention, a memory cell is constituted by a plurality of memory cell transistors and one more ferroelectric capacitor connected in series than the memory cell transistors, and the ferroelectric capacitor is provided. Among them, the electrodes of the k-th (k is an integer) and the (k + 1) -th ferroelectric capacitors connected to each other are both connected to the k-th bit line via the k-th memory cell transistor. , The common word line is connected to the gate electrode of the memory cell transistor, and the first plate line is connected to the electrode on the side where the bit line of the first ferroelectric capacitor is not connected, According to the operation control method of the ferroelectric memory in which the second plate line is connected to the electrode of the ferroelectric capacitor on the side where the bit line is not connected, after performing the above-mentioned data reading, By applying a voltage between the first plate line and the second plate line in a direction opposite to that at the time of reading data in a state where a voltage for turning off the memory cell transistor is applied to the voltage line, After the step of changing the direction and magnitude of polarization of the ferroelectric capacitor, the method of claim 13 is used to set the polarization direction of the ferroelectric capacitor and write data.

According to a fifteenth aspect of the present invention, a memory cell is constituted by a plurality of memory cell transistors and one more ferroelectric capacitor connected in series than the memory cell transistors, and the ferroelectric capacitor is provided. Among them, the electrodes of the k-th (k is an integer) and the (k + 1) -th ferroelectric capacitors connected to each other are both connected to the k-th bit line via the k-th memory cell transistor. , The common word line is connected to the gate electrode of the memory cell transistor, and the first plate line is connected to the electrode on the side where the bit line of the first ferroelectric capacitor is not connected, Of the ferroelectric memory in which the second plate line is connected to the electrode of the ferroelectric capacitor on the side to which the bit line is not connected.
Either one of the plate wires of
Applying a voltage between the plate line of and the second plate line,
By applying a voltage for turning on the first and second memory cell transistors to the word line, the data read including the step of causing a voltage change in all the bit lines according to the written data. It is characterized by doing.

The invention according to claim 16 relates to the operation control method for a ferroelectric memory according to claim 15, wherein the voltage change occurring in the first and second bit lines is determined by a differential sense amplifier. It is characterized in that it is carried out including a step of detecting a potential difference from another bit line which is precharged to a voltage.

A seventeenth aspect of the invention relates to the operation control method of the ferroelectric memory according to the sixteenth aspect, and precharges the bit line used for detecting the potential difference from the k-th second bit line. As the voltage value, the voltage applied between the first plate line and the second plate line is approximately k / (N +
It is characterized by using 1).

According to the eighteenth aspect of the present invention, a memory cell is constituted by a plurality of memory cell transistors and one more ferroelectric capacitor connected in series than the memory cell transistors, and the ferroelectric capacitor is provided. Among them, the electrodes of the k-th (k is an integer) and the (k + 1) -th ferroelectric capacitors connected to each other are both connected to the k-th bit line via the k-th memory cell transistor. , The common word line is connected to the gate electrode of the memory cell transistor, and the first plate line is connected to the electrode on the side where the bit line of the first ferroelectric capacitor is not connected, According to the operation control method of the ferroelectric memory in which the second plate line is connected to the electrode on the side where the bit line of the ferroelectric capacitor is not connected, The step of making the grounded plate line of the first or second plate lines the same potential as the non-grounded plate line, and then the step of grounding the first and second plate lines And re-writing data including the step of grounding all bit lines after that.

According to a nineteenth aspect of the present invention, a memory cell is constituted by a plurality of memory cell transistors and one more ferroelectric capacitor connected in series than the memory cell transistors, and the ferroelectric cell is provided. K of the body volume
The electrodes on the mutually connected sides of the (k is an integer) and the (k + 1) th ferroelectric capacitor are both connected to the kth bit line via the kth memory cell transistor,
A common word line is connected to the gate electrode of the memory cell transistor, a first plate line is connected to the electrode on the side where the bit line of the first ferroelectric capacitor is not connected, and a final plate According to the operation control method of the ferroelectric memory, in which the second plate line is connected to the electrode of the ferroelectric capacitor on the side where the bit line is not connected, the word line is connected to the word line after the data is read. On the other hand, in a state in which a voltage for turning off the memory cell transistor is applied, the first plate line and the second plate line are turned in the direction opposite to that in the data reading.
After the step of changing the polarization direction and the magnitude of all the ferroelectric capacitors by applying a voltage between the plate line and the plate line of Data including the steps of bringing the plate line to the same potential as the non-grounded plate line, then grounding the first and second plate lines, and then grounding all bit lines It is characterized by rewriting.

According to a twentieth aspect of the present invention, a memory cell formed of first, second and third ferroelectric capacitors and first and second memory cell transistors is formed on a semiconductor substrate. Related to the structure of the ferroelectric memory cell,
First Ms operating as the first memory cell transistors respectively formed in desired regions on the semiconductor substrate.
The IS-type transistor and the second MIS-type transistor that operates as the second memory cell transistor are the first
First interlayer insulating film, and first and second bit wirings respectively connected to the element regions of the first and second MIS type transistors are formed on the first interlayer insulating film. In order to cover the first and second bit lines, the first
A second interlayer insulating film is formed on the interlayer insulating film of
The first, second and third ferroelectric capacitors were formed on the inter-layer insulating film, and a wiring structure for connecting the first, second and third ferroelectric capacitors in series was formed. It is characterized by that.

A twenty- first aspect of the present invention relates to the ferroelectric memory cell structure of the twentieth aspect , wherein embedded wiring for connecting a part of the wiring structure to the element regions of the first and second MIS transistors. Is formed.

The invention according to claim 22 is the same as claim 20 or
21. A ferroelectric memory cell structure according to 21 .
A third interlayer insulating film is formed on the second interlayer insulating film so as to cover the second and third ferroelectric capacitors, and the wiring structure is formed on the third interlayer insulating film. It has a feature.

The invention of claim 23, wherein the claim 20, 2
1 or 22 , the first, second and third ferroelectric capacitors each have a laminated structure in which an upper electrode and a lower electrode are formed on both sides of a ferroelectric film. It is characterized by becoming.

The present invention according to claim 24 relates to a method of manufacturing a ferroelectric memory cell structure, wherein a first MIS type transistor and a second MIS type transistor are formed in a desired region of a semiconductor substrate, and the semiconductor substrate is formed. A transistor forming step of forming a first interlayer insulating film so as to cover the first and second MIS type transistors on the first interlayer insulating film so as to be connected to the element regions of the first and second MIS transistors, respectively. A bit wiring forming step of forming the bit wiring of
And a second interlayer insulating film is formed on the first interlayer insulating film so as to cover the second bit wiring, and then the first, second and third ferroelectric films are formed on the second interlayer insulating film. A step of forming a ferroelectric capacitor for forming a body capacitor, and a third step on the second interlayer insulating film so as to cover the first, second and third ferroelectric capacitors.
A wiring structure forming step of forming a wiring structure in which the first, second and third ferroelectric capacitors are connected in series to the third interlayer insulating film after the interlayer insulating film is formed. It has a feature.

A twenty-fifth aspect of the present invention relates to a method of manufacturing a ferroelectric memory cell structure according to the twenty- fourth aspect, wherein the step of forming the ferroelectric capacitor includes a first conductor film, a ferroelectric film and a second conductor film. After the conductor films are sequentially formed to form a laminated film, the laminated film is patterned into a desired shape.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using the embodiments. First Embodiment FIG. 1 is a circuit diagram showing a configuration of a ferroelectric memory according to a first embodiment of the present invention, and FIG. 2 is a timing diagram for explaining a first operation control method of the same ferroelectric memory. FIG. 3 is a timing chart for explaining a second operation control method of the same ferroelectric memory,
FIG. 4 is a sectional view showing a ferroelectric memory cell structure used in the same ferroelectric memory, FIGS. 5 and 6 are process diagrams showing a method of manufacturing the same ferroelectric memory cell structure in the order of steps, and FIG.
8 and 9 are sectional views showing another example of the structure of the ferroelectric memory cell used in the same ferroelectric memory. As shown in FIG. 1, the ferroelectric memory 1 of this example has three first to third ferroelectric capacitors 39 to 41 connected in series and two MOS type transistors (memory cell transistors) 2.
A memory cell 2 configured to store 2-bit data is provided. The gate electrodes of the first MOS type transistor 25 and the second MOS type transistor 26 of the memory cell 2 are commonly connected to the word line WL1. As will be described later, the drain region 32 serving as one electrode of the first MOS type transistor 25.
Is connected to the bit line BL1A through the plug conductor 51 and the bit wiring 37, while the source region 31 which is the other electrode of the transistor 25 is connected to the first ferroelectric capacitor 39 through the plug conductor 57 and the local wiring 42. It is commonly connected to the second ferroelectric capacitor 40.

Further, as will be described later, the source region 33, which is one of the electrodes of the second MOS transistor 26, is connected to the bit line BL through the plug conductor 52 and the bit line 38.
The drain region 34, which is connected to 1B and serves as the other electrode of the transistor 26, is shared by the second ferroelectric capacitor 40 and the third ferroelectric capacitor 41 through the plug conductor 58 and the local wiring 43. It is connected. Furthermore, the first to third ferroelectric capacitors 39 to 41 connected in series are connected.
The first ferroelectric capacitor 39 of is connected to the plate line PL1A, and the third ferroelectric capacitor 41 of is connected to the plate line PL1.
Connected to B.

Similarly, the other memory cell 3 includes first to third three ferroelectric capacitors 9 to 11 connected in series and 2
MOS type transistor (memory cell transistor)
5 and 6 are configured to store 2-bit data. Here, the ferroelectric capacitors 9 to 11 and the transistors 5 and 6 are configured substantially the same as the ferroelectric capacitors 39 to 51 and the transistors 25 and 26 described above, respectively. The bit lines BL2B and BL3A are connected to the differential sense amplifier 23.

The bit line BL1A is a differential sense amplifier 2
1 and the bit line BL1B is connected to the differential sense amplifier 22. A reference potential is applied from the differential sense amplifier 21 via the bit line BL0B to the bit line BL1A, and a reference potential is applied from the differential sense amplifier 22 via the bit line BL2A to the bit line BL1B. Here, bit lines BL0B and B
A memory cell connected to the word line WL1 cannot be connected to L2A. For example, as shown in FIG.
The memory cell 3 connected to the bit line BL2A is not connected to the word line WL1 but is connected to the word line WL2.

Next, the first operation control method of the ferroelectric memory of this example will be described with reference to the timing chart of FIG. The description will be given in the order of the data read method and the data rewrite method. In the initial state, the word line WL1, the plate lines PL1A and PL1B, and the bit lines BL0B, BL1A, BL1B and BL2A are grounded. First, at time t1, the potential of the plate line PL1A is raised to Vcc (power supply potential).
Next, at time t2, the bit lines BL0B and BL1
A potential of A is raised to Vcc / 3, and at the same time, bit line B
Precharge the potentials of L1B and BL2A to 2Vcc / 3. Here, the bit lines BL0B, BL1A, BL1B, and BL2A may be precharged before the potential of the plate line PL1A is raised, but in this case, the plate line PL1A and the bit lines BL0B, BL1A, BL are used.
When the potential of the plate line PL1A rises due to coupling with 1B and BL2A, the precharged bit line BL
Since the potentials of 0B, BL1A, BL1B, and BL2A may change, as described above, the plate line PL1
It is desirable to raise the potential of A first.

Next, at time t3, the word line WL1
Potential is raised to a value higher than the value obtained by adding the threshold voltage of the memory cell transistor to Vcc. As a result, according to the data written in the first to third ferroelectric capacitors 39 to 41, the precharged bit lines BL1A and BL are
1B potential rises like a and c respectively,
It descends like b and d. Then, at time t4,
The differential sense amplifier 21 allows bit lines BL0B and B0
The potential difference between L1A is amplified, and the potential difference between the bit lines BL1B and BL2A is amplified by the differential sense amplifier 22. As a result, bit lines BL1A and BL1B
Each of the signals generated (read out) is bound to either Vcc or ground. With the above, the data read operation is completed.

Next, as described above, each ferroelectric capacitor 3
According to the data written in 9 to 41, the potentials of the precharged bit lines BL1A and BL1B are
The reason for rising like a and c or falling like b and d will be described. The data written in each of the ferroelectric capacitors 39 to 41 has two kinds of states depending on the direction of the remanent polarization of each of the ferroelectric capacitors 39 to 41. That is, the bit lines BL1A and BL1B and the plate line P are previously set.
A voltage is applied to each of the ferroelectric capacitors 39 to 41 connected in series by using L1A and PL1B, and when the voltage is removed, each ferroelectric capacitor 3 is applied according to the principle of the ferroelectric memory.
Remanent polarization occurs in 9 to 41. Here, for example, the data obtained when voltage is applied in the state where the potential on the bit line side is higher than that on the plate line side is 1, and conversely, when the voltage is applied when the potential is lower on the bit line side than the plate line side. The potential obtained by reading the bit lines BL1A and BL1B according to the data written in each of the ferroelectric capacitors 39 to 41 will be described with the obtained data as 0.

(1) When data 1 is written in the first ferroelectric capacitor 39 and data 1 is written in the third ferroelectric capacitor 41 In this case, by raising the potential of the plate line PL1A, A voltage is applied to the first to third ferroelectric capacitors 39 to 41, but the direction of the voltage is the same as that of the first ferroelectric capacitor 41 in the direction opposite to the writing direction. The same direction is applied to the dielectric capacitor 39. by the way,
Ferroelectric capacitors have the property that when a voltage is applied in the direction opposite to the direction in which remanent polarization is generated, the amount of change in polarization is greater than when a voltage is applied in the same direction. That is, when the voltage is applied in the opposite direction, the effective capacitance value becomes larger than when the voltage is applied in the same direction. Therefore, the third ferroelectric capacitor 41 is connected to the first ferroelectric capacitor 39.
It can be considered that the effective capacitance value is larger than that of Second
As for the ferroelectric capacitor 40, the effective capacitance value cannot be specified because a voltage is not applied at the time of writing, but it is equal to or larger than the capacitance value of the first ferroelectric capacitance 39 and the third ferroelectric capacitance 41. It can take only a value less than the capacity value of.

When a voltage is applied to the first to third ferroelectric capacitors 39 to 41 connected in series, the voltage applied to one of the ferroelectric capacitors decreases as the capacitance value increases. Therefore, the first to third ferroelectric capacitors 39 to
Compared with the case where all 41 have the same effective capacitance value, the voltage applied to the third ferroelectric capacitor 41 is lower and the voltage applied to the first ferroelectric capacitor 39 is higher.
When Vcc is applied between the plate lines PL1A and PL1B, if the effective capacitance values of the first to third ferroelectric capacitors 39 to 41 are equal, a voltage of Vcc / 3 is applied to each. In this case, a voltage lower than Vcc / 3 is applied to the third ferroelectric capacitor 41, and a voltage higher than Vcc / 3 is applied to the first ferroelectric capacitor 39. Therefore, the potential read to the bit line BL1A becomes higher than Vcc / 3 like a, and the potential read to the bit line BL1B becomes 2Vcc like c.
It will be higher than / 3.

(2) When data 0 is written in the first ferroelectric capacitor 39 and data 1 is written in the third ferroelectric capacitor 41 In this case, the data is written in the second ferroelectric capacitor 40 at the time of writing. Is also applied, the direction of the voltage is opposite between the first ferroelectric capacitor 39 and the third ferroelectric capacitor 41. Therefore, by increasing the potential of the plate line PL1A, the direction of the voltage applied from the third ferroelectric capacitor 41 to the first ferroelectric capacitor 39 is changed to the third ferroelectric capacitor 41.
For the second ferroelectric capacitor 40, in the same direction as for the second ferroelectric capacitor 40, and for the first ferroelectric capacitor 3
The opposite is true for 9. Therefore, the effective capacitance values are the first ferroelectric capacitance 39 and the third ferroelectric capacitance 41.
Becomes equal to, and from these values, the second ferroelectric capacitor 4
Since the value of 0 becomes small, the voltage applied to the first ferroelectric capacitor 39 and the third ferroelectric capacitor 41 becomes lower than Vcc / 3. Therefore, the potential read to the bit line BL1A becomes lower than Vcc / 3 like b, and the potential read to the bit line BL1B becomes 2Vcc like c.
It will be higher than / 3.

(3) When data 1 is written in the first ferroelectric capacitor 39 and data 0 is written in the third ferroelectric capacitor 41 In this case, the second ferroelectric capacitor 40 is written at the time of writing. Is also applied, the direction of the voltage is opposite between the first ferroelectric capacitor 39 and the third ferroelectric capacitor 41. Therefore, by increasing the potential of the plate line PL1A, the direction of the voltage applied from the third ferroelectric capacitor 41 to the first ferroelectric capacitor 39 is changed to the third ferroelectric capacitor 41.
In the same direction as in writing, in the same direction as in the second ferroelectric capacitor 40, and in the first ferroelectric capacitor 3
For 9 is the same direction. Therefore, the effective capacitance values are the first ferroelectric capacitance 39 and the third ferroelectric capacitance 41.
Becomes equal to, and from these values, the second ferroelectric capacitor 4
Since the value of 0 becomes large, the voltage applied to the first ferroelectric capacitor 39 and the third ferroelectric capacitor 41 becomes higher than Vcc / 3. Therefore, the potential read to the bit line BL1A becomes higher than Vcc / 3 like a, and the potential read to the bit line BL1B becomes 2Vcc like d.
It becomes lower than / 3.

(4) When data 0 is written in the first ferroelectric capacitor 39 and data 0 is written in the third ferroelectric capacitor 41 In this case, the data is written in the second ferroelectric capacitor 40 at the time of writing. Voltage is not applied. Therefore, by increasing the potential of the plate line PL1A, the third ferroelectric capacitor 41
The direction of the voltage applied to the first ferroelectric capacitor 39 is from the same direction as the writing to the third ferroelectric capacitor 41 and the opposite direction to the first ferroelectric capacitor 39. become.
Therefore, the effective capacitance value is the first ferroelectric capacitance 39
The third ferroelectric capacitor 41 becomes smaller than that of the first ferroelectric capacitor 39, the value of the second ferroelectric capacitor 40 is lower than that of the first ferroelectric capacitor 39, and the value of the third ferroelectric capacitor 41 is smaller than that of the third ferroelectric capacitor 41. Since it becomes higher than the capacitance value, the voltage applied to the first ferroelectric capacitor 39 becomes lower than Vcc / 3 and the third ferroelectric capacitor 41.
Is higher than Vcc / 3. for that reason,
The potential read to the bit line BL1A is Vc as in b
It becomes lower than c / 3, and the potential read to the bit line BL1B becomes lower than 2Vcc / 3 like d.

Next, the data rewriting method will be described. In order to rewrite data in the first to third ferroelectric capacitors 39 to 41, at time t5, the potential of the plate line PL1B is raised to Vcc, and then at time t7, the plate lines PL1A and PL1B are grounded. To do. Next, at time t8, the bit lines BL0B, BL1A,
BL1B and BL2A are grounded. As a result, the time t
5 to time t7, or time t7 to time t
In any of up to 8, depending on the data to be rewritten, between the plate line PL1A and the bit line BL1A and between the plate line PL1B and the bit line BL1B, that is, the first ferroelectric capacitor 39 and the third ferroelectric capacitor Vcc is applied between the ferroelectric capacitors 41 of.

Therefore, at time t8, V is present between the first ferroelectric capacitor 39 and the third ferroelectric capacitor 41.
Since cc is not added, the data retained by the remanent polarization is written. That is, when the read data is 1, the bit line potential is Vc
Since it is c, no voltage is applied to the ferroelectric capacitor from time t5 to time t7, and the ferroelectric capacitor is kept in a high potential on the bit line side from time t7 to time t8. Is applied and the voltage is removed at time t8, so that data 1 is written.

When the read data is 0, the bit line potential is grounded, so that the time t5.
From the time to the time t7, a voltage is applied to the ferroelectric capacitor with the potential on the plate line side being high, and the voltage is removed at the time t7, so that data 0 is written. Finally, at time t9, the word line WL1
The data rewriting operation is completed by grounding.

When writing data,
At time t6, the potential corresponding to the data is set to the bit line BL.
1A and BL1B, the same operation as data rewriting is performed after time t7.

Next, the second operation control method of the ferroelectric memory of this example will be described with reference to the timing chart of FIG. Note that the data read operation performed up to time t4 is substantially the same as the first operation control method in FIG. 2, and therefore its description is omitted. After that, when no voltage is applied to the second ferroelectric capacitor 40 at the time of writing, in order to bring the effective capacitance value of the second ferroelectric capacitor 40 closer to the optimum value, the word is written at time t5. Ground line WL1. Next, at time t6, the plate line PL1A is grounded, the potential of the plate line PL1B is raised to Vcc, and a voltage is applied to the first to third ferroelectric capacitors 39 to 41. Next, at time t7, the plate line PL1
By raising the potential of A to Vcc so that no voltage is applied to the ferroelectric capacitors 39 to 41, at time t8, the potential of the word line WL1 is set to Vcc, and the threshold voltage of the memory cell transistor is set to Vcc. Increase higher than the added value.

Thereafter, at time t9 to time t12, an operation substantially similar to the operation at time t6 to time t9 in the first operation control method of FIG. 2 is performed to complete the data rewriting or data writing operation. To do.

As described above, according to the ferroelectric memory of this example, the bit line potential at the time of reading data becomes higher or lower than Vcc / 3 in one bit line BL1A according to the data, while Since the other bit line BL1B has a value higher or lower than 2Vcc / 3, the reference potential for the bit line BL1A is set to Vcc / 3 and the reference potential for the bit line BL1B is set to 2Vcc / 3. Since it can be fixed, it is possible to always use the reference potential fixed to the optimum value. Therefore, a data identification error due to a change in the reference potential will not occur. According to the ferroelectric memory of this example, the first to third ferroelectric capacitors 39 to 41 connected in series and the two memory cell transistors 25,
26 and the memory cell 2 for storing 2-bit data is provided, the occupied area of the memory cell required for storing 1-bit data is equivalent to 1.5 ferroelectric capacitors. Decrease to.

Next, with reference to FIG. 4, a ferroelectric memory cell structure used in the ferroelectric memory of this example will be described. As shown in FIG. 4, this ferroelectric memory cell structure has, for example, an N-type source region 31 and a drain region 32 which selectively become element regions in a part of a P-type silicon substrate 30.
And the source region 31 and the drain region 3 are formed.
A gate electrode 35 made of polycrystalline silicon or the like is formed on the channel region between the gate electrode 35 and the gate electrode 2 via a gate oxide film 27. The entire surface including the gate electrode 35 is covered with a first interlayer insulating film 47 made of a silicon oxide film or the like, and the first M
The OS type transistor 25 is formed. Similarly, P
An N-type source region 33 and a drain region 34, which serve as element regions, are selectively formed on the other portion of the type silicon substrate 30, and a gate oxide film is formed on the channel region between the source region 33 and the drain region 34. A gate electrode 36 made of polycrystalline silicon or the like is formed via 28. Then, the entire surface including the gate electrode 36 is covered with a first interlayer insulating film 47 made of a silicon oxide film or the like, and the second MOS is formed.
The type transistor 26 is formed. Each of the first and second MOS type transistors 25 and 26 is used as a memory cell transistor as described above. Both the gate electrodes 35 and 36 are connected to the word line WL1. The N-type source region 31 and the N-type drain region 32, the N-type source region 33 and the N-type drain region 34, and
Have substantially the same function and are interchangeable with each other.

A first MO film is formed on the first interlayer insulating film 47.
The bit wiring 37 connected to the N-type drain region 32 of the S-type transistor 25 through the plug conductor 51, and the second
The bit line 38 connected to the N-type source region 33 of the MOS transistor 26 and the plug conductor 52 is formed. The bit lines 37 and 38 are connected to the bit line BL1A and the bit line BL1B, respectively, as described above.

The entire surface of the first interlayer insulating film 47 including the bit wirings 37 and 38 is covered with a second interlayer insulating film 48 made of a silicon oxide film or the like. This second interlayer insulating film 4
A first ferroelectric capacitor 39, a second ferroelectric capacitor 40, and a third ferroelectric capacitor 41 are formed on the surface 8.
The first to third ferroelectric capacitors 39 to 41 have a laminated structure including lower electrodes 39A to 41A, ferroelectric films 39B to 41B, and upper electrodes 39C to 41C, respectively. The lower electrodes 39A and 41A of the first and third ferroelectric capacitors 39 and 41 are connected to the plate lines PL1A and PL1B, respectively.

The entire surface of the second interlayer insulating film 48 including the first to third ferroelectric capacitors 39 to 41 is covered with a third interlayer insulating film 49 made of a silicon oxide film or the like. The third interlayer insulating film 49 is connected to the plug conductor 53 connected to the upper electrode 39C of the first ferroelectric capacitor 39, the lower electrode 40A and the upper electrode 40C of the second ferroelectric capacitor 40, respectively. The formed plug conductors 54 and 55 and the plug conductor 56 connected to the upper electrode 41C of the third ferroelectric capacitor 41 are formed. In addition, the first to third interlayer insulating films 47 to 4
9 has a first MOS so as to penetrate the entire film thickness.
A plug conductor 57 connected to the N-type source region 31 of the type transistor 25 and a plug conductor 58 connected to the N-type drain region 34 of the second MOS type transistor 26 are formed. Further, on the third interlayer insulating film 49, the local wiring 42 for connecting the plug conductors 53, 54 and 57.
Is formed and each plug conductor 55, 56 and 58 is formed.
A local wiring 43 is formed to connect to each other. Therefore, the first to third ferroelectric capacitors 39 to 41 are arranged so as to be connected in series with each other. The third interlayer insulating film 49 including the local wirings 42 and 43 is covered with a final insulating film 50 made of a silicon oxide film or the like and protected from the external atmosphere.

Next, a method of manufacturing the same ferroelectric memory cell structure will be described in the order of steps with reference to FIGS. First, as shown in FIG. 5A, a well-known photolithography method, an ion implantation method, or the like is used for a part and another part of a P-type silicon substrate 30, respectively,
N-type source region 31 and drain region 32, N-type source region 33 and drain region 3 that selectively become element regions
4, gate oxide film 27 and gate electrode 35, gate oxide film 28 and gate electrode 36 are formed. Next, a first interlayer insulating film 47 made of a silicon oxide film or the like is formed on the entire surface by the CVD method or the like to form the first and second MOS type transistors 25 and 26.

Next, as shown in FIG. 5B, the first MOS type transistor 25 is formed by photolithography.
Of the first interlayer insulating film 47 on the N-type drain region 32 and the N-type source region 33 of the second MOS transistor 26.
After forming contact holes in the
The plug conductors 51 and 52 are formed by embedding polycrystalline silicon or the like by the VD method or the like. Next, after forming aluminum or the like on the entire surface by the CVD method or the like, patterning is performed by the photolithography method to form the plug conductors 51, 5
Bit wirings 37 and 38 are formed so as to be respectively connected to the two.

Next, as shown in FIG. 6C, a second interlayer insulating film 48 made of a silicon oxide film or the like is formed on the entire surface by a CVD method or the like to cover the first interlayer insulating film 47. . Next, a first conductor film made of a polysilicon film and a second conductor film made of a ferroelectric film and a polysilicon film are sequentially formed and laminated on the entire surface by a CVD method or the like, and then patterned. Then, the first ferroelectric capacitor 39, the second ferroelectric capacitor 40 and the third ferroelectric capacitor 41 are formed. First
-Third ferroelectric capacitors 39 to 41 have a laminated structure including lower electrodes 39A to 41A, ferroelectric films 39B to 41B, and upper electrodes 39C to 41C, respectively.

Next, as shown in FIG. 6D, a third interlayer insulating film 49 made of a silicon oxide film or the like is formed on the entire surface by a CVD method or the like to cover the second interlayer insulating film 48. . Next, by photolithography, the upper electrode 39C of the first ferroelectric capacitor 39, the lower electrode 40A and upper electrode 40C of the second ferroelectric capacitor 40, and the upper electrode of the third ferroelectric capacitor 41. Contact holes are formed in the third interlayer insulating film 49 on 41C, respectively. At the same time, contact is made so as to penetrate the entire thickness of the first to third interlayer insulating films 47 to 49 on the N type source region 31 and the drain region 34 of the first and second MOS transistors 25 and 26, respectively. Form a hole. Next, polycrystalline silicon or the like is embedded in each contact hole by the CVD method or the like to form the plug conductor 5
3 to 58 are formed respectively. Next, after forming aluminum or the like on the entire surface by the CVD method or the like, patterning is performed by the photolithography method to form each plug conductor 53, 54.
And a local wiring 42 for connecting the plug conductors 55, 57 and 58, and a local wiring 43 for connecting the respective plug conductors 55, 56 and 58.
To form. Then, the local wiring 4 is formed by the CVD method or the like.
A final insulating film 50 made of a silicon oxide film or the like is formed on the third interlayer insulating film 49 including the layers 2 and 43 to complete the ferroelectric memory cell structure of FIG.

FIG. 7 is a sectional view showing another example of the ferroelectric memory cell structure used in the ferroelectric memory of this example. The structure of this ferroelectric memory cell structure is largely different from that shown in FIG.
The point is that the wiring structure for connecting the three ferroelectric capacitors formed above in series is changed. That is, in this ferroelectric memory cell structure, as shown in FIG. 7, the lower electrodes of the first ferroelectric capacitor 39 and the second ferroelectric capacitor 40 are the common electrode 39A. The electrode 39A is connected to the local wiring 42 through the plug conductor 61. The upper electrode 39C of the first ferroelectric capacitor 39 is connected to the plate line PL1 through the plug conductor 62 and the local wiring 45.
It is connected to A.

Lower electrode 41A of the third ferroelectric capacitor 41
Is connected to the local wiring 43 through the plug conductor 66, and the plug conductor 64, the local wiring 44, and the plug conductor 6 are connected.
3 to the upper electrode 40C of the second ferroelectric capacitor 40. The upper electrode 41C of the third ferroelectric capacitor 41 is connected to the plate line PL1B through the plug conductor 65 and the local wiring 46. This ferroelectric memory cell structure can be easily manufactured only by changing the laminated structure and wiring pattern of each ferroelectric capacitor in the manufacturing process of FIGS. 6C and 6D. .. Other than this, the ferroelectric memory cell structure of FIG. 4 described above is substantially the same. Therefore, in FIG. 7, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted.

FIG. 8 is a sectional view showing another example of the ferroelectric memory cell structure used in the ferroelectric memory of this example. The structure of this ferroelectric memory cell structure is largely different from that shown in FIG.
The point is that the wiring structure for connecting the three ferroelectric capacitors formed above in series is changed. That is, in this ferroelectric memory cell structure, as shown in FIG. 8, the lower electrodes of the first ferroelectric capacitor 39 and the second ferroelectric capacitor 40 are the common electrode 39A. The electrode 39A is connected to the first MOS transistor 2 through the plug conductor 67.
5 to the N-type source region 31. Also, the third
The lower electrode 41A of the ferroelectric capacitor 41 is a plug conductor 68.
Through the N-type drain region 34 of the second MOS-type transistor 26. Other than this, it is substantially the same as the ferroelectric memory cell structure of FIG. 7 described above.

As described above, according to the configuration of this example, the first to third three ferroelectric capacitors 39 to 4 connected in series are used.
1 and two first and second memory cell transistors 2
Since the memory cell 2 is constituted by 5 and 26 to store 2-bit data, the reference potential can be fixed in principle. Also, the occupied area of the memory cell required to store 1-bit data can be reduced to 1.5 ferroelectric capacitors. Therefore,
It is possible to reduce the occupied area of the memory cell necessary for storing 1-bit data without causing a data identification error due to the change in the reference potential.

Second Embodiment FIG. 9 is a circuit diagram showing the structure of a ferroelectric memory according to a second embodiment of the present invention, and FIG. 10 illustrates a first operation control method of the same ferroelectric memory. FIG. 11 is a timing chart for explaining a second operation control method of the same ferroelectric memory. As shown in FIG. 9, the ferroelectric memory 20 of this example has a plurality of ferroelectric capacitors C (1) connected in series.
To C (N + 1) and a plurality of MOS type transistors (memory cell transistors) Tr (1) to Tr (N). Gate electrodes of the MOS transistors Tr (1) to Tr (N) are commonly connected to the word line WL. One of the electrodes of each of the MOS transistors Tr (1) to Tr (N) is connected to the bit lines BLT (1) to BLT (N), while the other electrode of the transistors Tr (1) to Tr (N) is connected. The electrodes are commonly connected to both adjacent ferroelectric capacitors.

Ferroelectric capacitance C at one end of the plurality of ferroelectric capacitances C (1) to C (N + 1) connected in series.
(1) is connected to the second plate line PLB, and the ferroelectric capacitor C (N + 1) at the other end is connected to the first plate line PLA.
It is connected to the. Bit lines BLN (1) to BLN
A reference potential is applied to each of (N) and each bit line B
LN (1) to BLN (N) and each bit line BLT (1)
To BLT (N) are differential sense amplifiers 71 (7).
1 (1) to 71 (N)). Here, when a certain value k is an integer from (1 to N), for example, a plurality of ferroelectric capacitors C (k) to C connected in series are used.
The common contact of (k + 1) is a MOS transistor Tr
It is connected to the bit line BLT (k) via (k).

Next, referring to the timing chart of FIG.
A first operation control method of the ferroelectric memory of this example will be described. The description will be given in the order of the data read method and the data rewrite method. In the initial state, the word line WL, the plate lines PLA and PLB, the bit line B
LT (1) to BLT (N) and BLN (1) to BLN
(N) is grounded. First, at time t1, the potential of the plate line PLA is raised to Vcc, and then at time t2, the bit lines BLT (k) and BL.
The potential of N (k) is precharged to kVcc / (N + 1). Here, the bit lines BLT (k) and BLN (k) may be precharged before the potential of the plate line PLA is raised, but in this case, the plate line PLA and the bit line BLT (k). ) And BLN (k), the potentials of the precharged bit lines BLT (k) and BLN (k) may change when the potential of the plate line PLA rises. First, it is desirable to raise the potential of the plate line PLA first.

At time t3, the potential of word line WL is raised to a level higher than Vcc plus the threshold voltage of the memory cell transistor. As a result, the precharged bit lines BLT (k) respectively rise like e or fall like f according to the data written in the ferroelectric capacitors C (1) to C (N). . Then, at time t4, the bit lines BLT (k) and BLN
The differential sense amplifier 71 coupled to the group (k) amplifies the potential difference between the bit lines BLT (k) and BLN (k) to generate a signal generated on the bit line BLT (k) at Vcc. Or ground it either. With the above, the data read operation is completed.

Next, the data rewriting method will be described. In order to rewrite data in the ferroelectric capacitors C (1) to C (N + 1), the potential of the plate line PLB is raised to Vcc at time t5, and then the plate lines PLA and PLB are grounded at time t7. To do. Next, at time t8, the bit lines BLT (k) and BLN
Ground (k). As a result, from time t5 to time t7
Or between time t7 and time t8, the voltage Vcc is applied to the ferroelectric capacitors C (1) to C (N) according to the data to be rewritten,
At time t8, no voltage is applied to the ferroelectric capacitors C (1) and C (N), so that the data retained by the remanent polarization is written. Further, a potential difference between BL (k-1) and BL (k) is added to the ferroelectric capacitance C (k) (k = 2 to (N-1)) depending on the data. Finally, at time t9, the word line WL is grounded to complete the data rewriting operation.

When writing data,
At time t6, the potential corresponding to the data is set to the bit line BL.
Given to (k), after time t7, the same operation as data rewriting is performed.

Next, referring to the timing chart of FIG.
A second operation control method of the ferroelectric memory of this example will be described. Note that the data read operation performed up to time t4 is substantially the same as the first operation control method in FIG. 10, and therefore its description is omitted. After that, when no voltage is applied to the ferroelectric capacitors C (1) to C (N) at the time of writing, the effective capacitance value of the ferroelectric capacitors C (1) to C (N) is set to a more optimal value. In order to be close, the word line WL is grounded at time t5. Next, at time t6, the plate line PLA is grounded, and the potential of the plate line PLB is raised to Vcc, so that the ferroelectric capacitors C (1) to C (C).
Apply voltage to (N). Next, at time t7, by raising the potential of the plate line PLA to Vcc,
After no voltage is applied to the ferroelectric capacitors C (1) to C (N), at time t8, the potential of the word line WL is set higher than the value obtained by adding Vcc to the threshold voltage of the memory cell transistor. To raise.

After that, at the time t9 to the time t12, the data rewriting or the data writing operation is completed by performing substantially the same operation as the operation from the time t6 to the time t9 in the first operation control method of FIG. To do.

As described above, also with the configuration of this example, substantially the same effects as those described in the first embodiment can be obtained.

The embodiment of the present invention has been described in detail above with reference to the drawings. However, the specific structure is not limited to this embodiment, and there are design changes and the like within a range not departing from the gist of the present invention. Also included in the present invention. For example, the bit wiring of the ferroelectric memory cell structure used in the ferroelectric memory is not limited to the example of being arranged at the lower position of the three ferroelectric capacitors, but may be in the same layer as the local wiring or the plate line, or the interlayer insulating film. You may make it arrange | position in the upper position rather than it through. The interlayer insulating films are not limited to silicon oxide films, but may be BSG (Boro-Silicate Glass) films, PSG (Phosph).
o-Silicate Glass) film, BPSG (Boro-Phospho-Silica
Another insulating film such as a te glass) film can be used.

The gate insulating film is an oxide film (Oxide Fi
Not limited to lm), a nitride film (Nitride Film) may be used, or a double film structure of an oxide film and a nitride film may be used. That is, as long as it is a MIS (Metal Insulator Semiconductor) type transistor, not only a MOS type transistor but also an MNS (Metal Nitride Semiconductor) type transistor may be used.
de Semiconductor) type transistor may be used. Further, the conductivity type of the semiconductor substrate or each semiconductor region may be reversed between P type and N type. That is, the invention can be applied not only to the N-channel type but also to the P-channel type MIS type transistor.
Further, the materials such as the insulating films and the conductor films, the film forming method, and the like are merely examples, and can be changed depending on the use, purpose and the like.

[0081]

As described above, according to the ferroelectric memory and the control method thereof, and the ferroelectric memory cell structure and the control method thereof according to the present invention, three ferroelectric capacitors and two ferroelectric capacitors connected in series are used. Since the unit memory cell is configured by the individual memory cell transistors to store 2-bit data, the reference potential can be fixed in principle. Further, the occupied area of the unit memory cell required for storing 1-bit data can be reduced to 1.5 ferroelectric capacitors. Therefore, without causing a data identification error due to a change in the reference potential,
It is possible to reduce the occupied area of the unit memory cell required for storing 1-bit data.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a ferroelectric memory that is a first embodiment of the present invention.

FIG. 2 is a timing diagram illustrating a first operation control method of the same ferroelectric memory.

FIG. 3 is a timing diagram illustrating a second operation control method of the same ferroelectric memory.

FIG. 4 is a cross-sectional view showing a structure of a ferroelectric memory cell used in the same ferroelectric memory.

FIG. 5 is a process drawing showing a method of manufacturing the same ferroelectric memory cell structure in the order of processes.

FIG. 6 is a process chart showing a method of manufacturing the same ferroelectric memory cell structure in the order of processes.

FIG. 7 is a cross-sectional view showing another example of a ferroelectric memory cell structure used in the same ferroelectric memory.

FIG. 8 is a cross-sectional view showing another example of a ferroelectric memory cell structure used in the same ferroelectric memory.

FIG. 9 is a circuit diagram showing a configuration of a ferroelectric memory that is a second embodiment of the present invention.

FIG. 10 is a timing diagram illustrating a first operation control method of the same ferroelectric memory.

FIG. 11 is a timing diagram illustrating a second operation control method of the same ferroelectric memory.

FIG. 12 is a circuit diagram showing a conventional ferroelectric memory.

FIG. 13 is a circuit diagram showing a conventional ferroelectric memory.

[Explanation of symbols]

1, 20 Ferroelectric memory 2, 3 Memory cells 21, 22, 23, 71, 71 (1) to 71 (N)
Differential type sense amplifiers 25, 26, Tr (1) to Tr (N) MOS type transistors (memory cell transistors) 27, 28 Gate oxide films 31, 33 Source regions 32, 34 Drain regions 35, 36 Gate electrodes 37, 38 Bit wiring 39 First ferroelectric capacitance 40 Second ferroelectric capacitance 41 Third ferroelectric capacitance 42 to 46 Local wiring 47 First interlayer insulating film 48 Second interlayer insulating film 49 Third interlayer Insulating film 50 Final insulating films 51 to 58, 61 to 68 Plug conductors C (1) to C (N + 1) Ferroelectric capacitors WL1, WL2, WL Word lines BL0B, BL1A, BL1B, BL2A, BL2B,
BLT (1) to BLT (N), BLN (1) to BLN
(N) ... Bit lines PL1A, PL1B, PL2A, PL2B, PLA, P
LB plate line

Claims (25)

(57) [Claims] 1. A ferroelectric memory for storing data by utilizing a polarization phenomenon of a ferroelectric, comprising: first, second and third ferroelectric capacitors connected in series; , A first and a second two memory cell transistors form a memory cell, and among the three ferroelectric capacitors, the first and second ferroelectric capacitors connected to each other Electrodes of both are connected to a first bit line through the first memory cell transistor,
And the electrodes of the third ferroelectric capacitor on the mutually connected side are both connected to the second bit line through the second memory cell transistor, and the first and second memory cell transistors are common. A ferroelectric memory characterized by being connected to a word line of. 2. A first plate line is connected to an electrode on the side to which the bit line of the first ferroelectric capacitor is not connected, and a bit line of the third ferroelectric capacitor is connected to it. the absence of side electrodes ferroelectric memory according to claim 1, wherein the second plate line is connected. 3. A first reference potential applying bit line corresponding to the first bit line and a second reference potential applying bit line corresponding to the second bit line are provided, and the first reference potential applying bit line corresponding to the first bit line is provided.
And the first reference potential applying bit line are connected to the first differential sense amplifier, and the second bit line and the second reference potential applying bit line are connected to the second differential sense amplifier. claim, characterized in that it is connected to the amplifier 1 or
2. The ferroelectric memory as described in 2 . 4. A memory cell is constituted by three first, second, and third ferroelectric capacitors connected in series, and two first and second memory cell transistors, wherein
Of the ferroelectric capacitors, the electrodes of the first and second ferroelectric capacitors, which are connected to each other, are both connected to the first bit line via the first memory cell transistor, The electrodes on the mutually connected sides of the second and third ferroelectric capacitors are both connected to a second bit line via the second memory cell transistor, and the first and second memory cells are connected. A transistor is connected to a common word line, a first plate line is connected to an electrode on the side not connected to the bit line of the first ferroelectric capacitor, and a bit of the third ferroelectric capacitor is connected. A method for controlling the operation of a ferroelectric memory, wherein a second plate line is connected to an electrode on the side not connected to the line, wherein the polarization direction of the first ferroelectric capacitor is set, Data read on the first bit line Writing the data, including the step of storing the data and the step of storing the data read to the second bit line by setting the polarization direction of the third ferroelectric capacitor. Method for controlling operation of ferroelectric memory. 5. The first and second lines for the word line
Applying a voltage between the first plate line and the first bit line and between the second plate line and the second bit line while applying a voltage for turning on the memory cell transistor of 5. The operation control method of the ferroelectric memory according to claim 4 , wherein the polarization directions of the first and third ferroelectric capacitors are set by the method. 6. After the data is read, the first line is applied in a direction opposite to that of the data read in a state in which a voltage for turning off the first and second memory cell transistors is applied to the word line. After the step of changing the direction and magnitude of polarization of the first ferroelectric capacitor to the third ferroelectric capacitor by applying a voltage between the plate line and the second plate line, The method according to item 5,
5. The method of controlling the operation of the ferroelectric memory according to claim 4, wherein the polarization direction of the third ferroelectric capacitor is set. 7. A memory cell is constituted by three first, second, and third ferroelectric capacitors and two first and second memory cell transistors connected in series, and the three memory cells are connected to each other.
Of the ferroelectric capacitors, the electrodes of the first and second ferroelectric capacitors, which are connected to each other, are both connected to the first bit line via the first memory cell transistor, The electrodes on the mutually connected sides of the second and third ferroelectric capacitors are both connected to a second bit line via the second memory cell transistor, and the first and second memory cells are connected. A transistor is connected to a common word line, a first plate line is connected to an electrode on the side not connected to the bit line of the first ferroelectric capacitor, and a bit of the third ferroelectric capacitor is connected. A method for controlling an operation of a ferroelectric memory, wherein a second plate line is connected to an electrode on a side not connected to the line, wherein one of the first and second plate lines is set to a ground state. The first plate line and the second plate line. A voltage is applied to the rate line and a voltage for turning on the first and second memory cell transistors is applied to the word line, so that a voltage change according to written data is generated. A method of controlling the operation of a ferroelectric memory, characterized in that data is read out including the step of generating in the second bit line. 8. The voltage change occurring in the first and second bit lines is detected by a differential sense amplifier including a step of detecting a potential difference from another bit line precharged to a constant voltage. 8. The operation control method of a ferroelectric memory according to claim 7 . 9. The first plate line and the second plate line are used as a voltage value for precharging a bit line used for detecting a potential difference between one of the first and second bit lines. Between the first plate line and the second plate line as a voltage value for precharging the bit line used for detecting the potential difference from the other bit line by using approximately 1/3 of the voltage applied between 9. The operation control method for a ferroelectric memory according to claim 8 , wherein approximately 2/3 of the voltage applied between them is used. 10. A first, a second and a third connected in series.
Of the three ferroelectric capacitors and the first and second two memory cell transistors form a memory cell, and among the three ferroelectric capacitors, the first and second ferroelectric capacitors The electrodes on the mutually connected side of the body volume are both the first
Of the second and third ferroelectric capacitors connected to the first bit line through the second memory cell transistor, and the electrodes of the second and third ferroelectric capacitors connected to each other through the second memory cell transistor Of the first and second memory cell transistors are connected to a common word line, and the first electrode is provided on the electrode on the side not connected to the bit line of the first ferroelectric capacitor. A method of controlling operation of a ferroelectric memory, wherein a plate line is connected, and a second plate line is connected to an electrode on a side of the third ferroelectric capacitor to which a bit line is not connected, A step of setting the grounded plate line of the first or second plate lines to the same potential as the non-grounded plate line after reading the data;
Then, rewriting of data is performed by including the steps of grounding the first and second plate lines and then grounding the first and second bit lines. Operation control method. 11. A first, a second and a third connected in series.
Of the three ferroelectric capacitors and the first and second two memory cell transistors form a memory cell, and among the three ferroelectric capacitors, the first and second ferroelectric capacitors The electrodes on the mutually connected side of the body volume are both the first
Of the second and third ferroelectric capacitors are connected to the first bit line via the second memory cell transistor, and the electrodes of the second and third ferroelectric capacitors on the mutually connected side are connected to each other via the second memory cell transistor. Of the first and second memory cell transistors are connected to a common word line, and the first electrode is provided on the electrode on the side not connected to the bit line of the first ferroelectric capacitor. A method for controlling the operation of a ferroelectric memory, wherein a plate line is connected, and a second plate line is connected to an electrode of the third ferroelectric capacitor on the side where the bit line is not connected, After the data is read, in a state in which a voltage for turning off the first and second memory cell transistors is applied to the word line, the first plate line and the second plate line are moved in a direction opposite to that in the data read. plate A voltage is applied between the first ferroelectric capacitor and the third ferroelectric capacitor.
After the step of changing the polarization direction and the magnitude of the ferroelectric capacitance of (1), the grounded plate line of the first or second plate lines is the same as the non-grounded plate line. Applying a potential, then grounding the first and second plate lines, and then the first and second plates
And re-writing the data, including the step of grounding the bit line. 12. A ferroelectric memory for storing data by utilizing a polarization phenomenon of a ferroelectric, comprising a plurality of memory cell transistors and one more memory cell transistor connected in series. A memory cell is formed by the ferroelectric capacitor, and the electrodes of the kth (k is an integer) and the (k + 1) th ferroelectric capacitor of the ferroelectric capacitor on the side connected to each other are both kth. The memory cell transistor is connected to the kth bit line, the gate electrode of the memory cell transistor is connected to the common word line, and the first ferroelectric capacitor bit line is connected. The first plate line is connected to the electrode on the non-contact side, and the second plate line is connected to the electrode on the side not connected to the bit line of the final ferroelectric capacitor. Ferroelectric memory that. 13. A plurality of memory cell transistors,
A memory cell is formed by one more ferroelectric capacitor connected in series than the memory cell transistor, and the kth (k is an integer) and the (k + 1) th of the ferroelectric capacitors.
The electrodes on the mutually connected side of the th ferroelectric capacitor are both connected to the kth bit line via the kth memory cell transistor, and a common word line is used for the gate electrode of the memory cell transistor. The first plate line is connected to the electrode on the side to which the bit line of the first ferroelectric capacitor is not connected and the side to which the bit line of the final ferroelectric capacitor is not connected A method for controlling the operation of a ferroelectric memory, wherein a second plate line is connected to the electrode of the all plate lines in a state where a voltage for turning on the memory cell transistor is applied to the word line. A method of controlling the operation of a ferroelectric memory, wherein a polarization direction of the ferroelectric capacitor is set by applying a voltage between the bit line and a bit line to write data. 14. A plurality of memory cell transistors,
A memory cell is formed by one more ferroelectric capacitor connected in series than the memory cell transistor, and the kth (k is an integer) and the (k + 1) th of the ferroelectric capacitors.
The electrodes on the mutually connected side of the th ferroelectric capacitor are both connected to the kth bit line via the kth memory cell transistor, and a common word line is used for the gate electrode of the memory cell transistor. The first plate line is connected to the electrode on the side to which the bit line of the first ferroelectric capacitor is not connected and the side to which the bit line of the final ferroelectric capacitor is not connected A method for controlling the operation of a ferroelectric memory, wherein a second plate line is connected to an electrode of the memory cell, wherein after the data is read, a voltage for turning off the memory cell transistor is applied to the word line. In this state, by applying a voltage between the first plate line and the second plate line in the direction opposite to that at the time of reading data, the direction and magnitude of polarization of all ferroelectric capacitors are changed. 14. A method of controlling operation of a ferroelectric memory, comprising: setting a polarization direction of the ferroelectric capacitor by the method according to claim 13 after performing the step of performing data writing. 15. A plurality of memory cell transistors,
A memory cell is formed by one more ferroelectric capacitor connected in series than the memory cell transistor, and the kth (k is an integer) and the (k + 1) th of the ferroelectric capacitors.
The electrodes on the mutually connected side of the th ferroelectric capacitor are both connected to the kth bit line via the kth memory cell transistor, and a common word line is used for the gate electrode of the memory cell transistor. The first plate line is connected to the electrode on the side to which the bit line of the first ferroelectric capacitor is not connected and the side to which the bit line of the final ferroelectric capacitor is not connected A method of controlling operation of a ferroelectric memory, wherein a second plate line is connected to an electrode of the first plate line, wherein one of the first plate line and the second plate line is grounded. And a second plate line are applied, and a voltage for turning on the first and second memory cell transistors is applied to the word line, so that all the voltage changes according to the written data can be achieved. A method of controlling the operation of a ferroelectric memory, comprising the step of: reading the data including the step of generating the bit line. 16. The voltage change occurring in the first and second bit lines is detected by a differential sense amplifier including a step of detecting a potential difference from another bit line precharged to a constant voltage. 16. The operation control method of a ferroelectric memory according to claim 15 . 17. A voltage applied between the first plate line and the second plate line as a voltage value for precharging the bit line used for detecting the potential difference between the k-th second bit line and the bit line. 17. The method for controlling the operation of a ferroelectric memory according to claim 16 , characterized in that substantially k / (N + 1) is used. 18. A plurality of memory cell transistors,
A memory cell is formed by one more ferroelectric capacitor connected in series than the memory cell transistor, and the kth (k is an integer) and the (k + 1) th of the ferroelectric capacitors.
The electrodes on the mutually connected side of the th ferroelectric capacitor are both connected to the kth bit line via the kth memory cell transistor, and a common word line is used for the gate electrode of the memory cell transistor. The first plate line is connected to the electrode on the side to which the bit line of the first ferroelectric capacitor is not connected and the side to which the bit line of the final ferroelectric capacitor is not connected A method of controlling the operation of a ferroelectric memory, wherein a second plate line is connected to the electrode of the first plate line which is grounded after the data is read. Of the plate line of the same as the plate line of the one not grounded,
A method of controlling the operation of a ferroelectric memory, further comprising the step of grounding the first and second plate lines and the step of grounding all bit lines after that. 19. A plurality of memory cell transistors,
A memory cell is formed by one more ferroelectric capacitor connected in series than the memory cell transistor, and the kth (k is an integer) and the (k + 1) th of the ferroelectric capacitors.
Electrodes on the mutually connected side of the th ferroelectric capacitor are both connected to the kth bit line via the kth memory cell transistor, and a common word line is used for the gate electrode of the memory cell transistor. , The first plate line is connected to the electrode on the side to which the bit line of the first ferroelectric capacitor is not connected, and the side to which the bit line of the final ferroelectric capacitor is not connected A method of controlling an operation of a ferroelectric memory, wherein a second plate line is connected to an electrode of the memory cell, wherein a voltage for turning off the memory cell transistor is applied to the word line after the data reading is performed. In this state, by applying a voltage between the first plate line and the second plate line in the direction opposite to that in reading data, the polarization direction and size of all ferroelectric capacitors are changed. The step of making the plate line which is grounded among the first or second plate lines the same potential as the plate line which is not grounded, and then the first and second plate lines. 2. A method of controlling the operation of a ferroelectric memory, comprising rewriting data including the step of grounding the plate line of 1. and the step of grounding all bit lines thereafter. 20. A ferroelectric memory cell in which a memory cell composed of first, second and third ferroelectric capacitors and first and second memory cell transistors is formed on a semiconductor substrate. A first M structure having a structure, which operates as the first memory cell transistor formed in a desired region on the semiconductor substrate.
The IS-type transistor and the second MIS-type transistor that operates as the second memory cell transistor are the first
First interlayer insulating film, and first and second bit wirings connected to the element regions of the first and second MIS transistors are formed on the first interlayer insulating film. The first and second bit lines are covered so as to cover the first and second bit lines.
A second interlayer insulating film is formed on the interlayer insulating film of
The first, second, and third ferroelectric capacitors are formed on the interlayer insulating film, and a wiring structure for connecting the first, second, and third ferroelectric capacitors in series is formed. A ferroelectric memory cell structure characterized by the above. 21. The ferroelectric memory cell structure according to claim 20 , wherein a buried wiring is formed to connect a part of the wiring structure to device regions of the first and second MIS transistors. . 22. A third interlayer insulating film is formed on the second interlayer insulating film so as to cover the first, second and third ferroelectric capacitors, and the third interlayer insulating film is formed on the third interlayer insulating film. 22. The ferroelectric memory cell structure according to claim 20, wherein the wiring structure is formed. 23. The first and claim 20, characterized in that a layered structure in which the upper and lower electrodes formed on both surfaces of each of the second and third ferroelectric capacitor, the ferroelectric film 21. The ferroelectric memory cell structure according to 21 or 22 . 24. A first MIS is formed on a desired region of a semiconductor substrate.
Forming a first transistor and a second MIS transistor and forming a first interlayer insulating film so as to cover the semiconductor substrate; and forming the first and second transistors on the first interlayer insulating film. First to be connected to the element regions of the MIS type transistor respectively.
And a second bit line forming step of forming a second bit line, and a second interlayer insulating film is formed on the first interlayer insulating film so as to cover the first and second bit lines, and then, Two
Ferroelectric capacitor forming step of forming first, second and third ferroelectric capacitors on the interlayer insulating film, and the first, second and third ferroelectric capacitors so as to cover the first, second and third ferroelectric capacitors. After forming a third interlayer insulating film on the second interlayer insulating film, a wiring structure for connecting the first, second and third ferroelectric capacitors in series is formed on the third interlayer insulating film. A method of manufacturing a ferroelectric memory cell structure, comprising: a wiring structure forming step. 25. In the ferroelectric capacitor forming step, a first conductor film, a ferroelectric film and a second conductor film are sequentially formed to form a laminated film, and then the laminated film is formed into a desired film. 25. The method of manufacturing a ferroelectric memory cell structure according to claim 24 , wherein patterning is performed into a shape.