JPS6297367A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To implement high integration density, by making the thickness of an insulating film directly beneath a contact region of a second conductor layer and an external wiring, which constitute a gate electrode, larger than the thickness of a second insulating film. CONSTITUTION:An electrode 43 is provided on an insulating film 42. Then a thick insulating film 50 is deposited. The part on the electrode 43 is made to remain. The surface of a substrate at a gate part is exposed, and a gate oxide film 47 is formed. At a part of the electrode 43 neighboring the MOS transistor, the thick insulating film 50 becomes thin. When data is written in the memory cells in (i) rows and (j) columns in this constitution, a voltage of -5 volts is applied to a substrate 41, and a voltage of +12 volts is applied to the electrode 43. Then, an inverted layer 44 is formed on the surface of the substrate 41. When a voltage of +12 volts is applied to an address selecting line or a column line 53, the potential of a gate electrode 48 becomes +12 volts. Thus the transistor is turned ON. Then the data is written in a memory element 45 from a digit line 46. Then, the column line 53 is made to be 0 volt and the transistor is turned OFF. Then the data is accumulated on a capacitor element 45. Thus, the reading and the writing can be performed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and particularly to a dynamic memory cell.

As this type of semiconductor memory device, one in which one memory cell is formed by one transistor is said to be one. This has a configuration as shown in the plan view in FIG. 1, and one equivalent circuit consists of two lines. The outline of the structure will be explained for one cell. A semiconductor substrate, such as a P-type Si substrate, has regions (LIJ) spaced apart from each other.

(12) is provided between the two areas, and a channel portion (13) is provided between the two areas.
) is formed. Polycrystalline Si lit (14) is provided on the channel portion with an insulating film interposed therebetween. This polycrystalline Si layer (14) becomes a gate electrode. Another insulating film is provided on this polycrystalline 8M layer (14).

All0 column line (16
) is connected. A MOS transistor consisting of the n+ region 11), (12) and gate electrode (14) is used for address selection.

On the other hand, a second polycrystalline Si layer (17) is provided on the semiconductor substrate via an insulating film, and a capacitive element (18) is formed between this Si layer (17) and the substrate. .

Furthermore, the n-region (11) is formed of a diffusion layer, for example, and serves as a digit line (19).

In such a memory cell, it is necessary to separate the gate electrode of the 1st address selection MO transistor from the polycrystalline Si serving as one electrode of the capacitive element, which increases the cell area. The area occupied by the contact holes that make contact between the column lines and the gate electrodes is wasted, and these lead to a decrease in the degree of integration or an increase in the area of memory cells, which is a problem with the recent trend toward higher integration of semiconductors. They are contradictory.

The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor memory device with high integration density.

Another object of the present invention is to provide a semiconductor memory device with a smaller memory footprint compared to the area occupied by memory cells.

Still another object of the present invention is to provide a semiconductor memory device capable of high-speed reading.

The details of the present invention will be explained below with reference to the drawings. Third
The figure is a plan view showing an embodiment of the apparatus of the present invention, and FIG. 4 is a sectional view taken along the line ■--■ in FIG. 3.

First, to explain the structure, for example, a relatively high resistance silicon substrate (41) is prepared as a semiconductor substrate. An insulating film such as silicon dioxide (
42], a first electrode (43) is provided.

As the insulating film, 8i0. ,Si,N,.

This first electrode (43) may be made of a polycrystalline Si″'c groove, which may be used in a suitable combination of AJzO3 and the like.

Its production is by the usual CVD (Chemical Va
This was carried out by the pour deposition method. Of course Mo, W, AA! It may be made of metal materials such as. By applying a positive voltage to the first'@-pole (43) with respect to the semiconductor substrate (rl), an n-type inversion layer (44) is formed on the substrate surface. This n-type inversion 1m (44)
and the @l electrode (43) as both electrodes, and a nine capacitor (4
5) is constructed.

On the other hand, an n+
There are 46 territorial areas. The n+ region 46) is
For example, it can be formed by the usual diffusion method. This n+ region 46) extends in a direction perpendicular to one paper surface and is used as a digit line.

Of course, the n+ region 46) may be manufactured by a method other than thermal diffusion, or may be made of a conductive material.

A second electrode (4B) is provided between the n+ region 46) and the inversion layer (44) via a gate insulating film (47). The gate insulating film (47) is 1, for example, 100O.
A thickness of Sin was used. Of course, other insulating materials may be used, and as the Wc2 electrode (48), polycrystalline S1
However, like the first electrode, a metal material such as Mo, W, or Aj may also be used. This @2 electrode becomes a gate electrode, and this gate electrode (48) and rl” region (46
), inversion li! (44), insulating film (47) and MOS)
Two registers (49) are configured.

The gate electrode (48) of this MOS) transistor (49)
) is extended in nine states on the @l electrode (43) via an insulating film (50).This insulating film (5o) is different from the gate insulating film (47) in that both P3 edge films are of the same quality. It is desirable to have a thickness of 4. For example, the thickness is 8000A and 9.The material of this insulating film (50) is A I20B, 8
It goes without saying that it may include i, N, etc. Insulating film (
50) the second @ pole (48) extending above and the first electrode (
It is desirable for high-speed operation that the capacitance (O3) of the portion sandwiched between the transistor (43) and the transistor (43) is as small as possible compared to the gate-to-substrate capacitance <, Cs) of the transistor (49).

For this purpose, the film thickness may be increased.

The insulating film (5o) may be made of a substance with a low dielectric constant. A protective insulating film (5X) is deposited on the gate electrode (48), and a predetermined opening (52) is provided in this film. Contact is made through this opening i (52) with the external wiring (53) that constitutes the column line. The position where the aperture (52) is provided is particularly important in the present invention.
It is important that it be provided on the i-pole (43).

FIG. 41 shows fIl in which the entire opening is placed on the first electrode. In the device of this embodiment, the area of the memory capacitor portion is 300μrn, which is the same as before! Despite the shortcomings, the area occupied by the memory cells can be reduced to about that of conventional devices. As a result, the main capacitance associated with the digit line is small, and the sensitivity is improved even if the same sense amplifier as the conventional one is used.

You can also improve your speed.

The main points of the method for manufacturing the storage device shown in FIG. 4 will be explained.

After providing the first electrode (43) on the insulating film (42), the thick insulating film (50) (Il--for example, by CVD method) is deposited, leaving at least the top of the first electrode (43).

MOS) Expose the surface of the gate part substrate of the transistor. Then, in this state, a gate oxide film (47) is formed by thermal oxidation.The part of the half-electrode (43) adjacent to the MOS transistor has a partial thickness of P! ) was removed and treated with acid, making it thinner.

Now, the memory cells having such a configuration are used in a matrix arrangement as shown in FIG. 5, for example. , in the figure, 101, 102, etc. indicate individual memory cells,
103 etc. indicate a sense amplifier. The memory cell 1 in row i and column j will now be explained in correspondence with FIG. A case will be described in which information is written to the memory cell in the i-th row and the j-th column. -5 Volt to the substrate (41), +12 V to the first electrode (43)
Apply olt. As a result, free electrons are generated on the surface of the substrate (41) to form an inversion layer (44,1).In this state, the address selection line or column line (53) VC
When +12 Vol t is applied, the transistor (
The voltage level of the gate electrode (48) of 49) is +12 Volff
i and the transistor turns on. As a result, data is written into the memory element (45) from the digital line (46).

Then, when the first column line (53) is set to QValt and the transistor is turned off, data is stored on the capacitor.

When such memory cells are arranged in a matrix to form a large capacity memory, the digit 4 (46) IC has a large capacity compared to the memory capacity (45) of the cell. At the ninth stage, it's time to reveal the entire memory information.

When a voltage is applied to the gate electrode (48) of the transistor (49) to open the gate, one load of the memory cell is masked by the capacitance of the digit line, making it difficult for the sense amplifier to sense it.Therefore, the capacitance of the memory cell is preferably larger than the capacity of digit i.Conversely, if the capacities of the memory cells are the same.

If the total raw capacity of the digit aKft can be made small, the sensitivity and speed can be improved.

This result is as described above.

Furthermore, a gate extension portion of a MOS transistor.

Since the capacitance between the first electrode (43) and the first electrode (43) is small, the parasitic capacitance Cpij of the memory cell is reduced as shown in the equivalent circuit in FIG.
will also be small. Therefore, even if the driving capacity of the first line [j] is small, it can be used. Furthermore, even if the first column line is made up of A1 or the like, it generally has distributed resistance and causes a delay of C time constant due to the capacitance of the memory cell. Since this C becomes small, high-speed reading and writing capabilities are achieved. In particular, it is effective in realizing large-capacity memory systems.

In the above embodiment, one inversion region (44 N) was formed, but if an n+ region is formed in advance at the very bottom of the first electrode, an inversion voltage can be particularly applied to the first electrode. This is no longer necessary.Also, it goes without saying that the present invention can be applied to p-channel devices instead of n-channel devices.

[Brief explanation of drawings]

Figure m1 is a schematic plan view of a conventional 1-transistor/l-cell memory device, the equivalent circuit diagram of the 21st threshold (shown in Figure 1), and Figure 3 illustrates the one-disaster array device of the present invention. 4 is a sectional view taken along the line ■-vL in FIG. 3, and FIG. 5 is a diagram for explaining the memory matrix array.
The figure is a companion equivalent circuit diagram explaining the present invention in detail. In the figure, 11.12...n+ region 13...channel portion. 14tx7...Polycrystalline Si, 15...Opening part, 16
. . . Column line, 18 . . . Storage element, 41 . . . p-
8t, 42・S t O,, 43-'@ l '1K4
ff1.44--anti-Eli), 45... capacitor, 46... n+ region, 47... gate insulating film, 48
...Second electrode, 49...MOS) transistor, 5
0... phase edge film, 51... seeding insulating film, 52... opening portion, 53... wiring, 101.102... memory cell. 103...Sense amplifier. Agent Patent Attorney Noriyuki Yudo
Kikuo Takehana

Claims (1)

[Claims] 1 conductivity type semiconductor substrate, and a first conductivity type semiconductor substrate on the surface of this semiconductor substrate.
a first conductor layer forming a capacitor electrode opposite to the first region and formed on the region via a first insulating film; and a first conductor layer formed on the semiconductor substrate at a distance from the first region and the semiconductor a second region having a conductivity type opposite to that of the substrate and forming a digit line; a first portion existing on the surface of the semiconductor substrate between the first and second regions via a second insulating film; a second conductive layer constituting a gate electrode having a second portion extending and provided on the first conductive layer via a third insulating film; a fourth insulating film that covers the semiconductor substrate and has an opening on the second portion of the second conductor layer;
The second portion of the gate electrode is provided on the fourth insulating film and is in contact with the second portion of the gate electrode through the opening, and includes an external wiring serving as a column line, and the second conductor layer and the external wiring are connected to each other. A semiconductor memory device characterized in that the thickness of the insulating film directly under the contact region is greater than the thickness of the second insulating film.