JPS6297368A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To implement high integration density, by making the thickness of an insulating film on a first dielectric layer larger than the thickness of a capacitor electrode. CONSTITUTION:A first electrode 43 is provided on an insulating film 42. Then a thick insulating film 50 is deposited. A part on the first electrode 43 is made to remain. The surface of a substrate at the gate part of an MOS transistor is exposed, and a gate oxide film 47 is formed. A part of the electrode 43 neighboring the MOS transistor is made thin. When data is written in memory cells in (i) rows and (j) columns in this constitution, a voltage of -5 volts is applied on the substrate 41 and a voltage of +12 volts is applied to the electrode 43. Then, an inverted layer 44 is formed on the surface of the substrate 41. Under this state, a voltage of +12 volts is applied to an address selecting line or a column line 53. Then the potential of a gate electrode 48 of the transistor 49 becomes +12 volts and the transistor is turned ON. The data is written in a memory element 45 from a digital line 46. Then, the column line 53 is made to be 0 volt and the transistor is turned OFF. The data is accumulated in a capacitor element 45. Thus the reading and the writing can be performed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device, and particularly to a dynamic memory cell.

As this type of semiconductor memory device, one in which one transistor constitutes one memory cell is known. This has a structure opposite to that shown in the plan view in FIG. 1, and one equivalent circuit is as shown in FIG. 2. The outline of the structure will be explained for one cell. For a semiconductor substrate, for example, a P-type S1 substrate,
n+ regions 0υ separated from each other.

([2) is provided between these two areas, and a channel portion (13
) is formed. Polycrystalline Si 19 (14) is provided on the channel portion with an insulating film interposed therebetween.

This polycrystalline S i 14 (14) becomes a gate electrode. Another insulating film is provided on this polycrystalline Si layer (14).

AJO column line (16) through a predetermined opening (15)
connected to. The n+ region (11) and (12) gate electrodes (MOS) transistors each having one gate electrode are used for address selection.

On the other hand, a second polycrystalline Si layer (17) is provided on the semiconductor substrate via an insulating film, and a capacitive element (18) is formed between this Si layer (17) and the substrate. .

Further, the n+ region 1υ is formed of, for example, a diffusion layer, and can be used as a digit line (19).

In such a memory cell, it is necessary to separate the gate electrode of the 0 address selection MO transistor 8) from the polycrystalline 8i which becomes one electrode of the capacitive element, resulting in a small cell area. In addition, the area occupied by the ninth contact ball, which makes contact between the column line and the gate electrode, is also wasted.This reduces the degree of integration or increases the memory cell area, which is a problem with the recent high integration of semiconductors. It is contrary to the direction.

The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor memory device with high integration density.

Another object of the present invention is to provide a semiconductor memory device having a large memory capacity compared to the area occupied by memory cells.

Still another object of the present invention is to provide a semiconductor memory device capable of high-speed reading.

The details of the present invention will be explained below with reference to the drawings and sounds. Third
The figure is a plan view showing the device 91 of the present invention, @4
The figure shows a sectional view taken along the line ■-■ of Figure @3.

First, to explain the structure, for example, a relatively high resistance p+ type silicon base @ (41) is prepared as a semiconductor substrate. A first snow pole (43) is provided on a part of this substrate via an insulating film such as silicon dioxide (42).The insulating film includes 8i0., Si, N, etc.

AI, 0. This first electrode (43) is made of polycrystalline 8i,
Its production is by the usual CVD (Chemical Va
pourDeposition) method f
0 Of course M o , W .

The first electrode (which may be made of a metal material such as AI)
By applying a positive voltage of 1 to 43) to the semiconductor substrate +1), an n-type inversion (44) is formed on the surface of the substrate.

This n-type inversion N! I (44) and the above @ 111. pole (4
3) are connected to both electrodes to form a t-capacitor (45).

On the other hand, an n medium region (46) is provided within the substrate, spaced apart from the n-type inversion layer (44). The n+ middle region 46) is
For example, this n+ region 46), which is formed by a conventional diffusion method, extends in a direction perpendicular to the plane of the paper and is used as a digit line.

Of course, the method for manufacturing the n+ region 46 may be other than thermal diffusion, and it may also be formed from a conductive material.

An @2 electrode (48) is provided between this n+ region 46) and the inversion 1 (44) via a gate insulating film (47). The gate insulating film (47) is 1, for example 100
OA thickness 8 i 0. was used. Of course, other insulating materials may be used.Although polycrystalline Si is used for the second electrode (48), metal materials such as Mo, W, Aj, etc. may be used for the first electrode. This second electrode serves as a gate electrode, p, this gate electrode (48), and n middle region (46).
), Anti-ET @ (44), P, R Membrane (47) To”?!
A transistor (49) is configured.

Gate electrode (48) of this MOS) transistor (49)
Is it on the 1st pole (43)? This insulating film (50) is preferably made thicker than the gate insulating film (47) when both insulating films are of the same quality. The material of this insulating film (50) is A120B, Si
,N.

Of course, it is also possible to include the following. A capacitance (C) extending over the insulating film (50) and sandwiched between the first pole (48) and the first pole (43) is connected to the transistor (
For high-speed operation, it is desirable to configure the capacitance to be as small as possible compared to the gate-to-plate capacitance (Cs) of 49).

Just in case, you can configure the film to be thicker.

The e-edge film (50) may be made of a material with a low dielectric constant. A protective insulating film (51) is coated on the gate electrode (48), and a predetermined opening (52) is provided in this film. Contact is made through this opening (52) with an external wiring (53) forming a column line. The provision of the opening (52) is particularly important in the present invention, and at least a portion of the opening is provided with the first fi pole (52).
43) It is essential that it be provided above.

FIG. 4 shows an example in which the entire opening is placed on the first snow pole. In such an implementation array H1, the area of the memory capacitance portion is set to 300 μm as in the conventional case, and the area occupied by the memory cell can be reduced to about the same as in the conventional device. Parasitic capacitance is reduced, and sensitivity is improved even when using the same sense amplifier as before.

The main points of the method for manufacturing the storage device shown in FIG. 4 will be explained below. After installing the first electrode (43) on the eq membrane (42).

A thick insulating film (50) is then deposited by, for example, the CVD method.

Then, at least the top of the electrode (43) is left, and the MOS
The gate portion of the transistor substrate 1M1i is exposed.

In this state, a gate oxide film (4
7) i form. 111th C pole (43) (7) MO
S The area adjacent to the transistor is due to photographic exposure.

Part of the thickness is gone - the membrane (50) is removed and oxidized in a state of mind, making it thinner.

Now, 5 memory cells having such a configuration are used in a matrix arrangement as shown in FIG.
o3ysrts sense amplifier is shown.

Now, the memory cells in the 1Ffj column will be explained in correspondence with FIG. A case will be described in which information is written to the memory cell in the i-th row and the j-th column. -5 Volt pi 1 electric current is applied to the substrate (41), and +12 Voltt is applied to the substrate (43). As a result, free electrons are induced on the surface of the V-substrate (41) and an inversion layer (44) is formed. In this state, when +12 Volt is applied to the selection line or column line (53) to address 1, the gate voltage (48) of the transistor (49) becomes +
127alt, and the transistor is turned on. As a result, data is written from the Digiline (46) into the memory element (45).

Then, when the column line (53) is set to □vott and the transistor is turned off, data is stored in the capacitive element (45).

When such memory cells are arranged in a matrix to form a large capacity memory, the digit line (46) has a large capacity compared to the memory capacity (45) of the cell. When the whole picture comes out.

Gate t! of transistor (49)! When a voltage is applied to the pole (48) to open the gate hft, the charge in the memory cell is masked by the capacitance of the digit line, making it difficult to sense it with the sense amplifier. Therefore, it is desirable that the capacitance of the memory cell be smaller than the capacitance of the digit line. Conversely, if the memory cells have the same capacity.

If the parasitic capacitance it associated with the digit line can be reduced, sensitivity and speed can be improved.

This result is as described above.

Furthermore, MO8) a gate extension of a transistor.

Since the capacitance between the first electrode (43) and the first electrode (43) is small, the parasitic capacitance Cpij of the memory cell is reduced as shown in the equivalent circuit in FIG.
will also be small. Even if the driving capacity of this refined single-row line (j) is small, it can now be used. Furthermore, even if the column line is constructed of AJ or the like, it generally has distributed resistance, and a delay in the CR time constant occurs due to the capacitance of the memory cell. The method of reducing C allows high-speed reading and writing, which is particularly effective for realizing large-capacity memory systems.

In the above embodiment, one inversion region (44) is formed, and if an n+ region is formed in advance under the first electrode, in particular, an inversion voltage can be applied to the first electrode. There's no need to speak. Furthermore, it goes without saying that the present invention can be applied to not only n-channel devices but also p-channel devices.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view of a conventional 1-transistor/l-cell memory device, FIG. 2 is an equivalent circuit diagram of the device shown in FIG. The plan view of the structure to be explained, Figure 4 is the ■-VLS sectional view of Figure 3, and Figure 5 is
The figure is a diagram for explaining a memory matrix arrangement, and the sixth figure is a tth equivalent circuit diagram explaining the present invention in detail. Referring to the figure, 11112...n+ region 13...channel portion. +4 Reference 17... Polycrystalline 8i, 15... Opening part, 1
6... Column line, 18... Capacitive element, 41... p
-st, 42...8i0! , 43... 11th pole, 4
4.--Inversion 1.45...Capacitor, 46...n
+ region 47... Kate insulating film, 48... Second electrode, 49... MO8) transistor, 50... Insulating film,
51... Protection, protective membrane, 52... Opening part, 53...
・Wiring, 1011102...Memory cell. 103...Sense amplifier. Agent Patent Attorney Nori Chika Yudo Kikuo Takehana

Claims (1)

[Claims] 1 conductivity type semiconductor substrate, and a first conductivity type semiconductor substrate on the surface of this semiconductor substrate.
a first conductor layer forming a capacitor electrode opposite to the first region and formed on the region via a first insulating film; and a first conductor layer formed on the semiconductor substrate at a distance from the first region and the semiconductor a second region having a conductivity type opposite to that of the substrate and forming a digit line; a first portion existing on the surface of the semiconductor substrate between the first and second regions via a second insulating film; a second conductive layer constituting a gate electrode having a second portion extending and provided on the first conductive layer via a third insulating film; a fourth insulating film that covers the semiconductor substrate and has an opening on the second portion of the second conductor layer;
External wiring exists on the fourth insulating film and is in contact with the second portion of the second conductive layer through the opening and serves as a column line, and the thickness of the third insulating film is A semiconductor memory device characterized in that the thickness is greater than the thickness of the capacitor electrode.