JPS6221273B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly to a method of manufacturing a dynamic memory cell.

As this type of semiconductor memory device, one in which one memory cell is configured with one transistor is known. This has a configuration as shown in a plan view in FIG. 1, and an equivalent circuit as shown in FIG. 2. The outline of the structure will be explained for one cell. A semiconductor substrate, for example, a P-type Si substrate, is provided with n ⁺ regions 11, spaced apart from each other.
12 is provided, and a channel portion 13 is provided between the two regions.
is formed. A polycrystalline Si layer 14 is provided on the channel portion with an insulating film interposed therebetween. This polycrystalline Si layer 14 becomes a gate electrode. Another insulating film is provided on this polycrystalline Si layer 14 and connected to Al column lines 16 through predetermined openings 15. The n ⁺ regions 11 and 12, the gate electrode 14
A MOS transistor consisting of is used for address selection.

On the other hand, a second layer is placed on the semiconductor substrate via an insulating film.
A polycrystalline Si layer 17 is provided, and a capacitive element 18 is formed between this Si layer 17 and the substrate.

Further, the n ⁺ region 11 is formed of a diffusion layer, for example, and serves as a digit line 19.

In such memory cells, for address selection
Since it is necessary to separate the gate electrode of the MOS transistor from the polycrystalline Si serving as one electrode of the capacitor, the cell area becomes large. Furthermore, the area occupied by the contact hole for making contact between the column line and the gate electrode was wasted. These results in a decrease in the degree of integration or an increase in the memory cell area, which is contrary to the recent trend towards higher integration of semiconductors.

The present invention has been made in view of the above points, and an object thereof is to provide a method for manufacturing a semiconductor memory device with high integration density.

Another object of the present invention is to provide a method for manufacturing a semiconductor memory device having a large memory capacity compared to the area occupied by the memory cells.

Still another object of the present invention is to provide a semiconductor memory device capable of high-speed reading.

Still another object of the present invention is to provide a method for manufacturing a semiconductor memory device, which allows gate electrodes to be obtained with high reliability.

Hereinafter, details of the present invention will be explained using the drawings. FIG. 3 is a plan view showing a memory cell manufactured according to the present invention, and a sectional view taken along the line -- in FIG. 3 is shown correspondingly.

First, to explain the structure, for example, a relatively high resistance p ⁺ type silicon substrate 4 is used as a semiconductor substrate.
1 is prepared. A first electrode 1 is formed on a part of this substrate via an insulating film, for example, a silicon dioxide film 42.
3 is provided. As the insulating film, SiO ₂ ,
A laminate in which Si ₃ N ₄ , Al ₂ O ₃ , etc. are appropriately combined may also be used. This first electrode 43 was made of polycrystalline Si. Its production is carried out using normal CVD (Chemical
This was done using the Vapor Deposition method.

Of course, it may be made of a metal material such as Mo.W.Al. By applying a positive voltage to the first electrode 43 with respect to the semiconductor substrate 1, an n-type inversion layer 44 is formed on the substrate surface. A capacitor 45 is constructed with this n-type inversion layer 44 and the first electrode 43 as both electrodes.

On the other hand, in the substrate apart from this n-type inversion layer 44,
An n ⁺ region 46 is provided. The n ⁺ region 46 is
For example, it is formed by a conventional diffusion method. this n ⁺
The area 46 extends in a direction perpendicular to the plane of the paper and is used as a digit line.

Of course, the n ⁺ region 46 may be manufactured by a method other than thermal diffusion, and may be made of a conductive material.

A second electrode 48 is provided between the n ⁺ region 46 and the inversion layer 44 with a gate insulating film 47 interposed therebetween. For the gate insulating film 47, SiO ₂ with a thickness of 1000 Å was used, for example. Of course, other insulating materials may also be used. Further, as the second electrode 48, polycrystalline Si
However, like the first electrode, metal materials such as Mo, W, and Al may also be used. This second electrode serves as a gate electrode, and the gate electrode 48, the n ⁺ region 46, the inversion layer 44, and the insulating film 47 constitute a MOS transistor 49.

Gate electrode 48 of this MOS transistor 49
extends over the first electrode 43 with an insulating film 50 interposed therebetween. This insulating film 50 is desirably thicker than the gate insulating film 47 if both insulating films are of the same quality. For example, the thickness is 8000 Å. Of course, the material of this insulating film 50 may include Al ₂ O ₃ , Si ₃ N ₄ or the like. The capacitance C ₂ of the portion sandwiched between the second electrode 48 extending on the insulating film 50 and the first electrode 43 is configured to be as small as possible compared to the capacitance C ₂ between the gate and the substrate of the transistor 49. is desirable for high-speed operation.

For this purpose, the film thickness may be increased, or
The insulating film 50 may be made of a material with a low dielectric constant. A protective insulating film 51 is deposited on the gate electrode 48, and a predetermined opening 52 is provided in this film. Then, contact is made in this opening 52 with external wiring 53 forming a column line. The position where the aperture 52 is provided is particularly important in the present invention, and it is important that the aperture is provided in the capacitor region on the surface of the semiconductor substrate, in the above example, on the inversion layer 44. FIG. 4 shows an example in which the entire opening is placed on the first electrode. In the device of this embodiment, although the area of the memory capacitor portion was set to 300 μm ² as in the conventional device, the area occupied by the memory cell could be reduced to about 1/3 to 1/2 of that of the conventional device. As a result, the parasitic capacitance associated with the digit line was reduced, and even if the same sense amplifier was used as before, sensitivity and speed were improved.

Next, a manufacturing method according to an embodiment of the present invention will be described. After providing the first electrode 43 on the insulating film 42, a thick insulating film 50 is deposited by, for example, CVD method. Then, at least the top of the first electrode 43 is left,
Expose the surface of the substrate at the gate of the MOS transistor. Then, in this state, a gate oxide film 47 is formed by thermal oxidation. of the first electrode 43
The portion adjacent to the MOS transistor is thin because it is oxidized with some of the thick insulating film 50 removed due to photographic exposure.

Since the thickness of the insulating film on the surface of the first electrode 43 is stepped in this way, the gate electrode 48 can be obtained with high reliability.

Now, memory cells having such a configuration are used in a matrix arrangement as shown in FIG. 5, for example. In the figure, 101, 101, etc. indicate individual memory cells, and 103, etc. indicate a sense amplifier. The memory cell in row i and column j will now be explained in conjunction with FIG. 4. A case will be described in which information is written to the memory cell in the i-th row and the j-th column. To the board 41-
5 Volt and +12 Volt are applied to the first electrode 43. As a result, free electrons are induced on the surface of the substrate 41 and an inversion layer 44 is formed. When +12 Volt is applied to the address selection line or column line 53 in this state, the potential of the gate electrode 48 of the transistor 49 becomes +12 Volt, and the transistor is turned on. As a result, data is written from the digit line 46 to the memory element 45.

Next, when the column line 53 is set to 0 Volt and the transistor is turned off, the data is transferred to the capacitive element 45.
is accumulated in

When such memory cells are arranged in a matrix to form a large capacity memory, the digit line 46 has a large capacity compared to the memory capacity 45 of the cell. Therefore, when reading memory information, if a voltage is applied to the gate electrode 48 of the transistor 49 to open the gate, the charge in the memory cell is masked by the capacitance of the digit line, making it difficult to sense with a sense amplifier. Therefore, it is desirable that the capacitance of the memory cell be larger than the capacitance of the digit line. Conversely, if the capacitance of the memory cells is the same, sensitivity and speed can be improved if the parasitic capacitance associated with the digit line can be reduced. This result is as described above.

Furthermore, since the capacitance between the gate extension part of the MOS transistor and the first electrode is small, the sixth
As shown in the equivalent circuit in the figure, the parasitic capacitance of the memory cell
Cpij also becomes small. Therefore, it is possible to use the column line j even if its driving capacity is small. Furthermore, even if the column line is made of Al or the like, it generally has distributed resistance, and a delay in the CR time constant occurs due to the capacitance of the memory cell. Since this C becomes small, it becomes possible to read and write at high speed. In particular, it is effective in realizing large-capacity memory systems.

In the above embodiment, the case where the inversion region 44 was formed was explained, but in advance, under the first electrode,
If the n ⁺ region is formed, there is no particular need to apply an inversion voltage to the first electrode. Furthermore, it goes without saying that the present invention is applicable to not only n-channel devices but also p-channel devices.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view of a conventional one-transistor/one-cell memory device, FIG. 2 is an equivalent circuit diagram of the device shown in FIG. 1, and FIG. 3 illustrates a device manufactured according to the present invention. Figure 4 is the 3rd floor plan for
FIG. 5 is a diagram for explaining the memory matrix arrangement, and FIG. 6 is an equivalent circuit diagram for explaining the effects of the present invention. In the figure, 11, 12...n ⁺ region, 13...channel part, 14, 17...polycrystalline Si, 15...opening part,
16... Column line, 18... Capacitive element, 41...
p ^- Si, 42... _SiO2 , 43...first electrode, 44
...Inversion layer, 45...Capacitor, 46...n ⁺
Region, 47... Gate insulating film, 48... Second electrode, 49... MOS transistor, 50... Insulating film, 51... Protective insulating film, 52... Opening portion, 53
... Wiring, 101, 102 ... Memory cell, 10
3...Sense amplifier.

Claims (1)

[Claims] 1 a conductive type semiconductor substrate, a capacitor electrode formed on a first region of the surface of the semiconductor substrate via a first insulating film and facing the first region, and a capacitor electrode spaced apart from the first region; a second region formed on a semiconductor substrate and having a conductivity type opposite to that of the semiconductor substrate and forming a digit line; and a second region existing on the surface of the semiconductor substrate between the first and second regions via a second insulating film. a gate electrode having a first portion and a second portion extending from the first portion and provided on the capacitor electrode with a third insulating film interposed therebetween; and covering the semiconductor substrate including the top of the gate electrode. At the same time, a fourth insulating film having an opening on the second portion of the gate electrode and the second portion of the gate electrode present on the fourth insulating film are in contact with each other through the opening and are connected to the column line. and an external wiring, wherein the opening exists on a capacitor region on the surface of the semiconductor substrate, and the capacitance between the capacitor electrode and the gate electrode is smaller than the capacitance between the gate electrode and the semiconductor substrate. A method for manufacturing a memory device, wherein thermal oxidation is performed with an oxide film deposited on the capacitor electrode, and the oxide film is applied to the exposed capacitor electrode and the semiconductor substrate between the first region and the second region. A method of manufacturing a semiconductor memory device, comprising forming a second insulating film thinner than an oxide film, and then forming a gate electrode extending from the second insulating film to the third insulating film.