JPS5810864B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to high integration of semiconductor memory devices, and in particular, to increasing the degree of integration of semiconductor memory devices, and in particular to increasing the degree of integration of semiconductor memory devices, and in particular, by adding a capacitance (hereinafter abbreviated as capacitance) for storing information between a switching transistor and an information transmission line. The present invention relates to a three-dimensionally arranged semiconductor memory device.

That is, an object of the present invention is to provide a semiconductor memory device which has a large storage capacity and a small memory cell area per bit by three-dimensionally arranging the capacity for storing information. .

Hereinafter, the present invention will be explained in detail in comparison with a conventional device.

A conventional memory cell is shown in FIG. 1 in a plan view and in FIG.
As shown in a conceptual cross-sectional view of a cut surface, diffusion layers 11 and 19 formed on a substrate 12 and an oxide film 1 for isolation between elements are shown.
3 and the subsequently formed oxide films 17a and 17b
, a storage capacitor forming electrode 15 made of polycrystalline silicon, a gate electrode 16 made of polycrystalline silicon as well, a phosphorus silicate glass (PSG) film 14, and an aluminum (Al) electrode 18 serving as a word line.

Of these, the switching transistor 1 is constituted by the gate electrode 16, the gate oxide film 17a, and the diffusion layers 11 and 19 that become the drain and source, and the polycrystalline silicon electrode 15, the oxide 17b, and the inversion layer formed on the surface of the substrate 12. 22 constitutes a storage capacity.

Note that in FIG. 1, 17a, 17b and 14 are omitted.

For simplicity, the oxide film 13 is still shown in FIGS. 3 and 7.
, 17° 17a, 17b are omitted.

Conventionally, the switching transistor 1, the storage capacitor formed by the electrode 15 and the inversion layer are on the same plane, and are simply arranged two-dimensionally.

In contrast, in the semiconductor memory device of the present invention, a storage capacitor is three-dimensionally arranged above at least the gate of a switching transistor.

As is well known, a switching transistor has at least a source region, a drain region, and a gate on a semiconductor substrate.

Next, one embodiment of the memory cell of the present invention will be described with reference to FIGS. 3 and 4.

Figure 3 is a plan view of this embodiment, and Figure 4 is YY' in Figure 3.
It shows a cross-sectional view.

First, an oxide film 13 and a gate oxide film 17 are provided on a predetermined semiconductor substrate 12, and impurities are diffused into the substrate 12 through small holes 23 provided in the gate oxide film 17, or by means of ion implantation. A region made of a diffusion layer 11 of a conductivity type different from that of the substrate 12 is provided, and then a region made of a diffusion layer 8 (drain) of the same conductivity type as the substrate is formed.

Thereafter, a conductive layer consisting of a second electrode 9 which forms a storage capacitance by directly contacting the diffusion region 8 through the small hole 23 of the gate oxide film 17 is provided, and an insulating film 10 is sandwiched thereon.
A conductive layer consisting of an electrode 18 is provided, and a storage capacitor is formed by the electrodes 9 and 18 and the insulating film 10.

Note that in this case, the Al electrode 18 forms a data line.

That is, conventionally, an electrode 15 for forming a storage capacitor was provided on the same plane as the switching transistor 1 and in contact with the diffusion layer 11.
In contrast, in the present invention, the electrode 9 for forming a storage capacitor connected to the diffusion layer 8 (drain) is connected to the switching transistor 1. They are stacked and a storage capacitor is formed between them and the Al electrode 18 which becomes a data line.

To be more specific, in this embodiment, the switching transistor 1 has a small contact hole 2 formed in the gate oxide film 17 to connect the diffusion layer 8 which becomes the drain and the electrode 9.
3, diffusion regions 8 and 11 are formed by self-aligned diffusion, a substrate 12, a gate oxide film 17, and a gate electrode 16 made of polycrystalline silicon.

Therefore, in the present invention, the storage capacitor can be stacked three-dimensionally above the switching transistor 1,
Furthermore, since both the storage capacitor and the switching transistor 1 can be formed in a self-aligned manner, the memory cell area per one bit can be significantly reduced.

For example, the dimension of one side of the square contact hole 23 is 2 μm, the mask alignment margin is 1 μm, the width of the polycrystalline silicon electrode (gate) 16 is 2 μm, and the width of the diffusion layers 11 and 19 is 3 μm.
μm, element spacing 2 μm, gate oxide film 17 thickness 100
0 Å, thickness of insulating film 10 500 Å, storage capacitance 0.04 p
F, the memory cell area per bit is 100
It becomes μm.

This area is only about 40% of the memory cell area of 247 μm 2 of a conventional memory fabricated using the same design values.

Note that the substrate 12 has a specific resistance of 3Ω in the case of FIGS. 3 and 4.
cm p-type silicon, resistivity 3 in Figures 5 and 6
It is n-type silicon of Ωcm.

Further, in both cases, the thickness of the oxide film 13 for isolation between elements is 1 μm, and the gate oxide films 17 and 17a.

17b is 1000 Å, polycrystalline silicon electrode 9°15.1
6 has a thickness of 3500 Å, and the Al electrode 18 has a thickness of 6000 Å.

The insulating film 10 is still a thermal oxide film of 500 Å, and the insulating film 14 is still a 500 Å thick thermal oxide film.
000 Å PSG film, also 20 is 3000 Å PSG film
It is a membrane.

Of course, the storage capacitors may be provided in multiple layers.

Next, the configuration of a memory circuit having such a structure according to the present invention will be explained by taking a one-transistor type MO3 random access memory as an example.

A conventionally known one-transistor type MOS random access memory is composed of a memory array section 6 and an amplifier section γ shown in FIG.

Here, information is written to and read from the storage capacitor 2 by opening and closing the switching transistor 1 using a voltage pulse applied from the word line 3, applying a voltage to the storage capacitor 2 from the data line 4, or by applying the voltage of the storage capacitor 2 to the storage capacitor 2. This is done by detecting.

In contrast, in the semiconductor memory device according to the present invention, as shown in FIG. 6, the storage capacitor 2 is inserted between the switching transistor 1 and the data line 4, and one end of the storage capacitor 2 is directly connected to the data The other end is connected to a line 4 and the other end is connected to a DC voltage source (including oV) 5 through a switching transistor 1.

In this case, the reading and writing of information in the storage capacitor 2 is carried out in the same manner as in the past. First, the word line 3 is selected, the switching transistor 1 is made conductive, and one end of the storage capacitor 2 is connected to the voltage supplied from the DC voltage source 5. Fixed to.

Thereafter, data line 4 is selected for writing and reading through amplifier 7.

Next, a plan view of another embodiment of the present invention is shown in FIG.
A sectional view taken along the -Z' cut plane is shown in FIG.

In this embodiment, as shown in the figure, by diffusing or ion-implanting impurities such as boron or phosphorus through a small hole 23 formed in a gate oxide film 17, a part of an n-type silicon substrate 12 is formed into a region 11 and 8, a polycrystalline silicon electrode 9' is formed.

Here, the polycrystalline silicon electrode 9' serves as one electrode of the storage capacitor, and also serves as the gate electrode of the switching transistor 1, as will be described later.

An insulating film 1 for forming a storage capacitor on this electrode 9'
By forming the electrodes 21 serving as 0 and data lines, the storage capacitor can be three-dimensionally stacked above the switching transistor 1, and the storage capacitor and the switching transistor can also be formed in self-alignment.

When the semiconductor memory device of this example is manufactured using the above-mentioned design values, the memory cell area per bit is 64 μm.
2, which is about 33% smaller than the memory cell area of 195 μm 2 of a conventional memory manufactured using the same design values.

However, the storage capacitance at this time is 0.024 pF.

The circuit configuration of the memory array section 6 and the amplification section 7 in this case is shown in FIG.

As shown in the figure, the gate of the switching transistor 1 is connected to the drain and the source, and switching is performed by using the diffusion layer 11 as a back gate.

As described above, according to the present invention, the degree of integration of a semiconductor memory device can be significantly improved by reducing the area of the memory cell, and the results are significant.

[Brief explanation of the drawing]

Figure 1 is a plan view of a conventional memory cell, and Figure 2 is its X-
3 is a plan view showing an embodiment of the memory cell according to the present invention, FIG. 4 is a sectional view taken along the section YY', and FIG. 5 is a conventional one. FIG. 6 is a circuit diagram of a one-transistor MOS random access memory using a memory cell according to the present invention, FIG. 7 is a circuit diagram using a memory cell according to the present invention, and FIG. 7 is another embodiment of a memory cell according to the present invention. Fig. 8 is a plan view showing the cutting plane Z.
-Z' cross-sectional view, FIG.
FIG. 2 is a circuit diagram of a transistor-type MOS random access memory. 8: Diffusion layer (drain), 9, 9': Storage capacitor formation electrode, 10: Insulating film, 11: Diffusion layer, 12: Semiconductor substrate,
13: Insulating film (oxide film), 14: Insulating film (PSG film),
16: Gate electrode, 17: Gate oxide film, 18: Al electrode, 20: Insulating film (PSG film), 21: Electrode, 23: Small hole.

Claims (1)

[Claims] 1. At least a source region provided on a predetermined semiconductor substrate;
A field effect transistor consisting of a drain region and a gate provided in a predetermined region on the semiconductor substrate via a gate insulating film; a first conductive layer provided on the gate in sequence via an insulating film in box 1; a second insulating film and a second conductive layer, one of the first conductive layer and the second conductive layer being at least one layer of accumulation connected to the source region or the drain region of the field effect transistor; 1. A semiconductor memory device comprising a capacity. 2. The device according to claim 1, wherein the first conductive layer contacts the source region or the drain region through the opening in the gate insulating film, and contacts the source region or the drain region through the first insulating film. A semiconductor memory device characterized in that the semiconductor memory device is provided on the gate of the field effect transistor so that at least a portion thereof overlaps with the gate. 3. In the device according to claim 2, the field effect transistor includes at least a first region of a first conductivity type formed in the predetermined semiconductor substrate and is formed surrounding the first region. a second region of a second conductivity type, the gate is provided corresponding to the second region, and the source region and the drain region are located outside the first region or the second region. A semiconductor memory device characterized in that it is formed by a region. 4. The device according to claim 1, wherein the gate is constituted by the first conductive layer, and the first insulating film is combined with the second insulating film. A semiconductor storage device. 5. In the device according to claim 4, the field effect transistor includes at least a first region of a first conductivity type formed in the predetermined semiconductor substrate and is formed surrounding the first region. and a second region of a second conductivity type, wherein the source region and the drain region are formed from regions outside the first region or the second region.