KR100266064B1 - Cascade type channel equalizer - Google Patents

Abstract

PURPOSE: A cascaded high speed channel equalizer is provided to embody a high speed channel equalizer having the optional number of taps by connecting a high speed channel equalizer in parallel. CONSTITUTION: A controller(170) controls a high speed channel equalizing operation. A tap delay section(110) receives a symbol to perform a high speed channel equalizing operation and delays the symbol by the set number of taps. A reference signal generator(160) generates a reference signal when a data of a tap location is outputted and compares a channel equalizing output signal with the reference signal to generate an error signal. A multiplexer(130) selectively multiplexes the error signal from the reference signal generator(160) and an error signal produced by an error producing algorithm. A tap counting upgrade section(140) selectively receives the delay signal from the tap delay section(110) and upgrades a received tap counting. A filter(120) selectively receives the delay signal from the tap delay section(110) and filters input data according to the tap counting of the tap counting upgrade section(140).

Description

Cascade type channel equalizer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed digital communication system, and more particularly, to a channel equalizer for compensating amplitude and phase distortion of a reception channel in a HDTV receiver of a grand alliance (GA) vertical side band (VSB) scheme.

In general, in a high-speed digital communication system, the biggest deterioration of the system performance is Inter-Symbol Interference (ISI) caused by linear distortion of a channel, non-ideal frequency response, and the like. It is the channel equalizer that removes such intersymbol interference so that the data transmitted from the transmitter can be recovered without error. That is, when the channel equalizer communicates in a multipath between the transmitter and the receiver, the channel equalizer detects that the distorted signal added to the original signal is continuously changing and adjusts the equalizer tap coefficient to cancel the channel distortion characteristic. It is to be able to restore the data correctly.

Algorithms used in such channel equalizers include Least Mean Square (LMS) and Recursive Least Square (RLS) algorithms, and there are various structures such as TDL (tapped delay line) and lattice (lattice) structure. Mainly use TDL structure using.

VSB, the modulation and demodulation method currently used in HDTV, uses only a real signal. Therefore, due to the high signal rate and the use of multiple levels, the multipath of the channel is a major cause of signal distortion. The range for compensating the distortion of the signal is determined by the signal rate and the number of equalizer taps. In HDTV, 256 taps can be used to compensate for the distortion due to the multipath of about 23 dB.

1 is a block diagram of a conventional high speed channel equalizer.

As shown, the control unit 10 for controlling the operation of the entire channel equalization; A forward tap delay unit 20 for delaying and outputting the input data transmitted from the NTSC interference cancellation filter in the VSB receiver by a set number of taps; A reference signal generator 30 generating a reference signal according to a time point at which the tap position data is output, and comparing the reference signal with the equalizer output signal to generate an error signal; A backward tap delay unit 40 delaying the reference signal output from the reference signal generator 30 by a set number of taps and outputting the delayed reference signal; A forward tap coefficient updating unit (50) for updating a coefficient of each forward tap according to an error signal output from the reference signal generator (30); A backward tap coefficient updating unit 70 for updating a coefficient of each backward tap according to the error signal output from the reference signal generator 30; A filter for filtering output data of the forward tap delay unit 20 and the backward tap delay unit 40 according to the coefficients updated by the forward tap coefficient updater 50 and the backward tap coefficient updater 70, respectively. It consisted of 90 parts.

In the above description, the forward tap delay unit 20 includes a plurality of delay units 21-1 to 21-68 for delaying and outputting input data and the delay units 21-1 to 21. (68)) multiplexers (22-1) to (22-17) for multiplexing the input data outputted with delay in each of four units sequentially, and the specific delay data on the input side. ) And a multiplexer 23 for multiplexing the input data output from four specific delayers which select to set a direct path between the specific delay RAM and the filter unit 90.

In addition, the reference signal generator 30 may include a reference signal generator 31 which generates a signal previously promised between both sides of the transmission and reception in the training mode as a reference signal, and the filter when the channel equalization operation is performed in a blind mode. The slicer 32 slicing the signal output from the unit 70 and outputting the expected transmission value, and the signals output from the reference signal generator 31 and the slicer 32 according to the determination signal of the training mode and the blind mode A multiplexer 33 for multiplexing and an error signal generator 35 for generating an error signal by comparing the signal output from the filter unit 70 with the signal output from the multiplexer 33 are provided.

The backward tap delay unit 40 includes a plurality of delay units (41-1) to (41-196) for delaying and outputting the reference signal output from the reference signal generator 30, and Consists of a plurality of multiplexers (41-1)-(41-49) that sequentially multiplex the data output by the delays (41-1)-(41-196) into four units sequentially. It became.

In addition, the forward tap coefficient updating unit 50 may include a plurality of 8 * 6 multipliers that multiply the plurality of input data output from the forward tap delay unit 20 and the error signals output from the reference signal generator 30. (51-1)-(51-16)) and one-to-one correspondence with the plurality of 8 * 6 multipliers ((51-1)-(51-16)) and symbolize data output from the 8 * 6 multiplier. A plurality of delayers (52-1)-(52-16) delaying according to an internal arithmetic clock fs4 at four times the clock fs, and the plurality of delayers (52-1)-( 52-16)) and a plurality of shifters (53-1)-(53-16) that correspond one-to-one to shift the output signal of each delayer according to the offset speed adjustment signal of the channel distortion characteristic (step). )) And a plurality of adders ((54-) that add one-to-one correspondence with the shifters (53-1) to (53-16) and add a signal shifted from each shifter to the coefficient value of the previous symbol. 1)-(54-16)) and the respective adders ((54-) 1)-(54-16)) and a plurality of delay units 55-1 of four units that sequentially delay the signals output from each adder through four delay units according to the internal operation clock fs4. )-(55-16), (56-1)-(56-16), (57-1)-(57-16), (58-1)-(58-16) and the above four units It is composed of a plurality of limiting / rounding units (59-1)-(59-16) corresponding to the delay unit in one-to-one and making the data through the four units of the delay unit to a predetermined size.

The backward tap coefficient updating unit 70 multiplies the plurality of reference signals output from the backward tap delay unit 40 and the error signals output from the reference signal generator 30, respectively. Data output from the 6 * 4 multiplier in one-to-one correspondence with a multiplier (71-1)-(71-48) and the plurality of 6 * 4 multipliers (71-1)-(71-48) A plurality of delays (72-1) to (72-48) for delaying a signal according to an internal operation clock fs4 at four times the symbol clock fs, and the plurality of delays (72-1). (72-48)) and a plurality of shifters (73-1)-(73) corresponding to one-to-one correspondence and shifting the output signal of each delayer according to the offset speed adjustment signal (step) of the channel distortion characteristic. -48)), the signal shifted from each shifter in one-to-one correspondence with the shifters (73-1)-(73-48), respectively, and the delay unit 75-1 of the unit of four units 75-48), (76-1)-(76-48), (77-1)-(77-48), (78-1)-(78-48) sequentially A plurality of adders (74-1)-(74-48) that add signals, and one-to-one correspondence with the adders (74-1)-(74-48) to output signals from each adder; 4 units of multiple delayers (75-1)-(75-48), (76-1)-(76-48), (4 units which sequentially delay through four delayers according to the internal operation clock (fs4) 77-1)-(77-48), (78-1)-(78-48), and one-to-one correspondence with the four units of the delay unit to make the data through the four units of the delay unit to a predetermined size Two limiting / rounding parts (79-1)-(79-48).

The filter unit 90 is multiplexed by the multiplexers 22-1 and 22-16 in the forward tap delay unit 20 according to the coefficients updated by the forward tap coefficient updater 50. And a forward filter 93 for filtering the input data to be output, and a multiplexer 42-1 in the backward tap delay unit 40 according to the coefficient updated by the backward tap coefficient updater 70. A backward filter unit 97 for filtering the input data multiplexed and outputted at (42-48), the signal filtered by the forward filter unit 93 and the backward filter unit 97, and the forward tap delay unit, respectively And an adder 98 that adds the signal of the reference tap output from the multiplexer 23 to generate a channel equalization output signal.

The operation of the conventional high speed channel equalizer configured as described above is as follows.

Prior to describing the operation, the structure of the GA VSB data frame applied to the fast channel equalizer will be described. As shown in FIG. 9, each field is divided into two fields composed of 313 segments, and one field is a segment. It consists of a sync signal and 312 segments of data. In addition, the segment is composed of a segment synchronization signal of 4 symbols and data of 828 symbols. Here, the field synchronization signal located at the beginning of each field is composed of a signal previously promised by both transmission and reception.

Table 1a below shows the input and output signals of the conventional channel equalizer.

NAME (pin count) TYPE FUNCTION fs input Symbol Clock (10.762 MHz) fs4 input Symbol clock (4 * fs) vin (8) input 8-bit input signal field_lock input Field sync lock control signal field_sync input Field sync flag (1 during 828 symbols) seg_sync input Segment Sync Flag (1 for 4 symbols) comb input Select comb filter mode (1 when passing comb filter) vsbmode input VSB mode selection signal (8VSB 0, 16VSB 1) even_odd input Data field mode selection (even field 0, odd field 1) / cs input Equalizer Chip Selection (Micom's Equalizer Chip Assignment Signal) / wr input Write strobe (Miccom's data write strobe) / rd input Read Strobe (Miccom's Data Read Strobe) addr (3) input Microcomputer address bus data (8) input Microcomputer data bus other_err (6) input Error calculated by algorithm different from inside chip bypass input Input pass strobe (1 on pass) freeze input Coefficient Fixed Strobe (1 at Coefficient Fixed) updaterr_sel input Count update error selection (internal error 0, external error 1) only_trainm_mode input Operation mode selection (1 when operating in train mode only) errout_mode_sel input Output error selection (1 when outputting only train errors) overlap input Select tab overlap (1 if overlap is allowed) tap_position (2) input Insert tap position (00:15 ^th tap, 01: 31 ^st tap, 10: 47 ^th tap, 11:62 ^nd tap step_train (2) input Train Mode Staff step_blind (2) input Blind Mode Staff update_start (2) input Coefficient update start position (00:45 symbol, 01:90 symbol, 10: 135 symbol, 11: 180 symbol) control_sel input Chip control selection (0 for pin control, 1 for microcomputer control) fsync_to_ptl output Field_synchronous output delayed by PTL block ssync_to_ptl output Segment_synchronous output delayed by PTL block out_error (6) output Error output vout (10) output Data output in PTL block

Next, when the operation of the conventional high-speed channel equalizer is described, first, data is received in a VSB receiver in units of frames, and the control unit 10 in the VSB receiver receives information about a data frame in a corresponding signal (field_lock, field_sync, segment_sync, even_odd, vsb_mode, comb) to control channel equalization.

That is, as shown in FIG. 8, the controller 10 controls the channel equalization operation to start when the data frame received signal A is activated, and the channel equalization operation in the training mode while the field synchronization signal of 828 symbols is received. Control to perform the channel equalization operation in the blind mode while the arbitrary data symbol is received.

Further, the forward coefficient updating unit 50 and the backward coefficient updating unit 70 do not allow the coefficient update because the channel equalization operation is started and the input error value is set to 0 for a predetermined period, and all coefficients are set to 0. It has the same effect as exporting the signal of the tap position as it is. In the conventional high speed channel equalizer, the time for allowing the coefficient update can be selected as 45, 90, 135, or 180 symbols after the first data of the first field sync signal is outputted to the tap position.

In addition, when switching from the training mode to the blind mode, the coefficient update is suppressed up to 256 symbols of the next segment, and when the transition from the blind mode to the training mode, the coefficient update resumes after a certain symbol.

In detail, the delay unit 21-1 in the forward tap delay unit 20 delays and outputs input symbol data, and the delayed symbol data is delayed through the next delay unit 21-2. Thus, the data frame transmitted from the transmitting side is delayed at every symbol clock fs by the forward tap delay unit 20. The multiplexers 22-1 to 22-17 then multiplex the delayed symbol data into four units, and the first to fifteenth multiplexers 22-1 to 22-15 The multiplexed signal is output to the forward filter unit 93, and the second to sixteenth multiplexers 22-2 to 22-16 output the multiplexed signal to the forward tap coefficient updater 50. The multiplexer 23 selects a reference tap to receive data transmitted from the transmitter from the user and outputs the signal of the reference tap to the filter unit 90.

The reference signal generator 30 outputs, as a reference signal, a symbol promised in advance between transmission and reception while receiving the first 700 symbols among the field synchronization signals of 828 symbols under the control of the controller 10.

The backward tap delay unit 40 delays 0 before a valid reference signal is output from the reference signal generator 30 at the beginning of chip operation. Then, after the first data of the first field synchronization signal is output to the tap position, the reference signal output from the reference signal generator 30 is delayed according to the symbol clock. The delayed reference signals are 49 multiplexers (42). Multiplexed via -1)-(42-49). Thus, the first to 48th multiplexers 42-1 to 42-48 transfer the multiplexed signal to the backward filter unit 97, and the second to 49th multiplexers 42-2 to ( 42-49 transmits the multiplexed signal to the backward tap coefficient updater 70.

Thus, the sixteen multipliers 91-1-91-16 in the forward filter unit 93 combine the coefficients output from the forward tap coefficient updating unit 50 and the symbol data output from the forward tap delay unit 20. Multiplying each, the Carry Save Ether (CSA) 92-1 adds the output signals of the 16 multipliers. Thus, the multiplexer 92-5 and the adder 92-3 convert the value output from the carry save ether 92-1 according to the internal operation clock fs4 at four times the symbol clock fs. And added.

At the same time, the 48 multipliers 95-1-95-48 in the backward filter unit 97 transmit the coefficients output from the backward tap coefficient update unit 70 and the backward tap delay unit 40. The multiplied signals are multiplied, and the carry save ether (CSA) 96-1 adds the output signals of the 48 multipliers 95-1 to 95-48. Thus, the multiplexer 96-5 and the adder 96-3 convert the value output from the carry save editor 96-1 according to the internal operation clock fs4 at four times the symbol clock fs. And added. The adder 98 thus outputs the output signal of the forward filter 93 and the backward filter 97 and the reference tap signal output from the forward tap delay section 20 to obtain the final output signal of the channel equalizer. In addition, the final signal of the channel equalizer is output.

Here, the control clock uses an internal operation clock fs4 that is four times the symbol clock fs, and the control signal ctrl also repeats four modes to share the same operation device. In other words, the 256-tap signal is calculated by dividing the 64-tap signal by 64 taps. If the signals of the new forward tap delay unit 20 and the backward tap delay unit 40 are added when the added values are accumulated, the reset function is performed by adding zeros rather than adding the previous accumulated values.

When the coefficient update is not allowed in the channel equalization initialization operation, but the coefficient update allowance time is selected after the first data of the first field sync signal comes out of the output of the tap position, the forward tap coefficient update unit 50 and the backward tap are selected. The coefficient updater 70 updates the coefficients.

That is, the error signal generator 35 in the reference signal generator 30 forwards the error signal, which is a difference signal between the channel equalization signal and the reference signal, output from the filter unit 90, and the forward tap coefficient update unit 50 and the backward. It transfers to the tap coefficient update part 70. FIG.

Then, the forward tap coefficient updater 50 updates the coefficient according to the error signal output from the reference signal generator 30. Here, the coefficient update using the LMS algorithm uses (Equation 1).

C _(k-1) = C _k + B _ek X _k

: k번째의 오차신호β: staff size

: kth error signal

: k번째의 입력신호

: kth input signal

In detail, the sixteen multipliers 51-1 to 51-16 in the forward tap coefficient updater 50 output an 8-bit input symbol and a 6-bit error signal output from the forward tap delay unit 20. The multipliers 53-1 to 53-16 perform a right shift of 5 to 8 bits in accordance with the offset speed control signal of the channel distortion characteristic. The 22-bit shifted data is transferred to the forward filter unit 93 sequentially through the adders 54-1 to 54-16, the delay unit, and the limiting / rounding unit.

In addition, the backward tap coefficient updating unit 70 also operates in the same manner as the coefficient updating operation method of the forward tap coefficient updating unit 50 to update the coefficients.

Then, the forward filter unit 93 in the filter unit 90 filters the input symbol output from the forward tap delay unit 20 according to the coefficient output from the forward tap coefficient updater 50, and the backward filter unit ( 97 is to filter the reference signal output from the backward tap delay unit 40 according to the coefficient output from the backward tap coefficient updater 70. In this way, the adder 98 generates a channel equalization output signal by adding the signals output from the forward filter 93 and the backward filter 97 and the signals of the reference taps output from the forward tap delay unit 20, respectively. do. In this manner, the channel distortion characteristic is canceled by updating the tap coefficient with the error signal between the channel equalization output signal and the reference signal, and performing the channel equalization operation with the updated tap coefficient.

When the field sync signal of the 828 symbol is received and any data symbol is received thereafter, the controller 10 controls to perform the channel equalization operation in the blind mode.

Thus, the slicer 32 in the reference signal generator 30 slices the received data to estimate the transmission data, and outputs the estimated data to the backward tap delay unit 40 as a reference signal. The error signal generator 35 generates an error signal that is a difference signal between the channel equalization signal and the estimated signal output from the filter unit 90, and the forward tap coefficient updating unit 50 and the backward tap coefficient updating unit 70. Output to. The forward tap coefficient updating unit 50 and the backward tap coefficient updating unit 70 then update the coefficients so that the channel distortion characteristics are canceled, and the filter unit 90 causes the data to cancel the channel distortion characteristics. Will be filtered.

Here, rather than performing the blind mode channel equalization operation so that the channel distortion characteristic is canceled only with the data received without knowing the data transmitted from the transmitting side, the receiving side knows the transmission data from the transmitting side in advance, and thus the channel distortion characteristic. It is more efficient to perform the training mode channel equalization operation so that this is offset.

Thus, the high-speed channel equalizer automatically operates to equalize the channel distortion characteristics of the training mode and the blind mode according to the received data frame.

However, such a conventional fast channel equalizer needs to change both the number of taps of the forward tap coefficient updating unit 50, the backward tap coefficient updating unit 70, and the filter unit 90 in order to change the number of taps. There are a lot of complexities in implementing a large number of fast channel equalizers.

SUMMARY OF THE INVENTION An object of the present invention is to solve the conventional problems as described above. In particular, by cascading a fast channel equalizer having a certain number of taps in series, a cascaded fast channel equalizer capable of implementing an arbitrary number of taps can be achieved. To provide a flag.

The present invention to achieve the above object,

A controller for controlling a fast channel equalization operation;

A tap delay unit having a predetermined number of taps to perform a fast channel equalization operation in units of set taps, and receiving and outputting a symbol for performing the fast channel equalization operation by a set number of taps;

A reference signal generator for generating a new reference signal according to the control of the controller according to the timing at which the tap position data is output, and comparing the reference signal with a channel equalization output signal to generate an error signal;

A multiplexer for selectively multiplexing an error signal generated by the error generation algorithm different from the error signal generated by the reference signal generator under the control of the controller;

A tap coefficient updating unit for selectively receiving a signal delayed by the tap delay unit, and updating the tap coefficient according to the error signal output from the multiplexer using the received signal;

High-speed channel equalization having a predetermined number of taps by selectively receiving a signal delayed by the tap delay unit, filtering the received data according to the tap coefficients of the tap coefficient updating unit, and extending the number of taps by a set number of taps. The technical features of the present invention include a filter unit for generating a final equalization output signal having a desired number of taps by adding the channel equalization output signal by the other input symbol and the filtering data so as to implement the device.

1 is a block diagram of a conventional high speed channel equalizer;

2 is a detailed configuration diagram of a forward tap delay unit of FIG. 1;

3 is a detailed configuration diagram of a backward tap delay unit of FIG. 1;

4 is a detailed block diagram of the filter unit of FIG. 1;

5 is a detailed configuration diagram of the reference signal generator of FIG. 1;

6 is a detailed configuration diagram of the forward tap coefficient updater of FIG. 1;

7 is a detailed configuration diagram of the backward tap coefficient updater of FIG. 1;

8 is a timing diagram of a residual side band (VSB) synchronization signal;

9 is a structural diagram of a GA VSB data frame applied to a fast channel equalizer;

10 is a block diagram of a high speed channel equalizer according to the present invention;

11 is a detailed configuration of the tap delay unit of FIG.

12 is a detailed block diagram of the filter unit of FIG. 10;

FIG. 13 is a detailed configuration diagram of a reference signal generator of FIG. 10; FIG.

14 is a detailed configuration diagram of the tap coefficient update unit of FIG. 10;

Fig. 15 is a block diagram showing a 256-tap cascaded high-speed channel equalizer according to the present invention.

<Description of the code | symbol about the principal part of drawing>

110: tap delay unit 120: filter unit

130: multiplexer 140: tap coefficient update unit

160: reference signal generator 170: controller

200 to 500: first to fourth high speed channel equalizers

Hereinafter, with reference to the accompanying drawings, the configuration, operation and operation effects for an embodiment of the present invention "cascade type high-speed channel equalizer" according to the above technical concept as follows.

<Example>

First, the configuration of an embodiment of a 256-tap cascaded high-speed channel equalizer implemented by connecting a high-speed channel equalizer in units of 64 taps according to the present invention is filtered by a predetermined number of tap units for symbols transmitted from a transmitting side. A first high speed channel equalizer 500 for performing a channel equalization operation at high speed by adding the filtered signal and the feedback filtering signal to cancel the channel distortion characteristic; It is connected in series with the first high speed channel equalizer 500, receives a reference signal of the first high speed channel equalizer 500, which is a transmission symbol expected value at the receiving side, and is generated by previously transmitted symbols. A second high speed channel equalizer 200 which performs filtering at a high speed by the number of taps set to remove the interference between symbols; Symbols previously transmitted by being connected in series with the second fast channel equalizer 200, receiving a reference signal of the first fast channel equalizer 500 through the second fast channel equalizer 200. A third fast channel equalizer (300) for filtering to remove interference between symbols generated by the second filter and adding the filtered signal and the signal filtered by the second fast channel equalizer (200); It is connected in series with the third high-speed channel equalizer 300, receives the reference signal of the first high-speed channel equalizer 500 through the third high-speed channel equalizer 300 to filter, and the filtered And a fourth high speed channel equalizer 400 which adds a signal and a filtering signal transmitted from the third high speed channel equalizer 300 and feeds it back to the first high speed channel equalizer 500.

The first to fourth fast channel equalizers 500 to 400 may include a control unit for controlling the operation of the entire channel equalization; A tap delay unit for selectively receiving a reference signal generated by a symbol from a transmitting side or a previous channel equalization output signal and delaying by a predetermined number of taps to output the reference signal; A reference signal generator for generating a reference signal according to the time point at which the tap position data is output, and comparing the reference signal with the equalizer output signal to generate an error signal; A multiplexer for selectively multiplexing the error signal generated by the reference signal generator and the error signal generated by the error generation algorithm under the control of the controller; A tap coefficient updating unit updating the tap coefficient output from the tap delay unit according to the error signal output from the multiplexer; And a filter unit for filtering output data of the tap delay unit according to the tap coefficient of the tap coefficient update unit.

In addition, the tap delay unit is provided by a plurality of delay units (111-1) to (111-68) and a delay unit (111-1) to (111-68) which delay and output the input data. Multiple multiplexers (112-1)-(112-17) for multiplexing the input data delayed and output sequentially into four units and specific delay data on the input side are added directly to the filter unit, A multiplexer 113 outputs a reference tap signal by multiplexing input data output from four specific delayers selecting a direct path between the filter units.

The reference signal generator may include a reference signal generator 161 for generating a predetermined signal as a reference signal during transmission and reception during channel equalization in a training mode, and output from the filter unit during channel equalization in a blind mode. A slicer 162 for slicing a signal and outputting a transmission expected value as a reference signal, and a multiplexer for multiplexing the signals output from the reference signal generator 161 and the slicer 162 according to a determination signal of a training mode and a blind mode. 163 and an error signal generator 165 for generating an error signal by comparing the signal output from the filter unit with the signal output from the multiplexer 163.

The tap coefficient updating unit may include a plurality of multipliers (141-1) to (141-16) multiplying a plurality of data output from the tap delay unit and an error signal output from the multiplexing unit, and the plurality of A plurality of delayers (142-1)-(142-) which correspond one-to-one with the multipliers 141-1 to 141-16 to delay the data output from the multiplier according to the internal operation clock fs4. 16)) and one-to-one correspondence with the plurality of retarders 142-1 to 142-16 to move the output signal of each retarder according to the offset rate adjustment signal of the channel distortion characteristic ( a plurality of shifters (143-1) to (143-16) and one to one shifter corresponding to the shifters (143-1) to (143-16), respectively, to move in each shifter. A plurality of adders (144-1) to (144-16) for adding the received signal to the coefficients of the previous symbol, and one to one correspondence with the respective adders (144-1) to (144-16). Output from the adder Four units of delays 145-1, 145-16, 146-1, 146-16, which delay the signal sequentially through four delays according to the internal operation clock fs4. , (147-1)-(147-16), (148-1)-(148-16), and one-to-one correspondence with the four units of the delay unit to set the data through the four units of the delay unit to the set size. It consists of a number of limiting / rounding parts (149-1)-(149-16).

The filter unit may further include a plurality of multipliers 121-1-that multiply the coefficients updated by the tap coefficient updater and the data multiplexed and output by the multiplexers 112-1 to 112-16 in the tap delay unit. 121-16 and a plurality of delayers 122-1 through 122-16 for delaying data through the multipliers 121-1 through 121-16 according to an internal operation clock fs4. And a carry save ether 123 for adding a plurality of data through each of the delayers 122-1 to 122-16, and a previous cumulative value for adding data through the carry save ether 123. A register 124-3 for delaying the data through the first adder 124-2 and the first adder 124-2 according to an internal operation clock fs4 four times the symbol clock fs; The second adder 125-1 and the second adder 125-1, which add the data through the register 124-3 and the signal of the reference tap output from the multiplexer 113 in the tap delay unit, are added. Data and A third adder 125-4 which adds a skew input signal to output a cascade output signal, and delays a signal output from the third adder 125-4 according to a symbol clock fs to output a channel equalization signal. Consisting of a register 126.

Referring to the operation of the cascaded high-speed channel equalizer according to the present invention configured as described above are as follows.

First, the channel equalization operation is started and the input error signal of the tap coefficient update unit is set to 0 for a certain period so that coefficient update is not allowed.

Thereafter, when a data frame is input to the tap delay unit 510 in the first fast channel equalizer 500, the plurality of delay units 111-1 to 111-68 in the tap delay unit 510 are sequentially passed. Is delayed. The first multiplexer 112-1 then multiplexes the symbols through the first four delayers 112-1 through 112-4, and the second through seventeenth multiplexers 112-2 through 112-. 17 also operates in the same manner as the first multiplexer 112-1. Thus, the first through sixteenth multiplexers 112-1 and 112-16 provide the multiplexed output signal to the filter unit 520, and at the same time, the second through seventeenth multiplexers 112-2- 112-17 provides the multiplexed signal to the tap coefficient update unit 540.

Accordingly, the filter unit 520 filters the symbols output from the tap delay unit 510 using the tap coefficients of the tap coefficient update unit 540. That is, the sixteen multipliers 121-1 to 121-16 in the filter unit 520 multiply the symbols output delayed by the tap delay unit 510 and the tap coefficients output from the tap coefficient update unit 540. The sixteen delayers 122-1 to 122-16 store the values output from the multipliers 121-1 and 121-16 according to the internal operation clock fs4.

The carry save ether 123 then adds the data through the 16 delays 122-1 through 122-16, and the multiplexer 124-4 adds the previous data output from the delay 124-3. Multiplex the data according to the control signal. The first adder 124-2 adds data output from the carry save 123 and data output from the multiplexer 124-4. Here, the control clock uses an internal arithmetic clock fs4 that is four times the symbol clock fs, and the control signal also shares the same arithmetic device by repeating four modes. In other words, the 64 tap signals are calculated by dividing by 16 taps and summed. If the new tap signals are added when the added values are accumulated, the reset function is performed by adding zeros rather than adding the previous accumulated values.

On the other hand, the multiplexer 113 in the tap delay unit 510 outputs a signal of the reference tap when a reference tap to directly receive data transmitted from the transmitting side is selected. Then, the second adder 125-1 in the filter unit 520 adds the signal of the reference tap and the output signal of the first adder 124-2 to obtain the channel equalization output signal of 64 taps, and the third adder ( 125-4) adds the output signal of the second adder 125-1 and the cascade input signal to output a cascade output signal. Accordingly, the register 126 delays the output signal of the third adder 125-4 according to the symbol clock fs to generate a 64 tap channel equalization output signal.

Herein, while the field synchronization signal is received during the data frame, the controller controls the channel equalization operation to be performed in the training mode. Therefore, the data transmitted from the transmitting side can accurately predict the data transmitted from the transmitting side through the field synchronizing signal composed of the signals promised in advance between the transmitting and receiving sides, so that the reference signal generator 161 in the reference signal generator 560 refers to the transmission value. Output as a signal. This reference signal is generated during the reception of the front 700 symbol of the field sync signal. In addition, the error signal generator 165 outputs a difference signal between the reference signal and the channel equalization signal output from the filter unit 520 as an error signal.

At the same time, the tap coefficient updater 540 is generated by the symbols multiplexed by the second to seventeenth multiplexers 112-2-112-17 and the reference signal generator 560 in the tap delay unit 510. The tap coefficient is updated to cancel the channel distortion characteristic by receiving the received error signal.

Meanwhile, the generated reference signal sequentially passes through the tap delay units 210 to 410 in the second to fourth fast channel equalizers 200 to 400, so that interference between symbols generated by previously transmitted symbols is reduced. It is used to remove the part that occurs.

That is, the tap delay unit 210 in the second high speed channel equalizer 200 receives the reference signal output from the first high speed channel equalizer 500, and thus taps the first high speed channel equalizer 500. Operation is performed in the same manner as that of the delay unit 510. Then, the filter unit 220 in the second high-speed channel equalizer 200 uses the tap coefficients of the tap coefficient update unit 240 with respect to the reference signal output by being delayed by the tap delay unit 210. The cascade output signal cascade_out is generated by filtering in the same manner as the operation method of the filter unit 220 in the fast channel equalizer 500. The tap coefficient updater 240 updates the tap coefficients with a reference signal of the first fast channel equalizer 500 output from the tap delay unit 210 and an error signal output from the first fast channel equalizer 500. do.

Then, the third high speed channel equalizer 300 receives the cascade output signal output from the second high speed channel equalizer 200 as the cascade input signal cascade_in and simultaneously taps the delay in the second high speed channel equalizer 200. The reference signal output from the unit 210 is input, and the reference signal is filtered to output a cascade output signal cascade_out.

In addition, the fourth fast channel equalizer 400 also receives the reference signal output from the third fast channel equalizer 300 and the cascade output signal cascade_out, and filters the reference signal to filter the first fast channel equalizer. Pass in 500. Herein, the tap coefficient update unit 340 and 440 in the third and fourth fast channel equalizers 300 and 400 may also operate the tap coefficient update unit 240 in the second fast channel equalizer 200 described above. The tap coefficient is updated in the same manner as the method.

Thus, the first high speed channel equalizer 500 generates the final channel equalization output signal by adding the signals filtered by the second to fourth high speed channel equalizers 200 to 400. As such, the first fast channel equalizer 500 updates the tap coefficients every symbol clock to filter the received symbols, and the second to fourth fast channel equalizers 200 to 400 update the tap coefficients every symbol clock. The channel equalization operation is performed so as to cancel the channel distortion characteristic by filtering the reference signals generated by the high speed channel equalizer in the previous stage.

In this manner, if a data symbol is received after the field synchronization signal of 828 symbols is received in the data frame, the controller controls the channel equalization operation to be performed in a blind mode. At this time, the coefficient update is suppressed up to 256 symbols of the next segment. In addition, when switching from the blind mode to the training mode, the coefficient update during the reception of a certain symbol is suppressed.

When 256 symbols of data are received after switching to the blind mode, the first to fourth fast channel equalizers 500 to 400 update the tap coefficients and perform channel equalization on the received data symbols so that the channel distortion characteristics are canceled. Will be performed. Of the reference signal generators in each of the high-speed channel equalizers 500-400, only the first high-speed channel equalizer 500 slices the channel equalization output signal to generate a transmission expected value as a reference signal, and the channel equalization output signal and the reference signal. Generates a difference signal as an error signal. Then, the channel equalization operation is performed in the same manner as the channel equalization operation in the aforementioned training mode.

In this way, the channel equalization operation is performed while automatically switching between the training mode and the blind mode, thereby quickly adapting to the changed channel to restore accurate transmission data.

Fast channel adaptation can be achieved by updating all tap coefficients within one symbol clock.

In addition, the cascaded high-speed channel equalizer according to the present invention is capable of channel adaptation to all 8VSB, 16VSB, and ZCom filter pass-through modes.

In addition, by connecting the high speed channel equalizer in units of 64 taps in series, a high speed channel equalizer having an arbitrary number of taps can be realized, and the high speed channel equalizer in units of 64 taps can be implemented using only the forward channel equalizer according to a symbol input to the tap delay unit. In addition, the forward channel equalizer and the backward channel equalizer may be implemented in series.

Internally, pipelining is used to delay the output and the clock corresponding to the internal arithmetic clock (fs4), four times the symbol clock (fs), is used repeatedly for the parallel architecture. Reduced in size.

As described above, the present invention " cascaded fast channel equalizer " is particularly effective by implementing a fast channel equalizer of any number of taps by connecting a high speed channel equalizer in units of a certain number of taps in series.

In addition, by updating all the tap coefficients within one symbol clock, it is possible to achieve fast channel adaptation.

Claims (5)

In a high speed channel equalizer for restoring transmission data by canceling channel distortion characteristics in a high speed digital communication system, A controller 170 for controlling a fast channel equalization operation; A tap delay unit (110) having a predetermined number of taps to perform a fast channel equalization operation in units of set taps, and receiving and outputting a symbol for performing the fast channel equalization operation by a set number of taps; A reference signal generator 160 generating a new reference signal according to the control of the controller 170 and comparing the reference signal with the channel equalization output signal to generate an error signal according to the timing at which the tap position data is output; ; A multiplexer 130 for selectively multiplexing the error signal generated by the reference signal generator 160 and the error signal generated by the error generation algorithm under the control of the controller 170; A tap coefficient update unit 140 for selectively receiving a signal delayed by the tap delay unit 110 and updating the received tap coefficient according to an error signal output from the multiplexer 130; The signal delayed by the tap delay unit 110 is selectively input, and the received data is filtered according to the tap coefficient of the tap coefficient updater 140, and the channel equalization output signal and the filtering data by other input symbols are filtered. Cascade type high-speed channel equalizer, characterized in that consisting of a filter unit 120 for generating a final equalized output signal of the desired number of taps by adding a. The method of claim 1, If the data inputted to the tap delay unit 110 is data transmitted from the transmitting side, a forward channel equalization operation is performed. If the data inputted to the tap delay unit 110 is an expected transmission value of the receiving side, a backward channel equalization operation is performed. Cascade type high-speed channel equalizer, characterized in that to perform. The method of claim 1, wherein the tap coefficient update unit 140, The tap coefficient is updated by multiplying a plurality of data output from the tap delay unit 110 and an error signal output from the multiplexer 130, and providing the updated tap coefficient to the filter unit 120. Cascade high-speed channel equalizer. The method of claim 1, wherein the filter unit 120, A plurality of multipliers 121-1 to 121-16 multiplying the data transmitted from the tap delay unit 110 with the tap coefficients of the tap coefficient updater 140, and the multipliers 121-1. A plurality of delayers 122-1 to 122-16 for delaying data through -121-16 according to an internal operation clock fs4 four times the symbol clock fs; The control signal (ctrl) controls the carry save 123 for adding a plurality of data through the (122-1)-(122-16) and the set value for the accumulated value and the reset function through the register 124-3. A multiplexer 124-4 for multiplexing according to the &lt; RTI ID = 0.0 &gt;), a first adder 124-2 &lt; / RTI &gt; A register 124-3 for delaying the data through the one adder 124-2 according to the internal operation force fs4, the data through the register 124-3 and the multiplexer in the tap delay unit 110; Output from (113) A second adder 125-1 that adds the signal of the quasi-tap and outputs a channel equalization output signal of the set number of taps as a result, and channel equalization by input data different from the signal through the second adder 125-1. A third adder 125-4 which adds a cascade input signal as an output signal and outputs the result as a cascade output signal, and delays the signal output from the third adder 125-4 according to a symbol clock fs. And a register 126 for outputting the channel equalization signal. In a high speed channel equalizer for restoring transmission data by canceling channel distortion characteristics in a high speed digital communication system, A first high speed channel equalizer 500 for performing a channel equalization operation by filtering the received symbols in a predetermined number of tap units and adding the filtered signal and the feedback filtering signal to cancel the channel distortion characteristic; ; It is connected in series with the first high speed channel equalizer 500, and receives a reference signal of the first high speed channel equalizer 500, and is set to remove interference between symbols generated by previously transmitted symbols. A second high speed channel equalizer 200 which performs filtering at a high speed by the number of taps; It is connected in series with the second high-speed channel equalizer 200, and filters the reference signal of the first high-speed channel equalizer 500 through the second high-speed channel equalizer 200, the filtered signal and the A third high speed channel equalizer 300 which adds a signal filtered by the second high speed channel equalizer 200; It is connected in series with the third high-speed channel equalizer 300, and filters the output signal of the first high-speed channel equalizer 500 through the third high-speed channel equalizer 300, and the filtered signal and A cascade type high speed channel comprising: a fourth high speed channel equalizer 400 configured to add the filtering signal transmitted from the third high speed channel equalizer 300 to the first high speed channel equalizer 500. Equalizer.

Images