KR100241770B1 - Channel equalizer in hdtv using vestigial sideband - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a high-speed channel equalization device of a residual sideband (VSB) type high definition television (HDTV) receiver. In particular, the present invention buffers an input signal according to a symbol clock (fs) and internally computes a clock corresponding to four times the symbol clock. By filtering the input signal by the coefficient update of the tap corresponding to half the number of taps when the rising edge of (fs4) occurs, and filtering the input signal by the coefficient updating of the remaining half number of taps when the falling edge of the internal arithmetic clock occurs, By reducing the number of devices that update the tap coefficient and the number of devices that are filtered by half, the overall device configuration is reduced, and by configuring adjacent cells on the data path in the same module, the system performance is reduced by reducing data transmission delay in ASIC design. A high speed channel equalizer is provided for improving.

Description

High Speed Channel Equalizer of Residual Sideband Band Type High Definition Television Receiver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed digital communication system, and more particularly, to a channel equalizer for compensating amplitude and phase distortion of a reception channel in a grand alliance (VGA) vertical sideband high definition television (HDTV) receiver.

In general, inter-symbol interference (ISI) is the biggest factor degrading system performance in high speed digital communication systems. ISI is caused by linear distortion of channels, ie multipath channels, non-ideal frequency response, group delay, and so on. An adaptive equalizer is a kind of inverse filter installed inside the receiver to remove or reduce the ISI as much as possible, thereby recovering the data sent from the transmitter without error.

In the general adaptive equalizer, the equalizer tap coefficient is adjusted to offset the distortion characteristic of the channel by receiving a predetermined training sequence between the transmitting side and the receiving side during the initial training period. While operating in the blind mode, the equalizer tap coefficient is adjusted to compensate for channel distortion by estimating the symbol sent from the transmitter using only the received signal. The training mode and the blind mode are operated alternately to estimate the channel inversely.

1 is a block diagram of a general GA type VSB high definition television receiver block.

As shown, reference numeral 2 is a tuner for tuning only a desired channel from the signal received at the antenna, and 3 is an intermediate frequency for filtering only the intermediate frequency of the channel tuned at the tuner 2 and detecting segment synchronization and field synchronization. A filter and a sync detector, and reference numeral 4 is a timing information provider for providing a timing for processing an input signal according to the sync signal detected by the intermediate frequency filter and the sync detector 3.

Reference numeral 5 denotes an NTSC interference cancellation filter for removing channel interference from the channel signal output from the intermediate frequency filter and the synchronization detector 3, and reference numeral 6 denotes a linear channel distortion of the signal output from the NTSC interference cancellation filter. A compensating equalizer, 7 is a phase tracker that estimates the phase from the output of the equalizer 6.

In addition, reference numeral 8 is a lattice decoder 8 that decodes input data by performing backtracking after receiving a certain amount of data through the phase tracker 7, and 9 denotes data output from the lattice decoder 8. A data deinterleaver for deinterleaving, 10 is a Reed Solomon decoder for decoding the data through the data deinterleaver 9, and 11 is a data derandom for de-randomizing the data through the Reed Solomon decoder 10. It is firearms.

2 shows a data frame of VSB standard by GA, one segment is composed of 832 symbols, the first four symbols of each segment are segment synchronization signals, and the 828 symbols are data. One field is composed of 312 segments of data and one segment of field synchronization signal, and one frame is composed of two fields. In addition, 4 symbols constitute 1 byte in 8VSB, and 2 symbols constitute 1 byte in 16VSB.

The GA type VSB high definition television (HDTV) receiver having such a configuration tunes a desired channel in the tuner 2, obtains the intermediate frequency of the tuned channel in the intermediate frequency filter and the synchronization detector 2, and then segments the synchronization signal and the field. The synchronization signal is detected. The timing information providing unit 4 provides timing information for processing the input data according to the segment synchronization signal and the field synchronization signal obtained above. The NTSC interference cancellation filter 5 provides the inter-channel interference of the input channel data. Will filter. In addition, the equalizer 6 compensates for channel distortion of the channel data through the NTSC interference cancellation filter 5, and the phase tracker 7 attempts phase tracking for phase error compensation and frequency error compensation. The data compensated for the phase and frequency errors are then deinterleaved by the deinterleaver 9 after being decoded by the lattice decoder 8 and dequantized by the derandom decoder 11 after being decoded by the Reed Solomon decoder 10 again. Is performed to restore the original data.

HDTV with VSB receiver having this effect provides high quality video and CD quality sound. To realize this, high compression is required and perfect recovery from signal transmission and reception is required. One of the techniques for completely recovering such transmission data is a channel equalizer, and plays a particularly important role when compensating for distortion caused by a channel during digital transmission and reception.

As is well known, the channel equalizer is a kind of inverse filter installed inside the receiver for the purpose of compensating for linear channel distortion such as tilt and ghost. Distortion may be caused by incomplete elements in the transmission channel or in the receiving end. In addition, multipath adds signals reflected from buildings, moving objects, etc. to the original signal, making the original signal unrecognizable. These distortions are caused by image distortion such as picture distortion and ghost in analog TVs we are using, but in the digital transmission system, they are completely different from image or unrecoverable due to bit detection error.

3 is a block diagram of a general channel equalizer for such a function.

As shown, the control unit 10 for controlling the mode control and the coefficient update time allowed according to the information on the input data frame, and controls the entire channel equalization operation; A reference signal generator 30 generating a reference signal according to a point of time at which data at a tap position is output under the control of the controller 10, and comparing the reference signal with an output signal to generate an error signal; A backward tap delay unit 40 delaying an output signal from the reference signal generator 30 by a set number of taps and outputting the delayed output signal; A forward tap coefficient updating unit (50) for updating both coefficients of the forward taps within one symbol clock as the error signal output from the reference signal generator (30) and the output signal of the forward tap delay unit (20); A backward tap coefficient updating unit 70 for updating both the coefficients of the backward taps within one symbol clock as the error signal output from the reference signal generator 30 and the output signal of the backward tap delay unit 40; ; A forward tap delay unit 20 for delaying and transmitting the transmission data from the transmission side by a set number of taps; The forward tap coefficient updating unit 50 and the backward tap coefficient updating unit 70 respectively output the forward tap delay unit 20 and the backward tap delay unit 40 according to the tap coefficients updated. And a filter unit 90 for filtering the output / feedback data and adding the filtered output and feedback data to generate a channel equalization output signal.

In this case, the backward tap delay unit 40 is delayed with 196 delayers 41-1 through 41-196 which delay and output the reference signals output from the reference signal generator 30, respectively. It consists of 49 multiplexers 42-1 and 42-49 which multiplex the output data.

In addition, the forward tap delay unit 20 includes 68 delayers 21-1 to 21-68 for delaying and outputting symbols from the transmitting side, and 17 multiplexes for multiplexing the input symbols outputted with delay. And a multiplexer 23 for receiving the symbols from the transmitting side.

As illustrated in FIG. 7, the forward tap coefficient updater 50 multiplies a plurality of received symbols output from the forward tap delay unit 20 and error signals output from the reference signal generator 30. 16 multipliers (51-1)-(51-16), a plurality of delayers (52-1)-(52-16), 16 shifters (53-1)-(53-16), Retarders (55-1)-(55-16), (56-1)-(56-16), (57-1)-(57-16), (58-1)-(58-16) and Adder 54-1-54-16, and 16 rounding / limiting parts 60-1, 60-16.

In addition, the backward tap coefficient updater 70 multiplies the plurality of reference signals output from the backward tap delay unit 40 and the error signals output from the reference signal generator 200, respectively. -1)-(71-48), multiple delayers 72-1) -72-48, 16 shifters 73-1-73-48, and four units of delay Groups 75-1)-(75-48), (76-1)-(76-48), (77-1)-(77-48), (78-1)-(78-48), 16 adders 74-1-74-48 and 16 rounding / limiting parts 79-1-79-48.

The filter unit 90 includes a forward filter 93 for filtering an input symbol multiplexed by the forward tap delay unit 20 according to the coefficient updated by the forward tap coefficient updater 50, and the bag. A backward filter 97 for filtering the reference signal multiplexed by the backward tap delay unit 40 according to the coefficient updated by the word tap coefficient updating unit 70, the forward filter 93, and the backward word; And a summator 98 for generating a channel equalization output signal by adding the signal filtered by the filter unit 97 and the signal of the reference tap output from the multiplexer 23 of the forward tap delay unit 20. .

Table 1 below shows the input and output signals of each pin of the general high speed channel equalizer shown in FIG.

NAME (pin count) TYPE FUNCTION fs input Symbol Clock (10.762 MHz) fs4 input Symbol clock (4 * fs) vin (8) input 8-bit input signal field_lock input Field sync lock control signal field_sync input Field sync flag (1 during 828 symbols) seg_sync input Segment Sync Flag (1 for 4 symbols) comb input Select comb filter mode (1 when passing comb filter) vsbmode input VSB mode selection signal (8VSB 0, 16VSB 1) even_odd input Data field mode selection (even field 0, odd field 1) / cs input Equalizer Chip Selection (Micom's Equalizer Chip Assignment Signal) / wr input Write strobe (Miccom's data write strobe) / rd input Read Strobe (Miccom's Data Read Strobe) addr (3) input Microcomputer address bus data (8) input Microcomputer data bus other_err (6) input Error calculated by algorithm different from inside chip bypass input Input pass strobe (1 on pass) freeze input Coefficient Fixed Strobe (1 at Coefficient Fixed) updaterr_sel input Count update error selection (internal error 0, external error 1) only_trainm_mode input Operation mode selection (1 when operating in train mode only) errout_mode_sel input Output error selection (1 when outputting only train errors) overlap input Select tab overlap (1 if overlap is allowed) tap_position (2) input Insert tap position (00:15 ^th tap, 01: 31 ^st tap, 10: 47 ^th tap, 11:62 ^nd tap step_train (2) input Train Mode Staff step_blind (2) input Blind Mode Staff update_start (2) input Coefficient update start position (00:45 symbol, 01:90 symbol, 10: 135 symbol, 11: 180 symbol) control_sel input Chip control selection (0 for pin control, 1 for microcomputer control) fsync_to_ptl output Field_synchronous output delayed by PTL block ssync_to_ptl output Segment_synchronous output delayed by PTL block out_error (6) output Error output vout (10) output Data output in PTL block

The operation of the channel equalizer of the general high definition television system configured as described above is as follows.

First, when the VSB receiver receives a symbol from the transmitting side, the control unit 10 in the fast channel equalization system obtains information on a data frame from a corresponding signal (field_lock, field_sync, segment_sync, even_odd, vsb_mode, comb). Control channel equalization.

That is, as shown in FIG. 9, the controller 10 controls the channel equalization operation in the training mode while the data frame receiving signal B is activated and the front end 700 symbols of the field sync signal of 828 symbols are received. In addition, the channel equalization operation is performed in a blind mode while a data symbol formatted after the field sync signal of the data frame is received. When switching from the training mode to the blind mode, the coefficient update is suppressed up to 256 symbols of the next segment, and even when switching from the blind mode to the training mode, the coefficient update resumes after a certain symbol has passed.

That is, the reference signal generator 30 generates a predetermined training sequence between the transmission and reception while transmitting and receiving the 700 symbol of the front end portion of the field synchronization signal, and outputs the training sequence to the backward tap delay unit 40. The error between the training sequence and the received symbol is output. The calculation is output to the backward tap coefficient updating unit 70 and the forward tap coefficient updating unit 50. The forward tap coefficient updater 50 then updates all tap coefficients per symbol rate to minimize the mean squared error with the error signal, and at the same time, the backward tap coefficient updater 70 also uses the error signal. All tap coefficients will be updated.

Thus, the forward filter 93 filters the input symbols delayed by the forward tap delay unit 20 by the tap coefficients output from the forward tap coefficient updater 50, and the backward filter 97 The training sequence, that is, the reference signal, through the backward tap delay delay unit 40 is filtered by the tap coefficient output from the backward tap coefficient updater 70. The summer 98 generates a channel equalization output signal by summing the signals through the forward filter 93 and the backward filter 97 and the signals of the reference taps, respectively.

When all of the 256 tap coefficients are simultaneously updated within one symbol clock by the forward tap coefficient updating unit 410 and the backward tap coefficient updating unit 430, the filter unit 600 updates the tap coefficients updated by the coefficient updating unit 400. Filtering is performed on each filter input signal to generate a channel equalization output signal from which channel distortion characteristics are canceled.

Then, when the field synchronization signal is received and data from the transmitting side is transmitted, the control unit 10 estimates a symbol to be transmitted from the transmitting side and controls the symbol prediction value to be generated as a reference signal, so that the reference signal generating unit 30 A symbol prediction value is generated and transmitted to the backward tap delay unit 40.

Thus, the symbol equalization value generated by predicting the symbol to be transmitted by the transmitting side is used as the reference signal instead of using the symbol previously promised between the transmission and reception as the reference signal. It works in a way.

Thus, a general high speed channel equalization system is operated to cancel channel distortion characteristics by automatically performing channel equalization operations in training mode and blind mode according to a control unit for controlling the entire channel equalization operation with information obtained by the received data frame. Will be.

In addition, a typical high-speed channel equalization system uses an internal computation clock (fs4), which is four times the symbol clock, to reduce the chip size by repeatedly using the same computational device for parallel architectures, and within one symbol clock (fs). All tap coefficients will be updated.

This general high-speed channel equalization system has a disadvantage in that the system configuration is complicated because adjacent blocks on the data path cannot be designed as an ASIC.

In addition, since adjacent blocks on the data path cannot be designed as a single block, a line delay occurs on a path through which data is transmitted, thereby degrading system performance.

An object of the present invention is to solve the above-described problems, and in particular, by changing the structure of the forward tap coefficient updating unit, the backward tap coefficient updating unit, and the filter unit which occupy most of the area of the channel equalizer, Of VBB high-definition television (HDTV) receivers, which improve the system performance by reducing the transmission rate and reducing the line propagation delay by modularizing adjacent blocks on the data path into one block. It is to provide a high speed channel equalizer.

The present invention to achieve the above object,

A control unit for controlling the mode control and the coefficient update allowing time according to the information on the input data frame, and controlling the channel equalization operation by driving the system to the rising edge and the falling edge of the internal operation clock; It is an error signal outputted from the reference signal generator that generates the error signal and the reference signal for canceling the channel distortion, and when the rising edge of the internal operation clock is generated, the input signal is filtered by updating the coefficient of the corresponding tap, and the falling edge of the internal operation clock. The technical feature of the present invention is that the channel equalizer is configured to filter the input signal by updating the coefficient of the corresponding tap when it occurs.

1 is a block diagram of a typical GA VSB HDTV receiver;

2 is a structural diagram of a data frame of a residual sideband method according to the GA standard;

3 is a block diagram of a general channel equalizer applied to FIG. 1;

4 is a detailed configuration diagram of a forward tap delay unit of FIG. 3;

5 is a detailed configuration diagram of a backward tap delay unit of FIG. 3;

6 is a detailed block diagram of the filter unit of FIG. 3;

7 is a detailed configuration diagram of the forward tap coefficient updating unit of FIG. 3;

8 is a detailed configuration diagram of the backward tap coefficient updating unit of FIG. 3;

9 is a timing diagram of a residual sideband synchronization signal applied to a general channel equalizer;

10 is a block diagram of a fast channel equalizer of a residual side band band (VSB) type high definition television (HDTV) receiver according to the present invention;

11 is a detailed block diagram of the channel equalizer of FIG. 10;

12 is a detailed block diagram of the filter cell of FIG.

13 is a detailed configuration diagram of the cumulative adder of FIG.

14 is a detailed configuration of the tap cell of FIG.

15 is a detailed configuration of the tap delay cell of FIG.

16 is a detailed configuration diagram of a delay cell of FIG. 11;

17 is a timing diagram showing an operation flow of a filter cell and a cumulative adder.

* Explanation of symbols for main parts of the drawings

100: controller 200: channel equalizer

300: reference signal generator 210: forward filtering unit

220: backward filtering unit 250: cumulative adder

211,213,215,217: Filter cell 212,214,216: Tap cell

218: tap delay cell 221-243: filter cell

244: Delay cell

Hereinafter, the configuration and operation of an embodiment according to the technical concept of the present invention ″ a high-speed channel equalization apparatus of a residual side wave band (VSB) high definition television (HDTV) receiver 'will be described in detail with reference to the accompanying drawings. .

<Example>

First, the configuration of an embodiment of the high-speed channel equalization apparatus of a residual sideband (VSB) type high definition television (HDTV) receiver is timed to allow mode control and coefficient update according to information on an input data frame, as shown in FIG. A control unit 100 for controlling the channel equalization operation by driving the system to the rising edge and the falling edge of the internal operation clock; A reference signal generator 300 generating a reference signal according to a point of time at which data at a tap position is output under the control of the controller 100, and comparing the reference signal with an equalization output signal to generate an error signal; An error signal output from the reference signal generator 300 includes a channel equalizer 200 for filtering an input signal by updating a coefficient of a tap each time a rising edge or a falling edge of an internal operation clock is generated.

In this case, the channel equalizer 200 updates the coefficients of the corresponding taps when the rising edge and the falling edge of the internal operation clock fs4 are generated, and filters the symbols from the transmitter. (210), and the backward filtering unit 220 for filtering the reference signal of the rotor from the reference signal generator 300 by updating the coefficient of the tap when the rising edge and the falling edge of the internal operation clock (fs4) occurs; When the rising edge and the falling edge of the internal operation clock fs4 are generated, the filtered values output from the forward filtering unit 210 and the backward filtering unit 220 are added, respectively, and the reference tap is added to the added value. And a cumulative adder 250 for generating a channel equalization output signal by adding a signal of.

The forward filtering unit 210 buffers and delays the symbols from the transmission side during the eight symbol clocks fs and uses an internal operation clock fs4 as an error signal output from the reference signal generator 300. Filter cell 211 for filtering the buffered symbol by updating the coefficient of the tap each time the rising edge and the falling edge of the) and the received symbol from the filter cell 211 buffered for eight symbol clocks and delayed, When the rising edge and the falling edge of the internal operation clock fs4 are updated with the error signal output from the reference signal generator 300, the tap coefficients are updated to filter the buffered symbols, and the symbol at the preset reference tap position is output. A filter cell 213 that accepts and buffers a tap cell 212 and a symbol transmitted with a delay from the tap cell 212, and operates in the same manner as the filter cell 211 to filter a symbol; 213 receives and buffers the symbol, operates in the same manner as the tap cell 212, filters the symbol, and outputs the signal of the set reference tap, and the tap cell 214 is transmitted from the tap cell 214. The filter cell 215 for buffering and delaying the symbol to be processed, and the filter cell 215 for filtering the symbol by operating in the same manner as the pulver cell 211, and the delayed symbol transmitted from the pulver cell 215 and the tap cell 212. A filter cell for filtering by operating in the same manner, and for filtering the tab cell 216 for outputting a symbol in the corresponding reference tab and a symbol transmitted from the tap cell 216 in the same manner as the filter cell 211 ( 217 and the symbol transmitted from the filter cell 217 in the same operation as the filter cell 211, outputs the symbol in the set reference tab, and generates the error signal in the reference signal generator 300 to do Delaying symbols by John time consists of a tapped delay cell 218.

The filter cell may include a tap delay unit 400 for buffering and delaying an input symbol according to a symbol clock fs and a symbol delayed and output from the tap delay unit 400 according to a control signal ctrl. A rising edge of the internal arithmetic clock fs4 using the multiplexers 411 and 412 to sequentially multiplex the symbols output from the multiplexer 411 and the error signals output from the reference signal generator 300. And a multiplexer 412 for multiplexing the symbols of the second half of the tap delay unit 400 and a first half symbol of the tap delay unit of the tap delay connected to the rear end of the filter cell. The coefficient output / filter unit 420 filters the symbols output from the multiplexer with updated coefficients every time the rising edge and the falling edge of the internal operation clock fs4 are generated.

The tap delay unit 400 is composed of eight delayers 401-408 that buffer and delay input symbols during one symbol clock (fs) period.

The coefficient update / filter unit 420 is multiplexed according to a control signal (ctrl) in the multiplexer 412 which multiplexes the output signals of the four delay units 405-408 in the latter half of the tap delay unit 400. Multiplexes the output signal according to the control signal ctrl in a multiplexer for multiplexing the output signal and the output signal of each of the first four delayers of the tap cell connected to the rear end of the filter cell according to the internal operation clock fs4. A multiplexer 421, a multiplier 422 multiplying the signal output from the multiplexer 421 and an error signal output from the reference signal generator 300, and a signal through the multiplier 422. A negative deflip-flop 423 buffering and outputting the falling edge of the operation clock fs4, and a positive deflip-flop 424 buffering and outputting the signal through the multiplier 422 when the rising edge of the internal operation clock is generated. Positive deflector A multiplexer 425 for multiplexing the signals output from the 424 and the negative flip-flop 423 according to an internal operation clock, and a signal through the multiplexer 425 to a channel distortion detail rate signal (step). A shifter 426 for right shifting according to the set bit, an adder 427 for adding a previous symbol that is buffered and delayed according to a signal through the shifter 426 and an internal operation clock, and the adder Four positive flip-flops (428-431) for sequentially buffering the signal through the (427) whenever the rising edge of the internal arithmetic clock occurs, and the signal through the adder (427) when the falling edge of the internal arithmetic clock occurs. Four negative deflip-flops 432-435 for buffering and sequentially delaying each signal, and a first rounding / limiting part for making the signal output from the positive deflip-flop 430 into a set symbol bit ( 437), a second rounding / limiting unit 439 and the first rounding / limiting unit 437 and the second rounding / limiting unit which make the signal output from the negative deflip-flop 434 into a set symbol bit. The multiplexer 441 for multiplexing the signals output from the 439 according to the internal arithmetic clock and outputting them as tap coefficient signals, and the filter cell input signals respectively output from the multiplexers 411 and 412 are internal arithmetic clocks. A multiplexer 442 multiplexed according to the multiplexer, a multiplier 443 multiplying a signal output from the multiplexer 442 and a tap coefficient output from the multiplexer 441, and a signal through the multiplier 443. The negative deflip-flop 444 outputs when the falling edge of the internal arithmetic clock is generated, and the positive deflip-flop 445 outputs the signal through the multiplier 443 when the rising edge of the internal arithmetic clock is generated.

The tap cell is configured in the same manner as the configuration of the filter cell, and outputs the corresponding reference tap signal at the position of the set reference tap.

The tap delay cell 218 is configured in the same manner as the configuration of the filter cell, and outputs the corresponding reference tap signal from the set reference tap, and as much as the error signal generation time of the reference signal generator 300. The apparatus further includes a set number of delayers 509-512 for buffering and delaying input symbols and a multiplexer 517 for multiplexing output signals of the delayers 509-512 according to a multiplexing control signal ctrl. do.

The backward filtering unit 220 buffers and delays the reference signal generated by the reference signal generator 300 according to a symbol clock fs, and outputs the error signal output from the reference signal generator 300. The filter cell 221 for filtering the buffered reference signal by updating the coefficient of the tap each time the rising edge and the falling edge of the internal operation clock fs4 is generated, and buffering the signal transmitted from the filter cell in front of the filter cell ( In the same manner as in 221, the plurality of filter cells 222-243 for transmitting the buffered and delayed reference signal to the filter cell at the next stage and the filter cells 222-243 are sequentially passed according to the symbol clock. And a delay cell 244 for buffering and filtering the reference signal and delaying the reference signal by the time required to generate the error signal in the reference signal generator 300.

The filter cells 221-243 are configured in the same manner as the filter cells 211 in the forward filtering unit 210.

The delay cell 244 is configured in the same manner as the filter cells 221-243, and the filter cell connected to the front end of the delay cell 244 by the error signal generation time of the reference signal generator 300. Four delayers 559-562 for delaying the buffering signal of 243 and a multiplexer for multiplexing the signals output from the delayers 559-562 according to the multiplexing control signal ctrl ( 567).

The cumulative adder 250 includes a first carry save ether 600 which adds all the signals output each time the falling edge of the internal operation clock fs4 is generated by the forward filtering unit 210, and the forward filtering unit 210. ), The second carry save ether 601 which adds all the signals output each time the rising edge of the internal arithmetic clock is generated, and the signal output each time the falling edge of the internal arithmetic clock is generated by the backward filtering unit 220 A third carry save adder 602 to be added, a fourth carry save adder 603 which adds all the signals output each time the rising edge of the internal operation clock is generated by the backward filtering unit 220, and the four carry adders. Equalization that adds all the signals output from the save ethers 600 to 603 and adds the reference tap signal output from the forward filtering unit 210 to the addition result to generate a channel equalization output signal. The signal generator 610 is configured.

In the above, the equalization signal generator 610 may include a negative deflip-flop 611 and a adder 612 that buffer the signal output from the first carry save ether 600 when a falling edge of the internal operation clock fs4 is generated. A multiplexer 614 for storing the added value to accumulate for one symbol clock fs, and an adder 612 for adding a signal output from the deflip-flop 611 and a signal output from the multiplexer 614. ), A positive deflip-flop 615 for buffering the signal output from the second carry save 601 when the rising edge of the internal operation clock is generated, and a value added by the adder 616 is one symbol clock fs. An output from the multiplexer 618 for storing the data during the accumulation, an adder 616 for adding signals through the positive deflip-flop 615 and the multiplexer 618, and the third carry save ether 602. Signal is generated when the falling edge of the internal A buffered negative flip-flop 621, a multiplexer 624 for storing the signal through the adder 622 so that it accumulates during one symbol clock fs, the negative flip-flop 621 and the multiplexer ( An adder 622 for adding a signal through 624, a positive deflip-flop 625 for buffering a signal output from the fourth carry save 603 when a rising edge of an internal operation clock is generated, and an adder 626 A multiplexer 628 for storing the signal through the accumulator for one symbol clock, an adder 626 for adding the output signal of the positive deflip-flop 625 and the output signal of the multiplexer 628, and An adder 631 for adding signals output from the four adders 612, 616, 622, and 626, the value added by the adder 631, and the set taps of the forward filtering unit 210. The channel equalization output signal is added by adding the output reference tap signal. It consists of an adder 632 that occur.

The operation of the high-speed channel equalizer of the residual sideband band (VSB) type high definition television (HDTV) receiver according to the present invention configured as described above is as follows.

When receiving a symbol from a transmitting side in a residual sideband (VSB) receiver, the control unit 100 in the fast channel equalization system obtains information about a data frame from a corresponding signal (field_lock, field_sync, segment_sync, even_odd, vsb_mode, comb). In this way, the channel equalization operation is controlled (where each input / output signal of FIG. 10 is as shown in Table 1 above).

That is, as shown in FIG. 9, the controller 100 controls the channel equalization operation in the training mode while the data frame reception signal B is activated and the front end 700 symbols of the field synchronization signals of 828 symbols are received. In addition, the channel equalization operation is performed in a blind mode while a data symbol formatted after the field sync signal of the data frame is received. When switching from the training mode to the blind mode, the coefficient update is suppressed up to 256 symbols of the next segment, and even when switching from the blind mode to the training mode, the coefficient update is resumed after a certain symbol has passed to cancel the channel equalization distortion. The best channel will be tracked.

First, the case of operating in the training mode, the forward filtering unit 210 in the channel equalizer 200 buffers the symbols from the transmitting side in accordance with the symbol clock (fs), the internal corresponding to four times the symbol clock The buffered input symbol is filtered by updating the coefficient of the corresponding tap according to the operation clock fs4. In addition, the backward filtering unit 220 in the channel equalizer 200 receives the training sequence generated by the reference signal generator 300, that is, the reference signal, and buffers the received training signal according to the symbol clock fs. Filter the buffered reference signal by updating the coefficients of the corresponding tap. The cumulative adder 250 adds the filtered signals output from the forward filtering unit 210 and the backward filtering unit 220 each time the rising edge and the falling edge of the internal operation clock fs4 are generated. The final channel equalization output signal is output by adding the reference tap signal output from the set reference tap of the forward filtering unit 210 to the set value.

Referring to the operation of each block of the channel equalizer 200 in detail, in the high-definition television system of the Grand Alliance (GA) VSB (Vestigial SideBand) method, the channel distortion is canceled using the current 256 taps. ) 64 and 192 taps in the backward filtering unit 220.

Eight delays 401-408 in the first filter cell 211 of the forward filtering unit 210 buffer the symbols from the transmitting side according to the symbol clock fs, and the multiplexer 411 has four first half portions. The output signal of the delayers 401-404 is multiplexed according to the multiplexing control signal ctrl, and the other multiplexer 412 multiplexes the output signal of each of the latter four delayers 405-408. Multiplex according to The output signals of the two multiplexers 411 and 412 are respectively input to a multiplier 443 for filtering in the coefficient update / filter unit 420.

The reference signal generator 300 generates an error signal between the reference signal and the channel equalization output signal as an error signal and provides the input signal of the coefficient update / filter unit 420 to update the coefficient of the tap.

Thus, the multiplexer 421 in the coefficient update / filter section 420 has a tap cell 212 connected to the output symbols of the four late delayers 405-408 and the rear end of the filter cell 211, as shown in FIG. The multiplexed output signals of the four delays of the first half of the circuit are input and multiplexed according to the internal operation clock fs4. In this case, the multiplexed symbol of the subsequent tap cell 212 is input because the corresponding symbol is delayed by the time that the error signal is generated in the reference signal generator 300.

The coefficient update / receiving receives the multiplexed output symbols of the four delayers 405-408 of the second half of the filter cell 211 and the multiplexed output signals of the first four delayers of the tap cell 212 connected to the rear end of the filter cell 211. The filter unit 420 updates the tap coefficients with the multiplexed output symbols and error signals of the four delay units 405-408 of the second half of the filter cell 211 whenever the rising edge of the internal operation clock fs4 is generated. Thus, the signal from the transmitting side received by the tap delay unit 400 is multiplied by the updated tap coefficient, and the filtered signal is output and transmitted to the accumulator adder 250 whenever the rising edge of the internal operation clock fs4 is generated.

The coefficient update / filter unit 420 updates the tap coefficients with multiplexed output signals and error signals of the first four delayers of the tap cell 212 whenever a falling edge of the internal operation clock fs4 occurs. The multiplied output signal is multiplied by the updated tap coefficient and the multiplexed output signals of the first four delayers of the tap cell 212 to output the filtered signal for each falling edge of the internal arithmetic clock fs4 to output a filtered adder 250. To pass.

Also, in the tap cell 212 connected to the rear end of the filter cell 211, the buffered symbol in the filter cell 211 is buffered according to a symbol clock, and the same method as the tap coefficient update and filtering operation of the filter cell 211 is performed. When the rising edge and the falling edge of the internal operation clock fs4 are generated, the filtered signal is output to the accumulator adder 250. When the 16th tap is set to the reference tap, a signal received in the direct path from the transmitting side is obtained from the 16th tap. The position of the reference tap selects one of the signals of the 16th, 32, 48th, and 63rd taps as the reference tap signal, and the selected reference tap signal can speed up the offset of the channel distortion.

In addition, the tap delay cell 218 operates in the same manner as the above-described operation of the filter cell 211 to transmit the value filtered by the accumulator adder 250 and the reference tap signal received at the set tap 63.

In addition, the backward filtering unit 22 buffers the reference signal generated by the reference signal generator 300 according to the symbol clock, and operates in the same manner as the operation method of the forward filtering unit 210 to operate the internal operation clock. When the falling edge occurs and the rising edge occurs, the signal filtered by the accumulator adder 250 is respectively output.

Thus, the accumulator adder 250 adds both the filtered signal output when the falling edge of the internal operation clock fs4 and the filtered signal output when the rising edge of the internal operation clock are generated by the forward filtering unit 210. The backward filtering unit 220 adds both the filtered signal output when the falling edge of the internal operation clock and the filtered signal output when the rising edge of the internal operation clock is generated, and the filtered portion of the forward filtering unit 210. The added value of the signal and the added value of the filtered signal of the backward filtering unit 220 are added again, and the symbol output from the reference tap set to the added value is added to finally generate a channel equalization output signal. .

In this operation, the channel equalizer 200 operates in the training mode under the control of the controller 100, and tracks the channel in reverse.

While receiving the field synchronization signal, the control unit 100 controls the high-speed channel equalization system to perform channel equalization in a training mode that cancels channel distortion characteristics through a training sequence previously promised between transmission and reception. When receiving and receiving the data symbol, the controller 100 controls the channel equalization operation to be performed in a blind mode that cancels the channel distortion characteristic through the transmission symbol prediction value at the receiving side.

Thus, when the operation in the blind mode will be described, the reference signal generator 300 predicts a transmission symbol to generate a reference signal, and generates an error signal between the generated reference signal and the channel equalization output signal as an error signal. It operates in the same way as when operating in training mode.

In this operation, the channel equalizer 200 operates under the control of the controller 100 to buffer the input signal according to the symbol clock fs, and to increase the internal operation clock fs4 corresponding to four times the symbol clock. The tap coefficient is updated during one symbol clock by filtering the input signal by the coefficient update of the tap corresponding to half the tap number when it occurs, and filtering the input signal by the coefficient update of the other half when the falling edge of the internal operation clock occurs. In addition, the number of devices of the tap coefficient updater and the filter unit may be reduced to half so as to be implemented as a single module.

Thus, the high-speed channel equalization apparatus of a residual sideband band (VSB) type high definition television (HDTV) receiver corresponds to four times the symbol clock (fs) for a symbol buffered and delayed for one symbol clock (fs). By performing channel equalization by filtering each rising edge and falling edge of the internal operation clock fs4, the number of devices in the channel equalizing device is reduced, so that the overall device configuration is reduced and the delay in the data path is reduced. Performance is improved.

As described above, the present invention ″ a high speed channel equalizer of a residual side wave band (VSB) type high definition television (HDTV) receiver, in particular, buffers an input signal in accordance with a symbol clock (fs) and quadruples the symbol clock. Filter the input signal by counting the taps corresponding to half the number of taps when the rising edge of the internal arithmetic clock (fs4) that corresponds to, and updating the counts of the remaining half taps when the falling edge of the internal arithmetic clock occurs. By filtering the input signal, the total device configuration is reduced by reducing the number of devices updating the tap coefficient and the filtering device in half, and the system performance is improved by reducing the delay in the data path.

Claims (13)

In a channel equalizer that estimates the channel inversely in a residual sideband (VSB) high definition television receiver, A control unit 100 for controlling the mode control and the coefficient update allowing time according to the information on the input data frame, and controlling the channel equalization operation by driving the system to the rising edge and the falling edge of the internal operation clock; When the rising edge of the internal arithmetic clock is generated, the input signal is filtered by updating the coefficient of the tap when the rising edge of the internal arithmetic clock is generated. And a channel equalizer (200) for filtering an input signal by updating coefficients of a corresponding tap when a falling edge of the channel is generated. The high-speed channel equalizer of a high definition television (HDS) receiver of a residual sideband band (VSB) system. The method of claim 1, wherein the channel equalizer 200, Forward filtering to filter the symbols from the transmitting side by updating the coefficients of the corresponding taps when the rising edge and the falling edge of the internal operation clock fs4 corresponding to four times the symbol clock fs are generated. The backward filtering unit 220 filters the reference signal of the rotor from the reference signal generator 300 by updating the coefficient of the tap when the rising edge and the falling edge of the internal operation clock fs4 are generated. And each time the rising edge and the falling edge of the internal operation clock fs4 are generated, the filtered values output from the forward filtering unit 210 and the backward filtering unit 220 are added, and based on the added value. A high-speed channel equalizer of a residual sideband band type high definition television receiver, comprising: a cumulative adder (250) generating a channel equalization output signal by adding a tap signal. The method of claim 2, wherein the forward filtering unit 210, The symbol from the transmitting side is buffered and delayed during the symbol clock fs, and an error signal output from the reference signal generator 300 causes the tap of the rising edge and the falling edge of the internal operation clock fs4 to occur. An internal operation clock fs4 as an error signal output from the reference signal generator 300 by updating a coefficient to filter a buffer cell to filter the buffered symbol, and to buffer and delay the received symbol transmitted from the filter cell connected to the front end. Filter the buffered symbols by updating the coefficients of the tap each time the rising and falling edges of, and selectively sets the number of tap cells that output the symbols received through the direct path from the sender at the set reference tap position. Sequential connection, Filtering the symbol transmitted from the filter cell connected to the front end in the same operation as the filter cell, outputs the symbol in the set reference tab, and delays the symbol by the time required to generate the error signal in the reference signal generator 300 A high-speed channel equalizer of a residual sideband band type high-definition television receiver characterized by connecting a tap delay cell to the last stage. The method of claim 3, wherein the filter cell, A tap delay unit 400 for buffering and delaying an input symbol according to a symbol clock fs, and a multiplexer sequentially multiplexing a symbol delayed and output from the tap delay unit 400 according to a control signal ctrl 411 and 412 and taps each time the rising edge and the falling edge of the internal operation clock fs4 are generated using the error signal output from the reference signal generator 300 to the symbols output from the multiplexer 411. A symbol output from the multiplexer 412 for multiplexing the coefficients of the tap delay unit 400, and multiplexing the first half symbol of the tap delay unit of the tap cell connected to the rear end of the filter cell. The high-speed television receiver of the residual sideband type high-definition television receiver comprising a coefficient update / filter unit 420 for filtering and outputting the rising edge and the falling edge of the internal operation clock fs4 with updated coefficients. Channel equalization device. The method of claim 4, wherein the tap delay unit 400, 8. A high-speed channel equalizer of a residual sideband type high definition television receiver, comprising eight delayers (401-408) for buffering and delaying input symbols for eight symbol clock (fs) periods. The method of claim 4, wherein the coefficient update / filter unit 420, The multiplexed output signal of the four delayers 405-408 of the latter half of the tap delay unit 400 and the multiplexed output signals of the first four delayers of the tap cell connected to the rear end of the filter cell are internally calculated. The multiplexer 421 multiplexed according to the &lt; RTI ID = 0.0 &gt;), &lt; / RTI &gt; the signal output from the multiplexer 421 and the error signal output from the reference signal generator 300 for each falling edge and rising edge of the internal operation clock fs4. A multiplier 422 multiplying, a negative deflip-flop 423 buffering a signal through the multiplier 422 when a falling edge of the internal arithmetic clock fs4 occurs, and a signal through the multiplier 422 A positive deflip-flop 424 buffering and outputting a rising edge, and a multiplexer 425 multiplexing the signals output from the positive-flip-flop 424 and the negative-flip-flop 423 according to an internal operation clock. And the multiplexing A shifter 426 for right shifting the signal through the signal 425 according to the channel distortion canceling speed signal, and according to the signal and the internal operation clock through the shifter 426. An adder 427 that adds the previous symbol that is buffered and delayed, and four positive deflip-flops 428-431 that sequentially buffer and delay the signal through the adder 427 whenever a rising edge of the internal operation clock is generated; Four negative flip-flops 432 to 435 for buffering the signals through the adder 427 and sequentially delaying the falling edges of the internal operation clock, respectively, and the signals output from the positive flip-flop 430. A first rounding / limiting unit 437 for making the set symbol bits, a second rounding / limiting unit 439 for making the signal output from the negative deflip-flop 434 into the set symbol bits, and the first A multiplexer 441 for multiplexing the signals output from the rounding / limiting unit 437 and the second rounding / limiting unit 439 according to an internal operation clock and outputting them as tap coefficient signals, and the multiplexer 411. A multiplexer 442 for multiplexing each of the filter cell input signals output from 412 according to an internal operation clock, and an output signal of the multiplexer 442 for each rising and falling edge of the internal operation clock fs4. A multiplier 443 multiplying the output tap coefficient of the multiplexer 441, a negative deflip-flop 444 for outputting a signal through the multiplier 443 when a falling edge of an internal operation clock is generated, and the multiplier 443 A high-speed channel equalizer of a residual sideband band type high definition television receiver, characterized by comprising a positive deflip-flop (445) for outputting a signal through a rising edge of an internal operation clock. The method of claim 3, wherein the tap cell, The symbol transmitted from the previous filter cell is buffered according to the symbol clock fs, and the buffered symbol is updated when the falling edge of the internal operation clock fs4 corresponding to four times the symbol clock is generated. When the rising edge of the operation clock fs4 occurs, the remaining tap coefficient is updated, the buffer buffered by the updated tap coefficient is filtered, and the reference tap signal received by the direct path from the transmitting side is set to the tap position. A high-speed channel equalizer of a residual sideband band type high-definition television receiver, characterized in that the output from the. The method of claim 3, wherein the tap delay cell, Buffer the symbol transmitted from the tap cell of the previous stage according to the symbol clock (fs), and update the coefficient of the corresponding tap when the falling edge of the internal operation clock (fs4) corresponding to the symbol clock is quadrupled. When the rising edge of the clock fs4 occurs, the remaining tap coefficients are updated, the symbols buffered by the updated tap coefficients are filtered, and the reference tap signal received by the direct path from the transmitting side is transmitted at the set tap position. And a high-speed channel equalization device of a residual sideband-type high-definition television receiver, which outputs and buffers and delays a symbol by a delay time at which an error signal is generated and transmitted by the reference signal generator. The method of claim 2, wherein the backward filtering unit 220, Delay buffering the reference signal generated by the reference signal generator 300 according to the symbol clock fs, and increase the edge of the internal operation clock fs4 as an error signal output from the reference signal generator 300. Filter cell 221 for filtering the buffered reference signal by updating the coefficient of the tap each time the falling edge occurs, and buffer the signal transmitted from the filter cell of the previous stage in the same manner as the filter cell 221, buffering A plurality of filter cells 222-243 for transmitting the delayed reference signal to a filter cell at a later stage, and buffered and filtered reference signals sequentially passed through the filter cells 222-243 according to a symbol clock. High-speed channel of the remaining side waveband type high-definition television receiver, characterized in that it consists of a delay cell 244 delaying the reference signal by the time required to generate an error signal in the signal generator 300 Device. The method of claim 9, wherein the filter cells (221-243), The reference signal transmitted from the reference signal generator 300 is buffered and delayed according to a symbol clock fs, and the symbol is quadrupled using the error signal and the buffered symbol transmitted from the reference signal generator 300. When the falling edge of the internal arithmetic clock fs4 corresponding to the clock fs is generated, the coefficient of the corresponding tap is updated, when the rising edge of the internal arithmetic clock fs4 is updated, the remaining coefficient of the tap is updated, and the updated tap coefficient is updated. A high-speed channel equalization device of a residual sideband band type high-definition television receiver, characterized in that for filtering the reference signal by using. The method of claim 9, wherein the delay cell 244, The reference signal transmitted from the reference signal generator 300 is buffered according to a symbol clock fs to further delay an error signal generated by the reference signal generator 300 by a delay time for transmission, and the reference signal. When the falling edge of the internal arithmetic clock fs4 corresponding to four times the symbol clock fs is generated by using the error signal and the buffered symbol transmitted from the generation unit 300, the coefficient of the corresponding tap is updated, and the internal arithmetic clock When the rising edge of (fs4) is generated, the remaining coefficients of the corresponding taps are updated, and the residual sideband band method is characterized by filtering the reference signal when the rising edge and falling edge of the internal operation clock fs4 are generated using the updated tap coefficient. High-speed channel equalizer for high-definition television receivers. The method of claim 2, wherein the cumulative adder 250, The first carry save ether 600 which adds all the signals output whenever the falling edge of the internal operation clock fs4 is generated by the forward filtering unit 210, and the rising edge of the internal operation clock by the forward filtering unit 210. A second carry save ether 601 that adds all the signals output at each occurrence, and a third carry save ether which adds all the signals output each time a falling edge of the internal operation clock is generated by the backward filtering unit 220 ( 602, a fourth carry save der 603 that adds all the signals output each time the rising edge of the internal operation clock is generated by the backward filtering unit 220, and the four carry save ers 600-603. And an equalization signal generator 610 which adds all of the output signals and adds the reference tap signal output from the forward filtering unit 210 to the addition result value to generate a channel equalization output signal. Residual sidebands band way high-speed channel equalization unit of the high-definition television receiver, characterized by. The method of claim 12, wherein the equalization signal generator 610, When the falling edge of the internal arithmetic clock (fs4) is generated, the filtering value output from the first carry save edder 600 and the third carry save 602, respectively, and the second carry when the rising edge of the internal arithmetic clock (fs4) Adding a filtering value respectively output from the save ether 601 and the fourth carry save ether 603, and adding the reference tap signal received from the reference tap set to the added value to generate a channel equalization output signal. A high speed channel equalizer of a residual sideband band type high definition television receiver.

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