KR100266022B1 - Method of fabricating capacitor - Google Patents

Method of fabricating capacitor Download PDF

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KR100266022B1
KR100266022B1 KR1019970069077A KR19970069077A KR100266022B1 KR 100266022 B1 KR100266022 B1 KR 100266022B1 KR 1019970069077 A KR1019970069077 A KR 1019970069077A KR 19970069077 A KR19970069077 A KR 19970069077A KR 100266022 B1 KR100266022 B1 KR 100266022B1
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South Korea
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layer
lower electrode
forming
insulating material
barrier layer
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KR1019970069077A
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Korean (ko)
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KR19990050041A (en
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이준식
이인순
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/75—Electrodes comprising two or more layers, e.g. comprising a barrier layer and a metal layer

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A capacitor formation method is provided to minimize losses of effective area of a lower electrode and to prevent an oxidation of a metal barrier layer when annealing a dielectric film. CONSTITUTION: After forming a polysilicon layer on a semiconductor substrate(200) having transistors, a polysilicon plug(p2) is formed by etching the polysilicon layer. By sequentially depositing and patterning metal films, such as Ti/TiN and a refractory metal film, a first barrier layer and a lower electrode(204) are formed on the polysilicon plug(p2). By wet etching the first barrier layer, an undercutting barrier layer(202-1) is formed. Then, an insulating spacer(206) is formed at both sidewalls of the undercutting barrier layer(202-1) in order to prevent an oxidation of the barrier metal(202-1). Then, a dielectric film(208) is formed on the resultant structure.

Description

캐패시터 형성방법Capacitor Formation Method

본 발명은 캐패시터(capacitor) 형성방법에 관한 것으로, 특히, 하부전극의 유효면적의 손실을 최소화하기에 적당한 캐패시터 형성방법에 관한 것이다.The present invention relates to a method of forming a capacitor, and more particularly, to a method of forming a capacitor suitable to minimize the loss of the effective area of the lower electrode.

반도체장치의 고집적화에 따라 셀(cell) 면적이 축소되어도 커패시터가 일정한 축전 용량을 갖도록 축전 밀도를 증가시키기 위한 많은 연구가 진행되고 있으며, 이 축전 용량을 증가시키기 위해서는 캐패시터를 적층(stacked) 또는 트렌치(trench)의 3차원 구조로 형성하여 유전층의 표면적을 증가시키어 왔다.Due to the high integration of semiconductor devices, many studies have been conducted to increase the storage density so that a capacitor has a constant storage capacity even if the cell area is reduced. The three-dimensional structure of the trench has been increased to increase the surface area of the dielectric layer.

그러나, 적층 캐패시터 또는 트렌치 캐패시터는 제조 공정이 복잡하여 유전층의 표면적을 증가시키는 데 한계가 있으므로, 캐패시터의 유전층을 산화탄탈늄(Ta2O5) 또는 PZT(Pb(Zr Ti)O3) 또는 BST((Ba Sr)TiO3) 등의 고유전 물질을 사용하여 유전층을 형성함으로써 축전 용량을 증가시키는 기술이 종래에 제안된 바가 있다.However, the layered capacitor or a trench capacitor is because there is a limit to which the manufacturing process is complicated to increase the surface area of the dielectric layer, oxidation of the dielectric layer of the capacitor tantalum (Ta 2 O 5) or PZT (Pb (Zr Ti) O 3) or BST A technique for increasing the storage capacity by forming a dielectric layer using a high dielectric material such as ((Ba Sr) TiO 3 ) has been proposed in the past.

도 1a 내지 도 1c 는 종래기술에 따른 캐패시터 형성을 위한 제조공정도이다.1a to 1c is a manufacturing process diagram for forming a capacitor according to the prior art.

도면에 도시되지는 않았지만, 반도체기판(100)에는 소자의 활성영역과 필드영역을 한정하는 필드산화층이 형성되어져 있고, 소자의 활성영역 상에 게이트산화층이 개재된 게이트전극이 형성되어져 있고, 이 게이트전극 양측의 활성영역에 소오스/드레인영역으로 이용되는 불순물 확산영역을 형성함으로써 트랜지스터(transistor)가 형성되어져 있다. 그리고 상술한 트랜지스터를 덮고 불순물영역을 노출시키는 접촉구가 형성된 층간절연층으로 이루어져 있다.Although not shown in the drawing, the semiconductor substrate 100 has a field oxide layer defining an active region and a field region of the device, and a gate electrode interposed with a gate oxide layer on the active region of the device. Transistors are formed by forming impurity diffusion regions used as source / drain regions in the active regions on both sides of the electrode. And an interlayer insulating layer formed with a contact hole covering the transistor described above and exposing an impurity region.

도 1a 와 같이, 상술한 반도체기판(100) 상에 접촉구를 덮도록 다결정실리콘층을 형성한 후, 식각하여 다결정실리콘 플러그(p1)를 형성한다.As shown in FIG. 1A, after the polysilicon layer is formed on the semiconductor substrate 100 to cover the contact hole, the polysilicon plug p1 is formed by etching.

반도체기판(100) 상에 다결정실리콘 플러그(p1)을 덮도록 Ti/TiN 등의 금속층을 형성한 후, 그 상부에 고융점을 갖는 귀금속층을 적층한다. 이 금속층 및 귀금속층을 일정영역 패터닝하여 제 1장벽금속층(102) 및 하부전극(104)을 형성한다. 상술한 제 1장벽금속층(102)은 하부전극(104)을 형성하기 위한 귀금속 성분이 다결정실리콘 플러그(p1) 내로 확산되는 것을 방지하는 역할을 한다.After forming a metal layer such as Ti / TiN on the semiconductor substrate 100 so as to cover the polysilicon plug p1, a noble metal layer having a high melting point is stacked thereon. The metal layer and the noble metal layer are patterned to form a first barrier metal layer 102 and the lower electrode 104. The first barrier metal layer 102 described above serves to prevent diffusion of a noble metal component for forming the lower electrode 104 into the polysilicon plug p1.

이 후에, 하부전극(104)을 덮는 절연물질층(106)을 형성한다.Thereafter, an insulating material layer 106 covering the lower electrode 104 is formed.

도 1b 와 같이, 절연물질층(106)을 에치백하여 장벽금속층(102) 및 하부전극(104) 측면에 스페이서(106-1)를 형성한다. 이 스페이서(106-1)은 이 후의 유전층 열처리 공정에서 가해지는 열로 인하여 금속장벽층(102)이 산화되는 것을 방지하기 위한 것이다.As shown in FIG. 1B, the insulating material layer 106 is etched back to form spacers 106-1 on sidewalls of the barrier metal layer 102 and the lower electrode 104. This spacer 106-1 is for preventing the metal barrier layer 102 from being oxidized due to the heat applied in the subsequent dielectric layer heat treatment process.

도 1c 와 같이, 반도체기판(100) 상에 하부전극(102) 및 스페이서(106-1)를 덮도록 산화탄탈늄(Ta2O5)(108)등을 이용하여 유전층(106)을 적층하여 형성한다.As shown in FIG. 1C, the dielectric layer 106 is stacked on the semiconductor substrate 100 by using tantalum oxide (Ta 2 O 5 ) 108 or the like to cover the lower electrode 102 and the spacer 106-1. Form.

이 때, 산화탄탈늄은 금속화되기 쉬우며, 유전층(106)인 산화탄탈늄층이 금속화된다는 것은 곧 도전성질을 갖게된다는 것으로 이를 통해 누설전류가 흐르게 될 우려가 있다.At this time, tantalum oxide is likely to be metallized, and the tantalum oxide layer, which is the dielectric layer 106, is metallized, which may have a conductive property, and thus leakage current may flow.

그러므로, 이를 방지하기 위해서는 산소분위기에서 산화탄탈늄층에 고온에서 열처리공정을 실시함으로써 산화탄탈늄의 금속화를 방지하고 공정챔버 내에 잔재된 불순물 함량을 줄이어 유전층의 전기적 특성을 강화하였다.Therefore, in order to prevent this, the tantalum oxide layer is heat treated at a high temperature in an oxygen atmosphere to prevent metallization of tantalum oxide and to reduce the content of impurities remaining in the process chamber to enhance the electrical characteristics of the dielectric layer.

그러나, 종래의 기술에서는 제 2장벽금속층이 하부전극의 하부 측면을 감싸고 있으므로, 결과적으로, 하부전극의 표면적이 감소된다. 따라서, 캐패시터의 축전용량이 감소되는 문제점이 있었다.However, in the prior art, since the second barrier metal layer surrounds the lower side of the lower electrode, the surface area of the lower electrode is reduced as a result. Therefore, there was a problem that the capacitance of the capacitor is reduced.

따라서, 상기의 문제점을 해결하고자 본 발명은 캐패시터의 하부전극의 유효면적이 감소되는 것을 방지가능한 캐패시터 형성방법을 제공하려는 것이다.Accordingly, an object of the present invention is to provide a method of forming a capacitor capable of preventing the effective area of the lower electrode of the capacitor from being reduced.

본 발명의 캐패시터 형성방법은 불순물영역을 포함하는 트랜지스터가 형성된 반도체기판에 불순물영역을 노출시키는 접촉홀 및 접촉홀을 채우는 다결정실리콘 플러그를 갖도록 층간절연층을 형성하는 공정과, 층간절연층 상에 다결정실리콘 플러그를 덮도록 금속장벽층 및 하부전극을 순차적으로 형성하는 공정과, 장벽금속층의 일부를 제거한 후에 제거된 부위의 측면에 잔류되도록 절연물질층을 형성하는 공정과, 절연물질층 및 하부전극을 덮도록 유전층을 형성하는 공정을 구비한 것을 특징으로 한다.The capacitor forming method of the present invention comprises the steps of forming an interlayer insulating layer having a contact hole exposing an impurity region and a polysilicon plug filling a contact hole in a semiconductor substrate on which a transistor including an impurity region is formed, and a polycrystal on the interlayer insulating layer. Forming a metal barrier layer and a lower electrode so as to cover the silicon plug; and forming an insulating material layer so as to remain on the side of the removed portion after removing a part of the barrier metal layer; And forming a dielectric layer so as to cover the dielectric layer.

도 1a 내지 도 1c 는 종래기술에 따른 캐패시터 형성을 위한 제조공정도이다.1a to 1c is a manufacturing process diagram for forming a capacitor according to the prior art.

도 2a 내지 도 2d 는 본 발명에 따른 캐패시터 형성을 위한 제조공정도이다.2A to 2D are manufacturing process diagrams for forming a capacitor according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100, 200. 반도체기판 102, 202. 금속장벽층100, 200. Semiconductor substrate 102, 202. Metal barrier layer

104, 204. 하부전극 106, 206. 절연물질층104, 204. Lower electrodes 106, 206. Insulating material layer

108, 208. 유전층108, 208. The dielectric layer

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하겠다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2a 내지 도 2d 는 본 발명에 따른 캐패시터 형성을 위한 제조공정도이다.2A to 2D are manufacturing process diagrams for forming a capacitor according to the present invention.

도 2 와 같이, 종래기술에 상술한 방법에 의해, 반도체기판(200)에는 불순물영역을 갖는 트랜지스터가 형성되어져 있고, 상술한 트랜지스터를 덮고 불순물영역을 노출시키는 접촉구가 형성된 층간절연층으로 이루어져 있다.As shown in Fig. 2, by the method described above in the prior art, the semiconductor substrate 200 is formed with a transistor having an impurity region, and is formed of an interlayer insulating layer having a contact hole for covering the transistor and exposing the impurity region. .

도 2a 와 같이, 상술한 반도체기판(200) 상에 접촉구를 덮도록 다결정실리콘층을 형성한 후, 식각하여 다결정실리콘 플러그(p2)를 형성한다.As shown in FIG. 2A, after the polysilicon layer is formed on the semiconductor substrate 200 to cover the contact hole, the polysilicon plug p2 is formed by etching.

반도체기판(200) 상에 다결정실리콘 플러그(p2)을 덮도록 Ti/TiN 등의 금속층을 형성한 후, 그 상부에 고융점을 갖는 귀금속층을 적층한다. 이 금속층 및 귀금속층을 일정영역 패터닝하여 제 1장벽금속층(202) 및 하부전극(204)을 형성한다. 상술한 제 1장벽금속층(202)은 하부전극(204)을 형성하기 위한 귀금속 성분이 다결정실리콘 플러그(p2) 내로 확산되는 것을 방지하는 역할을 한다.After forming a metal layer such as Ti / TiN on the semiconductor substrate 200 to cover the polysilicon plug p2, a noble metal layer having a high melting point is stacked thereon. The metal layer and the noble metal layer are patterned to form a first barrier metal layer 202 and a lower electrode 204. The first barrier metal layer 202 described above serves to prevent diffusion of a noble metal component for forming the lower electrode 204 into the polysilicon plug p2.

도 2b 와 같이, 습식식각 방법 등을 이용하여 제 1장벽금속층(202)의 일부를 제거한 후, 하부전극(204)를 덮되, 일부 제거된 제 1장벽금속층(202-1)의 측면을 채우도록 절연물질층(206)을 형성한다. 이 절연물질층(206)은 산화실리콘 등의 산화물을 SOG(Spin On Glass)방식으로 형성한다.As shown in FIG. 2B, after a part of the first barrier metal layer 202 is removed using a wet etching method, the lower electrode 204 is covered to fill the side surface of the partially removed first barrier metal layer 202-1. An insulating material layer 206 is formed. The insulating material layer 206 forms an oxide such as silicon oxide in a spin on glass (SOG) method.

도 2c 와 같이, 하부전극(204)을 마스크로 이용하여 절연물질층(206)을 제거하여 제 1장벽금속층(202-1)의 측면에 잔류시키어 측벽(206)을 형성한다.As illustrated in FIG. 2C, the insulating material layer 206 is removed using the lower electrode 204 as a mask, and the sidewall 206 is formed by leaving the insulating material layer 206 on the side of the first barrier metal layer 202-1.

이 절연물질층(206)은 장벽금속층(206)을 감싸고 있는 형태로, 이 후의 유전체 열처리 공정 시, 장벽금속층(202-1)이 산화되는 것을 방지하는 역할을 한다.The insulating material layer 206 surrounds the barrier metal layer 206, and serves to prevent the barrier metal layer 202-1 from being oxidized during the subsequent dielectric heat treatment process.

따라서, 본 발명의 절연물질층(206)은 장벽금속층(202)의 측면을 일부 건식식각 또는 습식식각 방법으로 제거하고, 제거된 부위에만 잔류시키고 하부전극을 노출시킴으로써 하부전극의 유효면적을 확보할 수 있다.Accordingly, the insulating material layer 206 of the present invention can secure the effective area of the lower electrode by removing the side surface of the barrier metal layer 202 by some dry etching or wet etching method, remaining only at the removed portion, and exposing the lower electrode. Can be.

도 2d 와 같이, 잔류된 절연물질층(206)및 하부전극(204)을 덮도록 유전체(208)을 형성한다.As shown in FIG. 2D, the dielectric 208 is formed to cover the remaining insulating material layer 206 and the lower electrode 204.

이 유전체(206)로는 산화탄탈늄(Ta2O5)을 이용하며, 이 산화탄탈늄은 제조 시, 그 표면 및 공정챔버에는 불순물이 다량 잔류되어 있으며, 또한, 결합 자체도 불안정한 상태이다.Tantalum oxide (Ta 2 O 5 ) is used as the dielectric 206. When the tantalum oxide is manufactured, a large amount of impurities remain on its surface and the process chamber, and the bond itself is also unstable.

또한, 산화탄탈늄은 금속화되기 쉬우며, 유전층(206)인 산화탄탈늄층이 금속화된다는 것은 곧 도전성질을 갖게된다는 것으로 이를 통해 누설전류가 흐르게 될 우려가 있다.In addition, tantalum oxide is easily metallized, and the metallization of the tantalum oxide layer, which is the dielectric layer 206, may have a conductive property, which may cause leakage current to flow therethrough.

따라서, 산화탄탈늄 표면 및 공정챔버 내부에 잔류된 불순물을 제거하고 불안정한 결합을 보다 안정하게 하고 금속화되는 것을 방지하기 위해서는, 산소분위기에서 고온에서 빠른 열처리(RTO:Rapidly Thermal Oxidation)를 진행시킨다. 즉, 산소분위기에서 단시간 내에 고온의 열처리과정을 통해 어닐링을 실시하여 층질 내에 존재하는 불순물, 결함, 결정경계면(grain boundary) 등과 같이 열역학적으로 불안정한 부위를 활성화시킨다.Therefore, in order to remove impurities remaining on the tantalum oxide surface and the inside of the process chamber, to make unstable bonds more stable, and to prevent metallization, rapid thermal oxidation (RTO) is performed at high temperature in an oxygen atmosphere. In other words, annealing is performed in an oxygen atmosphere through a high temperature heat treatment process within a short time to activate thermodynamically unstable sites such as impurities, defects, grain boundaries, etc. present in the layer.

그리고 산화탄탈늄의 금속화가 방지되고 공정챔버 내에 잔재된 불순물 함량을 줄이어 유전층의 전기적 특성을 강화한다.In addition, the metallization of tantalum oxide is prevented and the amount of impurities remaining in the process chamber is reduced to enhance the electrical characteristics of the dielectric layer.

상술한 바와 같이, 본 발명의 캐패시터 형성방법에서는 캐패시터의 유전층을 고온에서 열처리 공정 진행시키는 과정에서 금속장벽층이 산화되는 것을 방지할 수 있다.As described above, in the capacitor forming method of the present invention, the metal barrier layer may be prevented from being oxidized during the heat treatment process of the dielectric layer of the capacitor at a high temperature.

또한, 하부전극의 유효면적이 손실없이 캐패시터를 형성할 수 있는 잇점이 있다.In addition, there is an advantage that a capacitor can be formed without losing the effective area of the lower electrode.

Claims (3)

불순물영역을 포함하는 트랜지스터가 형성된 반도체기판에 상기 불순물영역을 노출시키는 접촉홀 및 상기 접촉홀을 채우는 다결정실리콘 플러그를 갖도록 층간절연층을 형성하는 공정과,Forming an interlayer insulating layer on a semiconductor substrate having a transistor including an impurity region and having a contact hole exposing the impurity region and a polysilicon plug filling the contact hole; 상기 층간절연층 상에 상기 다결정실리콘 플러그를 덮도록 금속장벽층 및 하부전극을 순차적으로 형성하는 공정과,Sequentially forming a metal barrier layer and a lower electrode on the interlayer insulating layer to cover the polysilicon plug; 상기 장벽금속층의 측면 일부를 식각하여 상기 하부전극의 바닥면의 일부위를 노출시키는 공정과,Etching a portion of the side surface of the barrier metal layer to expose a portion of the bottom surface of the lower electrode; 상기 층간절연층 상에 상기 식각된 장벽금속층의 측면을 채우고 상기 하부전극의 노출된 바닥면을 가리도록 절연물질층을 형성하는 공정과,Forming an insulating material layer on the interlayer insulating layer so as to fill a side surface of the etched barrier metal layer and cover an exposed bottom surface of the lower electrode; 상기 절연물질층 및 하부전극을 덮도록 유전층을 형성하는 공정을 구비한 캐패시터 형성방법.And forming a dielectric layer to cover the insulating material layer and the lower electrode. 청구항 1에 있어서,The method according to claim 1, 상기 절연물질층은 SOG(Spin On Glass) 방식으로 도포한 것이 특징인 캐패시터 형성방법.The insulating material layer is a capacitor forming method characterized in that the coating on the SOG (Spin On Glass) method. 청구항 1 또는 청구항 2에 있어서,The method according to claim 1 or 2, 상기 절연물질층은 산화물질인 것이 특징인 캐패시터 형성방법.And the insulating material layer is oxide.
KR1019970069077A 1997-12-16 1997-12-16 Method of fabricating capacitor KR100266022B1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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