KR100261684B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR100261684B1 KR100261684B1 KR1019970077381A KR19970077381A KR100261684B1 KR 100261684 B1 KR100261684 B1 KR 100261684B1 KR 1019970077381 A KR1019970077381 A KR 1019970077381A KR 19970077381 A KR19970077381 A KR 19970077381A KR 100261684 B1 KR100261684 B1 KR 100261684B1
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- oxide film
- gate electrode
- entire surface
- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 150000004767 nitrides Chemical class 0.000 claims abstract description 17
- 125000006850 spacer group Chemical group 0.000 claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000006731 degradation reaction Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005465 channeling Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28238—Making the insulator with sacrificial oxide
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 자기정렬콘택방식에 적용할 수 있는 질화막 스페이서를 이용하는 장치에서 질화막 스페이서 하부의 포스트산화막으로 고온산화막(High Temperature Oxide 이하, HTO)을 형성함으로서 소자의 전기적 특성을 향상시키는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, in a device using a nitride film spacer applicable to a self-aligned contact method, a high temperature oxide film (HTO) is formed as a post oxide film under a nitride film spacer. The present invention relates to a technique for improving electrical characteristics.
일반적으로, 반도체 소자에서 상하의 도전배선을 연결하는 콘택홀은 자체의 크기와 주변 배선과의 간격이 감소되고, 콘택홀의 지름과 깊이의 비인 에스팩트비(aspect ratio)는 증가한다.In general, the contact hole connecting the upper and lower conductive wirings in the semiconductor device is reduced in size and the distance between the peripheral wiring and the aspect ratio, which is the ratio of the diameter and the depth of the contact hole, is increased.
따라서, 다층의 도전배선을 구비하는 고집적 반도체소자에서는 콘택을 형성하기 위하여 제조 공정에서의 마스크들간의 정확하고 엄격한 정렬이 요구되어 공정여유도가 감소된다.Therefore, in a highly integrated semiconductor device having multiple conductive wirings, accurate and tight alignment between masks in a manufacturing process is required to form a contact, thereby reducing process margin.
상기 콘택홀은 간격 유지를 위하여 마스크 정렬시의 오배열 여유(misalig㎚ent tolerance), 노광 공정시의 렌즈 왜곡(lens distortion), 마스크 제작 및 사진식각 공정시의 임계크기 변화(critical dimension variation), 마스크간의 정합(registration)등과 같은 요인들을 고려하여 마스크를 형성한다.The contact hole may be misalignment tolerance during mask alignment, lens distortion during exposure, critical dimension variation during mask fabrication and photolithography, to maintain the spacing, The mask is formed by considering factors such as registration between the masks.
또한, 콘택홀 형성시 리소그래피(Lithography) 공정의 한계를 극복하기 위하여 자기정렬콘택(self-align contact; 이하, SAC) 형성 기술이 개발되었다.In addition, self-aligned contact (SAC) formation technology has been developed to overcome the limitations of the lithography process when forming contact holes.
한편, 64M DRAM 이상의 디바이스(device)에서 SAC 형성기술을 적용하기 위해 게이트전극 측벽에 절연 스페이서로 질화막을 사용하는 디바이스에서 질화막 스트레스(nitride stress)의 완화(release)를 위해 질화막 증착전에 포스트산화막(post oxide)을 증착한다.On the other hand, in a device using a nitride film as an insulating spacer on the sidewall of the gate electrode to apply the SAC formation technique to a device of 64M DRAM or more, a post oxide film is deposited before nitride film deposition for release of nitride stress. oxide).
상기 포스트산화막으로는 저온(Low Temperature)-화학기상증착(Cemical Vapor Deposition) 산화막 또는 중온(Medium Temperature)-화학기상증착(Cemical Vapor Deposition) 산화막을 주로 사용하는데, 포스트산화막의 구조의 따른 스트레스 유발(induced)로 산화막 손상(damage) 및 핫캐리어(hot carrier) 저하가 발생되어 소자의 신뢰성(reliability)을 떨어뜨리는 문제점이 있다.As the post oxide film, a low temperature (Cemical Vapor Deposition) oxide film or a medium temperature (Chemical Vapor Deposition) oxide film is mainly used. Oxide film damage and hot carrier degradation occur due to induced degradation of device reliability.
이에, 본 발명은 상기한 문제점을 해결하기 위한 것으로 자기정렬콘택방식에 적용할 수 있는 질화막 스페이서 장치에서 HTO막으로 이루어진 포스트 산화막을 게이트전극 상부의 희생산화막 상부에 형성한 후, 전표면에 질화막을 형성하고 전면식각하여 게이트전극 측벽에 질화막 스페이서를 형성함으로서 포스트산화막의 구조에 따른 질화막 스트레스 유발(induced)로 인해 발생하는 산화막 손상(damage) 및 핫 캐리어(hot carrier) 저하를 방지하여 소자의 전기적 특성 및 신뢰성을 향상시키는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention is to solve the above problems, in the nitride spacer device which can be applied to the self-aligned contact method, a post oxide film made of HTO film is formed on the sacrificial oxide film on the gate electrode, and the nitride film is formed on the entire surface. By forming the nitride film spacer on the sidewall of the gate electrode by forming and etching the entire surface of the gate electrode, the electrical properties of the device are prevented by preventing the damage of the oxide film and the deterioration of the hot carrier caused by the nitride film stress induced by the post oxide film structure. And to provide a method for manufacturing a semiconductor device to improve the reliability.
도 1a 내지 도 1d 는 본 발명에 따른 반도체 소자의 제조공정도1A to 1D are manufacturing process diagrams of a semiconductor device according to the present invention.
＜도면의 주요 부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
10 : 반도체 기판 12 : 게이트전극10
14 : 희생산화막 16 : 포스트산화막14: sacrificial oxide film 16: post oxide film
18 : 질화막 스페이서18: nitride film spacer
상기 목적을 달성하기 위해 본 발명에 따르면,According to the present invention to achieve the above object,
반도체 기판 상부에 게이트산화막과 게이트전극을 형성하는 공정과,Forming a gate oxide film and a gate electrode on the semiconductor substrate;
상기 구조의 전표면에 희생산화막을 형성하는 공정과,Forming a sacrificial oxide film on the entire surface of the structure;
상기 희생산화막 상부에 이온주입 공정을 실시하여 상기 게이트전극 양측의 반도체 기판에 소오스/드레인 확산영역을 형성하는 공정과,Forming a source / drain diffusion region in the semiconductor substrate on both sides of the gate electrode by performing an ion implantation process on the sacrificial oxide film;
상기 구조의 전표면에 포스트산화막을 형성하는 공정과,Forming a post oxide film on the entire surface of the structure;
상기 게이트전극 측벽에 질화막 스페이서를 형성하는 공정과,Forming a nitride film spacer on the sidewalls of the gate electrode;
상기 구조의 전표면에 열처리공정을 실시하는 공정을 포함하는 것을 특징으로 한다.It characterized in that it comprises a step of performing a heat treatment process on the entire surface of the structure.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d 는 본 발명에 따른 반도체 소자의 제조공정도이다.1A to 1D are manufacturing process diagrams of a semiconductor device according to the present invention.
먼저, 반도체 기판(10) 상부에 소자분리를 위한 필드산화막(도시 안됨)과 게이트산화막(도시 안됨)과 폴리실리콘막패턴으로된 게이트전극(12)을 순차적으로 형성한 다음, 희생산화 공정을 거쳐 상기 구조의 전표면에 희생산화막(14)을 형성한다.First, a field oxide film (not shown), a gate oxide film (not shown), and a
이 때, 상기 희생산화 공정은 쇼트채널효과(short channel effect)을 방지하기 위함이다.(도 1a 참조)At this time, the sacrificial oxidation process is to prevent a short channel effect (see Fig. 1a).
다음, 상기 희생산화막(14) 상부에 불순물 이온주입 공정을 실시하여 상기 게이트전극(12) 양측의 반도체 기판(10)에 소오스/드레인 확산영역(도시 안됨)을 형성한다.(도 1b 참조)Next, an impurity ion implantation process is performed on the
그 다음, 상기 구조의 전표면에 포스트산화막(16)을 형성한다.Next, a
여기서, 상기 포스트산화막(16)은 고온산화(High Temperature Oxide 이하, HTO)막으로 800 ∼ 900℃ 온도에서 200 ∼ 300Å 두께로 형성한다.Here, the
이 때, 상기 포스트산화막(16)으로 HTO막을 형성함으로서 종래의 200 ∼ 300℃ 온도에서 질화막 스페이서의 스트레스 유발(induced)로 산화막 손상(damage) 및 핫캐리어(hot carrier) 저하를 방지할 수 있다.At this time, by forming the HTO film with the
또한, 상기 희생산화 공정을 열산화공정으로 대체하여 800 ∼ 900℃ 온도에서 100 ∼ 300Å 두께의 열산화막(도시 안됨)을 형성한 다음, 후속 공정의 포스트산화막(16) 형성 공정을 생략하여도 질화막 스페이서의 스트레스 유발을 방지할 수 있다.(도 1c 참조)In addition, the sacrificial oxidation process is replaced with a thermal oxidation process to form a thermal oxide film (not shown) having a thickness of 100 to 300 kPa at a temperature of 800 to 900 ° C., and then the
다음, 상기 구조의 전표면에 스페이서 형성을 위한 질화막을 형성한 다음, 전면식각하여 상기 게이트전극(12) 측벽에 질화막 스페이서(18)를 형성한다.Next, a nitride film for forming a spacer is formed on the entire surface of the structure, and then the entire surface is etched to form a
이 때, 상기 질화막 스페이서(18)는 임플란트 공정시의 채널닝(channeling)현상을 방지할 목적으로 산화막 두께 조절을 할 수 있다.In this case, the
그 다음, 후속 공정으로 상기 구조의 전표면에 소자의 전기적 특성을 향상시키기 위해 열처리공정을 실시한다.Subsequently, a subsequent heat treatment is performed to improve the electrical characteristics of the device on the entire surface of the structure.
이 때, 상기 열처리 공정을 질소분위기에서 실시하여 600 ∼ 1000Å 두께의 열산화막(도시 안됨)을 형성한다.(도 1d 참조)At this time, the heat treatment step is carried out in a nitrogen atmosphere to form a thermal oxide film (not shown) having a thickness of 600 to 1000 kPa (see FIG. 1D).
상기한 바와같이 본 발명에 따르면, 게이트전극 상부에 희생산화막과 HTO막으로 이루어진 포스트 산화막을 형성한 후, 전표면에 질화막을 형성하고 전면식각하여 게이트전극 측벽에 질화막 스페이서를 형성함으로서 포스트산화막의 구조에 따른 질화막 스트레스 유발(induced)로 인해 발생하는 산화막 손상(damage) 및 핫 캐리어(hot carrier) 저하를 방지하여 소자의 전기적 특성 및 신뢰성을 향상시키는 이점이 있다.As described above, according to the present invention, after forming a post oxide film formed of a sacrificial oxide film and an HTO film on the gate electrode, a nitride film is formed on the entire surface, and the entire surface is etched to form nitride spacers on the sidewalls of the gate electrode. By preventing oxide damage and hot carrier degradation caused by nitride film stress induced (induced), there is an advantage to improve the electrical characteristics and reliability of the device.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970077381A KR100261684B1 (en) | 1997-12-29 | 1997-12-29 | Method for fabricating semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970077381A KR100261684B1 (en) | 1997-12-29 | 1997-12-29 | Method for fabricating semiconductor device |
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| Publication Number | Publication Date |
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| KR19990057330A KR19990057330A (en) | 1999-07-15 |
| KR100261684B1 true KR100261684B1 (en) | 2000-07-15 |
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| KR1019970077381A KR100261684B1 (en) | 1997-12-29 | 1997-12-29 | Method for fabricating semiconductor device |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100680943B1 (en) * | 2001-06-28 | 2007-02-08 | 주식회사 하이닉스반도체 | Method for forming transistor in semiconductor device |
| KR100426811B1 (en) * | 2001-07-12 | 2004-04-08 | 삼성전자주식회사 | Semiconductor device having SAC and Fabrication Method thereof |
| KR100489525B1 (en) * | 2002-04-16 | 2005-05-16 | 동부아남반도체 주식회사 | Method for preventing divot form a time spacer formation |
| KR100433490B1 (en) * | 2002-06-25 | 2004-05-31 | 동부전자 주식회사 | Method of manufacturing semiconductor device |
| KR100906940B1 (en) * | 2002-11-26 | 2009-07-10 | 매그나칩 반도체 유한회사 | Method of manufacturing a transistor in a semiconductor device |
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| KR19990057330A (en) | 1999-07-15 |
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