KR100261159B1 - Method for forming isolation region of semiconductor device - Google Patents

Method for forming isolation region of semiconductor device Download PDF

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KR100261159B1
KR100261159B1 KR1019970033162A KR19970033162A KR100261159B1 KR 100261159 B1 KR100261159 B1 KR 100261159B1 KR 1019970033162 A KR1019970033162 A KR 1019970033162A KR 19970033162 A KR19970033162 A KR 19970033162A KR 100261159 B1 KR100261159 B1 KR 100261159B1
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layer
semiconductor layer
insulating film
film
isolation region
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KR1019970033162A
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KR19990010373A (en
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장세진
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

PURPOSE: An isolation region of a semiconductor device and a method for forming the same are provided to improve an operating characteristic of an SOI substrate by forming an isolation region. CONSTITUTION: The first conductive semiconductor substrate(21) and an SOI substrate laminated with an isolation layer(22) and a semiconductor layer(22) are prepared. The first conductive type ion is implanted on the semiconductor layer(22). The first insulating layer and the second insulating layer are laminated on the semiconductor layer(22). A plurality fine pattern is formed by etching the first and the second insulating layers and the semiconductor layer(22). A field oxide layer(27) is formed by oxidizing a side of the semiconductor layer(22). The second insulating layer is removed. The field oxide layer(27) is smoothened by performing an etching process.

Description

반도체 소자의 격리영역 형성방법{Method for forming isolation region of semiconductor device}Method for forming isolation region of semiconductor device

본 발명은 반도체 소자에 대한 것으로 특히, SOI기판에 동작특성을 개선할 수 있는 반도체 소자의 격리영역을 형성하기 위한 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for forming an isolation region of a semiconductor device capable of improving operating characteristics on an SOI substrate.

도면을 참조하여 종래 반도체 소자의 격리영역 형성방법에 대하여 설명하면 다음과 같다.A method of forming an isolation region of a conventional semiconductor device will now be described with reference to the accompanying drawings.

도 1a 내지 1e는 종래 반도체 소자의 격리영역 형성방법을 나타낸 단면도이다.1A to 1E are cross-sectional views illustrating a method of forming an isolation region of a conventional semiconductor device.

SOI(Silicon On Insulation)기판에 격리영역을 형성하는 방법에 대한 것으로 도 1a에 도시한 바와 같이 p형 반도체 기판(1)과 p형 실리콘층(3)사이에 산화막으로된 격리층(2)을 가진 SOI기판을 준비한다. 이후에 상기 실리콘층(3)내에 채널 스톱이온으로 p형의 보론(Boron)이온을 주입한다.A method of forming an isolation region on a silicon on insulation (SOI) substrate, and as shown in FIG. 1A, an isolation layer 2 made of an oxide film is formed between a p-type semiconductor substrate 1 and a p-type silicon layer 3. Prepare the SOI substrate with Thereafter, p-type boron ions are implanted into the silicon layer 3 as channel stop ions.

도 1b에 도시한 바와 같이 상기 반도체 기판(1)상에 산화막과 질화막을 차례로 증착하여 버퍼산화막(4)과 산화방지막(5)을 형성한다.As shown in FIG. 1B, an oxide film and a nitride film are sequentially deposited on the semiconductor substrate 1 to form a buffer oxide film 4 and an antioxidant film 5.

도 1c에 도시한 바와 같이 전면에 감광막(6)을 도포한 후 필드영역으로 정의된 소정부분의 감광막(6)을 노광 및 현상공정으로 선택적으로 패터닝한다. 이후에 패터닝된 감광막(6)을 마스크로 이용하여 산화방지막(5)과 버퍼산화막(4)을 이방성 식각한 후 감광막(6)을 제거한다.As shown in FIG. 1C, after the photoresist film 6 is applied to the entire surface, the photoresist film 6 in a predetermined portion defined as a field region is selectively patterned by an exposure and development process. Subsequently, the antioxidant film 5 and the buffer oxide film 4 are anisotropically etched using the patterned photosensitive film 6 as a mask, and then the photosensitive film 6 is removed.

도 1d에 도시한 바와 같이 상기 산화방지막(5)을 마스크로 실리콘층(3)을 열산화하여 상기 격리층(2)까지 필드산화막(7)을 형성한다.As shown in FIG. 1D, the silicon layer 3 is thermally oxidized using the antioxidant film 5 as a mask to form a field oxide film 7 up to the isolation layer 2.

도 1e에 도시한 바와 같이 산화방지막(5)과 버퍼산화막(4)을 제거하여 SOI 기판에 필드산화막(7)이 형성되도록 한다. 이후에 활성영역에 게이트산화막과 게이트 전극과 소오스/드레인 영역을 형성한다.As shown in FIG. 1E, the oxide film 5 and the buffer oxide film 4 are removed to form the field oxide film 7 on the SOI substrate. Thereafter, a gate oxide film, a gate electrode, and a source / drain region are formed in the active region.

상기와 같이 형성되는 종래 반도체 소자의 격리영역 형성방법은 다음과 같은 문제점이 있다.The method of forming an isolation region of a conventional semiconductor device formed as described above has the following problems.

첫째, 격리층과 접촉되도록 필드산화막을 형성할 때 실리콘층에 주입된 보론이온이 필드산화막 하부와 격리층상부에 누적되어 도핑밀도가 높아지고 이와 같은 현상에 의하여 차후에 형성되는 n형의 소오스/드레인 영역과 PN접합을 형성하게 되어 소자의 동작시 졍션 캐패시턴스를 만들므로 소자의 동작 특성이 나빠진다.First, when the field oxide film is formed to be in contact with the isolation layer, boron ions implanted in the silicon layer accumulate on the lower portion of the field oxide film and on the isolation layer to increase the doping density, and the n-type source / drain region is formed later. And a PN junction to form a junction capacitance during operation of the device, resulting in poor operation characteristics of the device.

둘째, 필드산화막의 가장자리에 버즈빅(Bird's Beak)을 형성하게 되므로 소자의 활성영역이 감소된다.Second, since the bird's beak is formed at the edge of the field oxide film, the active area of the device is reduced.

셋째, 실리콘층을 지나서 격리층과 접촉할 때까지 산화공정을 하여 필드산화막을 형성하므로 필드산화막의 45%가 실리콘층의 표면 위로 올라오게 되므로 표면단차가 커지고 이에따라서 차후 공정을 하기가 어렵다.Third, since a field oxide film is formed by an oxidation process until it comes into contact with the isolation layer through the silicon layer, 45% of the field oxide film rises on the surface of the silicon layer, so that the surface step becomes large, and thus it is difficult to perform the subsequent process.

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 안정된 동작 특성을 나타낼 수 있는 반도체 소자의 격리영역 형성방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming an isolation region of a semiconductor device, which is designed to solve the above problems and can exhibit stable operating characteristics.

도 1a 내지 1e는 종래 반도체 소자의 격리영역 형성방법을 나타낸 공정단면도1A to 1E are cross-sectional views illustrating a method of forming an isolation region of a conventional semiconductor device.

도 2는 본 발명 반도체 소자의 격리영역을 나타낸 단면도2 is a cross-sectional view showing an isolation region of a semiconductor device of the present invention.

도 3a 내지 3f는 본 발명 반도체 소자의 격리영역 형성방법을 나타낸 공정단면도3A to 3F are cross-sectional views illustrating a method of forming an isolation region of a semiconductor device according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

21: 반도체 기판 22: 격리층21: semiconductor substrate 22: isolation layer

23: 실리콘층 24: 버퍼산화막23: silicon layer 24: buffer oxide film

25: 산화방지막 26: 감광막25: antioxidant film 26: photosensitive film

27: 필드산화막27: field oxide film

상기와 같은 목적을 달성하기 위한 본 발명 반도체 소자의 격리영역 형성방법은 제 1 도전형의 반도체 기판과 격리층과 반도체층이 차례로 적층된 SOI기판을 준비하는 단계, 상기 반도체층에 제 1 도전형 이온을 주입하는 단계, 상기 반도체층에 제 1 절연막과 제 2 절연막을 차례대로 증착하는 단계, 상기 제 1 절연막과 제 2 절연막과 반도체층을 식각하여 복수개의 미세패턴을 형성하는 단계, 상기 제 2 절연막을 마스크로 미세패터닝된 상기 반도체층의 측면을 일정비율로 산화시켜서 필드산화막을 형성하는 단계, 상기 제 2 절연막을 제거하는 단계, 상기 필드산화막을 습식각으로 완화시키는 단계를 포함하여 형성되는 것을 특징으로 한다.In order to achieve the above object, the method for forming an isolation region of a semiconductor device according to the present invention includes preparing a first conductive semiconductor substrate, an SOI substrate in which an isolation layer and a semiconductor layer are sequentially stacked, and forming a first conductivity type on the semiconductor layer. Implanting ions, depositing a first insulating film and a second insulating film sequentially on the semiconductor layer, etching the first insulating film, the second insulating film, and the semiconductor layer to form a plurality of fine patterns; Forming a field oxide film by oxidizing a side surface of the semiconductor layer finely patterned with an insulating film as a mask, removing the second insulating film, and relaxing the field oxide film by wet etching. It features.

첨부 도면을 참조하여 본 발명 반도체 소자의 격리영역 및 그의 형성방법을 설명하면 다음과 같다.An isolation region and a method of forming the semiconductor device of the present invention will be described with reference to the accompanying drawings.

도 2는 본 발명 반도체 소자의 격리영역을 나타낸 단면도이고, 도 3a 내지 3f는 본 발명 반도체 소자의 격리영역 형성방법을 나타낸 공정단면도이다.2 is a cross-sectional view illustrating an isolation region of the semiconductor device of the present invention, and FIGS. 3A to 3F are cross-sectional views illustrating a method of forming an isolation region of the semiconductor device of the present invention.

본 발명 반도체 소자의 격리영역은 도 2에 도시한 바와 같이 반도체 기판(21)과 격리층(22)과 실리콘층(23)이 차례대로 형성된 SOI(Silicon On Insulation)기판의 필드영역으로 정의된 실리콘층(23)에 격리층(22)과 접하고 일정한 폭으로 필드산화막(27)이 형성되어 있다.As shown in FIG. 2, the isolation region of the semiconductor device according to the present invention is silicon defined as a field region of a silicon on insulation (SOI) substrate in which a semiconductor substrate 21, an isolation layer 22, and a silicon layer 23 are sequentially formed. The field oxide film 27 is formed in the layer 23 in contact with the isolation layer 22 at a constant width.

상기와 같이 구성된 본 발명 반도체 소자의 격리영역 형성방법은 도 3a에 도시한 바와 같이 p형 반도체 기판(21)과 격리층(22)과 p형 실리콘층(23)이 차례로 적층된 SOI(Silicon On Insulation)기판을 형성한다.In the method of forming an isolation region of the semiconductor device according to the present invention configured as described above, as shown in FIG. 3A, a silicon on (SOI) layer in which a p-type semiconductor substrate 21, an isolation layer 22, and a p-type silicon layer 23 are sequentially stacked. Insulation) to form a substrate.

이후에 상기 실리콘층(23)내에 채널 스톱이온으로 p형의 보론(Boron) 이온을 주입한다.Thereafter, p-type boron ions are implanted into the silicon layer 23 as channel stop ions.

도 3b에 도시한 바와 같이 상기 실리콘층(23)상에 산화막과 질화막을 차례로 증착하여 버퍼산화막(24)과 산화방지막(25)을 형성한다.As shown in FIG. 3B, an oxide film and a nitride film are sequentially deposited on the silicon layer 23 to form a buffer oxide film 24 and an antioxidant film 25.

도 3c에 도시한 바와 같이 전면에 감광막(26)을 도포한 후 노광 및 현상공정으로 미세한 간격으로 복수개의 패턴을 갖도록 감광막(26)을 패터닝한다. 이때 패턴은 식각이 되는 부분인

Figure pat00001
는 45%로 그리고 식각이 되지 않는 부분인
Figure pat00002
는 55% 정도의 백분율을 갖도록 형성한다.As shown in FIG. 3C, the photosensitive film 26 is coated on the entire surface, and then the photosensitive film 26 is patterned to have a plurality of patterns at minute intervals in an exposure and development process. At this time, the pattern is an etching part
Figure pat00001
45% and the non-etched part
Figure pat00002
Form a percentage of about 55%.

도 3d에 도시한 바와 같이 패터닝된 감광막(26)을 마스크로 이용하여 상기 산화방지막(25)과 버퍼산화막(24)과 실리콘층(23)을 차례대로 이방성 식각한 후 감광막(26)을 제거한다.As shown in FIG. 3D, using the patterned photoresist layer 26 as a mask, the antioxidant layer 25, the buffer oxide layer 24, and the silicon layer 23 are sequentially anisotropically etched, and then the photoresist layer 26 is removed. .

이후에 열산화공정으로 상기 식각된 실리콘층(23)을 충분히 산화시켜서 필드산화막(27)을 형성한다. 이때 상기 도 3c에 도시한 바와 같이 식각되지 않고 남은 실리콘층(23)이 식각된 실리콘층(23)과 비교해서 55%정도이므로 이 비율만큼 실리콘층(23)의 측면을 산화시켜서 실리콘층(23)이 남지 않도록 한다. 이때 충분한 시간을 갖고 열공정하여 빈공간에 산화막이 다 채워지도록 균일하게 필드산화막(27)을 형성한다.Thereafter, the etched silicon layer 23 is sufficiently oxidized by a thermal oxidation process to form a field oxide film 27. At this time, since the remaining silicon layer 23, which is not etched, is about 55% as compared to the etched silicon layer 23, as shown in FIG. 3C, the side surface of the silicon layer 23 is oxidized by this ratio. ) Is not left. At this time, the field oxide film 27 is uniformly formed so that the oxide film is filled in the empty space by sufficient thermal processing.

도 3e에 도시한 바와 같이 상기 산화방지막(25)과 버퍼산화막(24)을 차례대로 제거한다.As shown in FIG. 3E, the antioxidant film 25 and the buffer oxide film 24 are sequentially removed.

도 3f에 도시한 바와 같이 실리콘층(23) 위로 부분적으로 돌출되어 형성된 필드산화막(27)을 습식각으로 제거하여 완화시킨다.As shown in FIG. 3F, the field oxide film 27 formed by partially protruding from the silicon layer 23 is removed by wet etching.

상기와 같은 본 발명 반도체 소자의 격리영역 형성방법은 다음과 같은 효과가 있다.The isolation region forming method of the semiconductor device of the present invention as described above has the following effects.

첫째, 실리콘층을 미세 패터닝한 후 실리콘층의 측면을 일정한 두께로 산화시켜 필드산화막을 형성하므로 가장자리에 버즈빅(Bird's Beak)이 형성되어 소자의 활성영역이 줄어드는 것을 방지할 수 있다.First, since the silicon oxide is finely patterned and the side surface of the silicon layer is oxidized to a certain thickness to form a field oxide film, a bird's beak is formed at the edge to prevent the active area of the device from being reduced.

둘째, 실리콘층을 미세 패터닝한 후 측면으로 산화가 일어나도록 하므로 활성영역과 필드산화막의 단차로 인하여 발생할 수 있는 차후공정 문제를 해결할 수 있고 공정시간도 단축할 수 있다.Second, since the silicon layer is finely patterned and then oxidized to the side, subsequent process problems that may occur due to the step difference between the active region and the field oxide film may be solved, and the process time may be shortened.

셋째, 실리콘층에 이온 주입된 보론이 누적되어 졍션 캐패시턴스를 만들어 소자의 동작 특성을 악화시키는 것을 막을 수 있으므로 제품의 동작 특성을 향상시킬 수 있다.Third, since the boron implanted in the silicon layer is accumulated to prevent the deterioration of the operating characteristics of the device by creating a cushion capacitance, it is possible to improve the operating characteristics of the product.

넷째, 실리콘층을 미세패터닝한 후 필드산화막을 형성하므로 보론의 농도를 균일하게 형성할 수 있다.Fourth, since the field oxide film is formed after the silicon layer is finely patterned, the concentration of boron can be uniformly formed.

Claims (5)

제 1 도전형의 반도체 기판과 격리층과 반도체층이 차례로 적층된 SOI 기판을 준비하는 단계,Preparing a SOI substrate in which a first conductive semiconductor substrate, an isolation layer, and a semiconductor layer are sequentially stacked; 상기 반도체층에 제 1 도전형 이온을 주입하는 단계,Implanting first conductivity type ions into the semiconductor layer, 상기 반도체층에 제 1 절연막과 제 2 절연막을 차례대로 증착하는 단계,Sequentially depositing a first insulating film and a second insulating film on the semiconductor layer; 상기 제 1 절연막과 제 2 절연막과 반도체층을 식각하여 복수개의 미세패턴을 형성하는 단계,Etching the first insulating film, the second insulating film, and the semiconductor layer to form a plurality of fine patterns; 상기 제 2 절연막을 마스크로 미세패터닝된 상기 반도체층의 측면을 일정비율로 산화시켜서 필드산화막을 형성하는 단계,Forming a field oxide film by oxidizing a side surface of the semiconductor layer finely patterned using the second insulating film as a mask at a predetermined ratio; 상기 제 2 절연막을 제거하는 단계,Removing the second insulating film, 상기 필드산화막을 습식각으로 완화시키는 단계를 포함함을 특징으로 하는 반도체소자의 격리영역 형성방법.And relaxing the field oxide layer by wet etching. 제 1 항에 있어서, 상기 제 1 절연막은 산화막을 증착하여 형성함을 특징으로 하는 반도체소자의 격리영역 형성방법.2. The method of claim 1, wherein the first insulating film is formed by depositing an oxide film. 제 1 항에 있어서, 상기 제 2 절연막은 질화막을 증착하여 형성함을 특징으로 하는 반도체소자의 격리영역 형성방법.2. The method of claim 1, wherein the second insulating film is formed by depositing a nitride film. 제 1 항에 있어서, 상기 반도체층을 미세패터닝할 때 식각되는 부분과 식각되지 않고 남는 부분의 백분율이 각각 45%와 55%가 되도록 하는 것을 특징으로 하는 반도체소자의 격리영역 형성방법.The method of claim 1, wherein the percentages of the portions to be etched and the portions not to be etched when the semiconductor layer is micropatterned are 45% and 55%, respectively. 제 1 항에 있어서, 상기 반도체층의 측면에 형성된 필드산화막은 식각되지 않고 남은 상기 반도체층(즉, 55%의 비율)이 모두 산화될 수 있도록 열공정하여 형성함을 특징으로 하는 반도체소자의 격리영역 형성방법.The isolation region of claim 1, wherein the field oxide layer formed on the side surface of the semiconductor layer is thermally formed so that the remaining semiconductor layer (that is, 55% of the ratio) is etched without being etched. Formation method.
KR1019970033162A 1997-07-16 1997-07-16 Method for forming isolation region of semiconductor device KR100261159B1 (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05114563A (en) * 1991-10-23 1993-05-07 Rohm Co Ltd Manufacture of soi structure

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05114563A (en) * 1991-10-23 1993-05-07 Rohm Co Ltd Manufacture of soi structure

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