KR100259587B1 - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A fabrication method of semiconductor devices having an SOI(silicon on insulator) structure is provided to easily control a floating body effect by selectively forming a silicide layer between an active region applied to a bias and an active region formed a transistor. CONSTITUTION: Polysilicon sidewalls(37) are formed at both sides of a first and a second active regions(33,33-1) defined by a field oxide(41), thereby connecting between the active regions(33,33-1) and a substrate. A gate line(43) is formed on the first active region(33). A silicide layer(39) is selectively formed between the first active region(33) used as transistor formation region and the second active region(33-1) used as a bias applying part. The silicide layer(39) is formed only on the surface of the substrate and the polysilicon sidewalls(37) for electrically connecting between the first and the second active regions(33,33-1).

Description

Manufacturing Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of controlling floating body effects in a semiconductor device having an SOI structure.

The silicon on insulator (SOI) structure is a structure in which a silicon single crystal thin film is formed on a buried insulating layer and a semiconductor device including a transistor is formed thereon. Since the SOI structure can realize a complete device isolation structure, high-speed operation is possible, and there is no active parasitic effect such as parasitic metal oxide semiconductor (MOS) transistor or parasitic bipolar transistor shown in PN junction isolation structure, so the latch up phenomenon However, there is an advantage that the circuit can be configured without a soft error phenomenon.

As a method of forming an SOI structure, a polycrystalline or amorphous silicon thin film is deposited on a silicon oxide, a buried insulating layer, and the single thin film is formed on a single crystal insulating layer such as sapphire, a deposited film recrystallization method in which the silicon thin film is melt recrystallized in a horizontal direction and grown in a solid phase. Epitaxial deposition for growing single crystals, and single crystal separation for embedding an insulating layer such as silicon oxide in a semiconductor substrate.

1 is a plan view of a semiconductor device having an SOI structure manufactured according to the prior art.

Referring to FIG. 1, which is a conventional semiconductor device, a gate line 19 is formed on an active layer 13 divided by a field oxide layer 17, and source / drain regions are formed on both side active layers 13 of the gate line 19. An impurity region used as a source / drain region is formed.

2A to 2D are cross-sectional process diagrams illustrating a method of manufacturing a semiconductor device according to the prior art in which the plan view of FIG. 1 is cut in the X-X 'direction.

Conventionally, as shown in FIG. 2A, the buried insulating layer 11 is formed on a conductive semiconductor substrate 11, for example, a p-type semiconductor substrate 11 by a conventional SOI formation method such as separation by implanted OXygen (SIMOX). 12) form. In the semiconductor substrate 11 separated from the buried insulating layer 12, the upper portion of the buried insulating layer 12 becomes the active layer 13. A buffer oxide film 14 and a nitride film 15 are sequentially formed on the active layer 13, and the nitride film 15, the buffer oxide film 15, the active layer 13, and the buried insulating layer 12 are sequentially formed. Patterning is performed to expose a predetermined portion of the semiconductor substrate 11.

Next, as shown in FIG. 2B, an oxide layer is deposited on the exposed semiconductor substrate 11 to cover the nitride layer 15 by chemical vapor deposition (hereinafter, referred to as CVD). Then, the oxide layer is chemical mechanical polishing (hereinafter referred to as CMP) to expose the nitride film 15. Thereafter, the nitride film 15 and the buffer oxide film 14 used as the mask are removed by a wet method to form a field oxide film 17 between the active layer 13 and the buried insulating layer 12.

2C, a gate oxide film 18 is formed on the active layer 13 isolated from the field oxide film 17 by thermal oxidation, and polysilicon doped with impurities on the gate oxide film 18. Depositing and patterning the polysilicon and gate oxide layer 18 to form a gate line 19.

Thereafter, using the gate line 19 as a mask, as shown in FIG. 2D, the active layer 13 on which the gate line 19 is formed is doped with impurities of a conductivity type different from that of the active layer 13. The impurity region 21 used as the drain region is formed.

As described above, a semiconductor device is manufactured by a method of isolating an active layer with a buried insulating layer and forming a transistor including an impurity region and a gate on the active layer.

However, in SOI devices, because the bottom of the channel body of the active layer is suspended by the BOX (Buried Oxide), in particular, holes generated by the alpha particles (α-particles) during operation of the device are accumulated in the body of the channel bottom. Indicates a floating body effect. This floating body effect causes a kink effect in the current / voltage curve, reducing the breakdown voltage of the device and causing an abnormal subthreshold slope. There is a problem of deterioration of device characteristics such as instability of operation, thereby lowering the reliability of the semiconductor device.

Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device having an SOI structure that can improve the reliability of the semiconductor device by controlling the floating body effect.

A semiconductor device manufacturing method according to the present invention for achieving the above object is to form a mask layer for exposing a predetermined portion on the first conductive type semiconductor substrate and the first conductive type active layer electrically separated by a buried insulating layer. And patterning the active layer and the buried insulating layer of the exposed portion because the mask layer is not formed to form first and second body contact holes for exposing a predetermined portion of the semiconductor substrate. Dividing into two active regions, forming first and second poly sidewalls having the same first conductivity type as the first and second active regions on side surfaces of the first and second body contact holes; Selectively forming a silicide layer on the surface of the semiconductor substrate and the first poly sidewall exposed through the first body contact, and filling the first and second body contact holes with an insulating material. Forming a region, removing the mask layer, and forming a gate through a predetermined portion of the first active region and a gate oxide layer on the field region; and forming a gate on both sides of the gate of the first active region. And selectively forming an impurity region of.

1 is a plan view of a semiconductor device manufactured according to the prior art.

2A to 2D are cross-sectional process diagrams illustrating a method of manufacturing a semiconductor device according to the prior art in which the plan view of FIG. 1 is cut in the X-X 'direction.

3 is a plan view of a semiconductor device manufactured in accordance with an embodiment of the present invention.

4A to 4E are cross-sectional process diagrams illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, in which the plan view of FIG. 3 is cut in the Y-Y 'direction.

<Brief description of symbols for the main parts of the drawings>

32: buried insulating layer 33: active layer

37 poly side wall 39 silicide layer

41: field oxide film

Hereinafter, with reference to the accompanying drawings will be described the present invention.

3 is a plan view of a semiconductor device having an SOI structure manufactured according to an embodiment of the present invention.

In the present method, as shown in FIG. 3, the poly sidewalls 37 are formed around the first and second active regions 33 and 33-1 separated by the field oxide layer 41 to form the first and second active layers. The gate lines 43 are formed on the first active region 33 and the first active region 33 in which the gate lines 43 are formed is connected to the regions 33 and 33-1 and the semiconductor substrate. Impurity regions used as source / drain regions are formed on both sides of the gate line 43. The second active region 33-1 in which the gate line 43 is not formed is connected to an external electrode so that holes or electrons accumulated in the body of the active layer in which the channel is formed can be extracted to the outside. Doped in the same conductivity type as the first and second active regions 33, and the poly-side wall 37 and the semiconductor between the first active region 33 and the second active region 33-1 biasing the outside The silicide layer 39 is selectively formed on the substrate surface.

4A through 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, in which the plan view of FIG. 3 is cut in the Y-Y 'direction.

This method forms a buried insulating layer 32 on a conductive semiconductor substrate 31, for example, a p-type semiconductor substrate 31, as shown in FIG. 4A by a conventional SOI forming method such as SIMOX. . In the semiconductor substrate 31 separated from the buried insulating layer 32, upper portions of the buried insulating layer 32 become first and second active regions 33 and 33-1. In addition, the buffer oxide film 34 and the nitride film 35 are sequentially formed on the first and second active regions 33 and 33-1, and the nitride film 35, the buffer oxide film 34, and the first and second films are sequentially formed. First and second body contacts 36 and 36-1 which sequentially pattern the second active regions 33 and 33-1 and the buried insulating layer 32 to expose a predetermined portion of the semiconductor substrate 31. ).

Then, polysilicon or amorphous silicon is deposited on the nitride film 35 to cover the surfaces of the first and second body contacts 36 and 36-1. Deposit. Tilt ion implantation of the polysilicon or amorphous silicon with the same conductivity type as the active layer 32 and annealing are performed to etch back the polysilicon doped with the impurity. First and second poly sidewalls 37 and 37-1 are formed on the side surfaces of the second body contacts 36 and 36-1 up to one third of the nitride film 35. Even when the first and second poly sidewalls 37 and 37-1 are formed using amorphous silicon, they are crystallized when ion implanted and annealed, and the first and second poly sidewalls 37 and 37-1 are crystallized. 1) connects the first and second active regions 33 and 33-1 to the semiconductor substrate 31.

As shown in FIG. 4C, a transition metal such as Ti, Ta, Co, Mo, or W is deposited by a sputtering method and heat-treated to cover the exposed semiconductor substrate 31 and the poly sidewall 37. Thus, the silicide layer 39 is formed on the exposed surfaces of the semiconductor substrate 31 and the poly sidewall 37 to remove unreacted transition metals. Thereafter, a portion of the silicide layer 39 that is not adjacent to the silicide layer 39 connecting the first active region 33 and the second active region 33-1 connected to the external electrode is selectively removed to be adjacent to the silicide layer 39. This prevents a short circuit with an active layer having another conductivity type.

Thereafter, as illustrated in FIG. 4D, an oxide material is deposited on the semiconductor substrate 31 to cover the nitride film 35 by CVD to form an oxide layer, and the oxide layer is CMP to expose the nitride film 35. . Thereafter, the nitride film 35 and the buffer oxide film 34 used as the masks are removed by a wet etching method to form a first body contact 36 having a silicide layer and a second body contact 36-1 having a poly sidewall. A field oxide film 41 is formed to fill the gap, and a gate line 43 having a gate oxide film 42 therebetween is formed in a predetermined portion on the first active region 33 isolated from the field oxide film 41.

Next, as shown in FIG. 4E, the gate line 43 is used as a mask, and a mask (not shown) is formed on the second active region 33-1 to form the first active line in which the gate line 43 is formed. An impurity region 45 used as a source / drain region is formed in only the region 33 by doping impurities having a different conductivity type from the first active region 33.

As described above, in the present invention, a poly-side wall connecting the active layer and the semiconductor substrate is formed, and a silicide layer is formed between the active region where a transistor is formed and the active region to apply an external bias to the poly side wall and the surface of the semiconductor substrate. Holes generated during operation of the active region to move the external bias through the channel portion where the impurity region is not formed, that is, in the longitudinal direction of the gate and apply the external bias through the p-type doped poly sidewall and silicide layer. Moved to. As described above, electrons accumulated in the active region under the channel of the pMOS can also be quickly moved to the active region to which an external bias is applied through the sidewall and the silicide layer.

Accordingly, the semiconductor device according to the present invention selectively forms a silicide layer between the active region to bias the outside and the active region where the transistor is formed to quickly discharge and float holes or electrons accumulated in the body at the bottom of the channel to the outside. There is an advantage to controlling the body effect.

Claims (3)

Forming a mask layer exposing a predetermined portion on an active layer of a first conductivity type electrically separated by a first conductive semiconductor substrate and a buried insulating layer, and the active layer and the buried portion of the exposed part because the mask layer is not formed Patterning the insulating layer to form first and second body contact holes for exposing predetermined portions of the semiconductor substrate, and separating the first and second active regions of a first conductivity type; Forming first and second poly sidewalls having the same first conductivity type as the first and second active regions on side surfaces of the first and second body contact holes; Selectively forming a silicide layer on a surface of the semiconductor substrate and the first poly sidewall exposed through the first body contact; Forming a field region by filling an insulating material in the first and second body contact holes, removing the mask layer, and forming a gate by interposing a gate oxide layer on a predetermined portion of the first active region and the field region; , And selectively forming an impurity region of a second conductivity type on both sides of the gate of the first active region. The method of manufacturing a semiconductor device according to claim 1, wherein the first and second poly sidewalls are formed by doping and annealing polysilicon and amorphous silicon with impurities. The method of manufacturing a semiconductor device according to claim 1, wherein the silicide layer is formed only on the poly sidewall and the surface of the semiconductor substrate connecting the first and second active regions.