KR100259343B1 - Method for manufacturing charge coupled device - Google Patents

Method for manufacturing charge coupled device Download PDF

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KR100259343B1
KR100259343B1 KR1019970045519A KR19970045519A KR100259343B1 KR 100259343 B1 KR100259343 B1 KR 100259343B1 KR 1019970045519 A KR1019970045519 A KR 1019970045519A KR 19970045519 A KR19970045519 A KR 19970045519A KR 100259343 B1 KR100259343 B1 KR 100259343B1
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region
main cell
electrostatic discharge
metal wiring
cell region
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KR1019970045519A
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Korean (ko)
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KR19990024422A (en
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최선
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/762—Charge transfer devices
    • H01L29/765—Charge-coupled devices
    • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
    • H01L29/76816—Output structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H01L27/14806—Structural or functional details thereof
    • H01L27/14812—Special geometry or disposition of pixel-elements, address lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/762—Charge transfer devices
    • H01L29/765—Charge-coupled devices
    • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
    • H01L29/76833—Buried channel CCD

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electromagnetism (AREA)
  • Ceramic Engineering (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE: A method for manufacturing a charge coupled device is provided to improve the characteristic of the charge coupled device by preventing a main cell area from electrically connecting to an electrostatic discharge protecting area. CONSTITUTION: A plurality of wells are formed by implanting p-type impurity ions into a substrate(1). A main cell area(2) and an electrostatic discharge protecting area(3) are formed by selectively implanting high density n-type or p-type impurity ions onto the well. After depositing an insulating layer(4), a contact hole is formed so as to expose the predetermined area. Then, a metal wiring(5) is formed. A P-SiO layer(8) is deposited on the insulating layer(4) which is formed with the metal wiring(5). After partially exposing the metal wiring by selectively etching the P-SiO layer(8), a pad(7) for applying an external signal is formed.

Description

고체촬상소자 제조방법Solid state imaging device manufacturing method

본 발명은 고체촬상소자 제조방법에 관한 것으로, 특히 금속배선공정 후 다층의 보호막증착시 발생하는 차지업(charge up)현상을 방지하는데 적당하도록 한 고체촬상소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a solid state image pickup device, and more particularly, to a method for manufacturing a solid state image pickup device suitable for preventing a charge up phenomenon occurring when a multilayer protective film is deposited after a metal wiring process.

일반적으로, 고체촬상소자는 기판에 광을 전기적인 신호로 변환하는 셀의 집합인 메인셀영역과, 정전기에 의한 소자의 보호를 위한 정전방전방지영역을 형성하고, 그 상부에 절연층을 증착한 후, 다시 메탈콘택 형성 및 금속배선을 형성하고, 다시 다층의 보호층을 증착하여 제조한다. 이러한 고체촬상소자는 다른 반도체 소자에 비해 공정진생시 발생되는 차지업의 방지가 곤란하다. 일반적인 반도체 소자에서는 보호층의 증착으로 각 영역에 원하지 않는 채널이 형성되는 차지업(charge up)현상을 통상 어닐링(annealing)을 통해 제거하게 되나, 고체촬상소자에서는 마이크로랜즈 공정에서 사용되는 재료가 150℃ 정도에서 녹거나 타버리기 때문에 어닐링공정의 사용이 불가능하여 차지업현상을 방지하는 다른 기술이 요구되고 있으며, 이와 같은 종래 고체촬상소자 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, a solid state image pickup device forms a main cell region, which is a set of cells that convert light into an electrical signal, and an electrostatic discharge prevention region for protecting the device by static electricity, and deposits an insulating layer thereon. After that, metal contact formation and metal wiring are formed again, and multilayer protective layers are deposited. Such a solid state image pickup device has difficulty in preventing charge-ups generated during process generation compared to other semiconductor devices. In general semiconductor devices, charge up phenomenon in which unwanted channels are formed in each region by deposition of a protective layer is usually removed by annealing, but in solid state imaging devices, materials used in the microlens process are 150 Since it melts or burns at about ℃, it is impossible to use the annealing process, and thus another technique for preventing the charge-up phenomenon is required. Referring to the accompanying drawings of the conventional solid-state imaging device, the following description will be given in detail.

도1은 종래 고체 촬상소자의 단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 피형 불순물이온을 주입하여 다수의 웰을 형성하고, 그 웰에 고농도 엔형 및 고농도 피형 불순물 이온을 선택적으로 이온주입하여 메인셀영역(2)과, 정전방전방지영역(3)을 형성하는 단계와; 상기 메인셀영역(2)과, 정전방전방지영역(3) 및 기판(1)의 상부에 절연막(4)을 증착한 후, 콘택홀을 형성하여 특정영역을 노출시킨 후, 금속공정을 통해 금속배선(5)을 형성하는 단계와; 상기 금속배선(5)이 형성된 메인셀영역(2), 정전방전방지영역(3) 및 기판(1)의 상부전면에 다층의 보호층(6)을 순차적으로 적층하는 단계와; 상기 보호층(6)의 일부를 선택적으로 식각하여 금속배선(5)의 일부를 노출시킨 후, 외부의 신호 인가를 위한 패드(7)를 형성하는 단계로 이루어 진다.1 is a cross-sectional view of a conventional solid-state image pickup device, as shown therein, in which a plurality of wells are formed by implanting an impurity ion into the upper portion of the substrate 1, and selectively ionizing high-energy and high-concentration impurity ions into the well. Implanting to form a main cell region (2) and an electrostatic discharge prevention region (3); After depositing an insulating film 4 on the main cell region 2, the electrostatic discharge prevention region 3 and the substrate 1, forming a contact hole to expose a specific region, and then metal Forming a wiring (5); Sequentially stacking a multi-layered protective layer (6) on the main cell region (2), the electrostatic discharge prevention region (3) and the upper surface of the substrate (1) on which the metal wiring (5) is formed; A portion of the protective layer 6 is selectively etched to expose a portion of the metallization 5, and then a pad 7 for external signal application is formed.

이하, 상기와 같은 종래 고체촬상소자 제조방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a conventional solid state image pickup device manufacturing method as described above will be described in detail with reference to the accompanying drawings.

먼저, 엔타입의 기판(1)에 피형 불순물을 선택적으로 주입하여 메인셀영역(2)과 정전방전방지영역(3)을 정의하고, 그 두 영역에 엔형 및 피형 불순물이온을 주입하여 금속전극과의 접촉저항을 감소시키거나, 외부의 입력신호에 비정상적으로 큰 신호가 입력되는 경우 소자를 보호하는 정전방전방지회로, 인가되는 광을 전기적인 신호로 출력하는 셀을 형성한다.First, the implanted impurities are selectively injected into the N-type substrate 1 to define the main cell region 2 and the electrostatic discharge prevention region 3, and the N-type and the implanted impurity ions are injected into the two regions so that the metal electrode and To reduce the contact resistance of the, or when an abnormally large signal is input to the external input signal to form an electrostatic discharge prevention circuit, a cell for outputting the applied light as an electrical signal.

그 다음, 상기 메인셀영역(2), 정전방전방지영역(3)과 기판(1)의 상부에 절연막(4)을 증착한다. 이때의 절연막(4)은 보통 산화막, 고온저압산화막(HLD), 붕소 인 실리콘 글라스(BPSG)를 합하여 사용한다.Next, an insulating film 4 is deposited on the main cell region 2, the electrostatic discharge prevention region 3, and the substrate 1. In this case, the insulating film 4 is usually used in combination with an oxide film, a high temperature low pressure oxide film (HLD), and boron silicon glass (BPSG).

그 다음, 상기 절연막(4)의 일부를 선택적으로 식각하여 상기 메인셀영역(2)과 정전방전방지영역(3)에 특정 이온이 주입된 영역을 노출시킨다.Next, a portion of the insulating film 4 is selectively etched to expose a region where specific ions are implanted in the main cell region 2 and the electrostatic discharge prevention region 3.

그 다음, 상기 절연막(4)의 상부에 금속을 증착하고, 선택적으로 식각하여 상기 노출된 영역에 접속되는 금속배선(5)을 형성한다.Next, a metal is deposited on the insulating film 4 and selectively etched to form a metal interconnect 5 connected to the exposed region.

그 다음, 상기 금속배선(5)이 형성된 절연막(4)의 상부에 다층의 보호층(6)을 증착하고, 도2에 도시된 마스크 패턴을 사용하여 그 보호층(6)을 선택적으로 식각하여 외부의 신호가 인가될 금속배선을 선택적으로 노출시키고, 그 상부에 금속을 증착하여 외부신호가 인가되는 패드(7)를 형성한다.Next, a multilayer protective layer 6 is deposited on the insulating film 4 on which the metal wiring 5 is formed, and the protective layer 6 is selectively etched using the mask pattern shown in FIG. The metal wiring to which an external signal is to be applied is selectively exposed, and the metal is deposited on the upper portion to form a pad 7 to which an external signal is applied.

이때, 상기와 같은 공정의 진행으로 발생된 음전하 차지업으로 인해 메인셀영역(2)과 정전방전방지영역(3) 사이의 기판(1) 표면하부에 피형 이온이 모이게 되어, 인버전(INVERSION)된 피채널이 형성된다. 이와 같이 차지업으로 인해 각 영역간에 채널이 형성되면 소자의 특성이 나빠지게 된다.At this time, due to the negative charge charge generated by the process as described above, the collected ions are collected under the surface of the substrate 1 between the main cell region 2 and the electrostatic discharge prevention region 3, and thus the inversion Formed channels are formed. As a result, when the channel is formed between the regions due to the charge up, the device characteristics deteriorate.

상기한 바와 같이 종래 고체촬상소자 제조방법은 보호층을 메인셀영역과 정전방전방지영역의 상부전면에 증착하고, 특정 영역에 콘택을 형성한 후, 패드를 형성함으로써, 차지업에 의해 메인셀영역과 정전방전방지영역의 사이에 채널이 형성되어 고체촬상소자의 특성이 열화되는 문제점이 있었다.As described above, in the conventional solid state image pickup device manufacturing method, the protective layer is deposited on the upper surface of the main cell region and the electrostatic discharge prevention region, the contact is formed in a specific region, and the pad is formed to form the main cell region by charging up. There is a problem in that a channel is formed between the antistatic discharge region and the characteristics of the solid state image pickup device.

이와 같은 문제점을 감안한 본 발명은 차지업이 발생하여도 각 메인셀영역과 정전방전방지회로간에 채널형성을 방지하는 고체촬상소자 제조방법을 제공함에 그 목적이 있다.It is an object of the present invention to provide a solid state imaging device manufacturing method for preventing channel formation between each main cell region and an electrostatic discharge prevention circuit even when a charge up occurs.

도1은 종래 고체촬상소자의 단면도.1 is a cross-sectional view of a conventional solid state image pickup device.

도2는 도1에 있어서, 다층구조의 보호층 식각시 사용되는 마스크의 평면도.2 is a plan view of a mask used in etching a protective layer of a multilayer structure in FIG.

도3은 본 발명 고체촬상소자의 단면도.3 is a cross-sectional view of the solid-state imaging device of the present invention.

도4는 도3에 있어서, 다층구조의 보호층 식각시 사용되는 마스크의 평면도.4 is a plan view of a mask used in etching a protective layer of a multilayer structure in FIG.

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

1:기판 2:메인셀영역1: Substrate 2: Main cell area

3:정전방전방지영역 4:절연막3: electrostatic discharge prevention area 4: insulating film

5:금속배선 6:보호층5: metal wiring 6: protective layer

7:패드 8:P-SiO층7: Pad 8: P-SiO layer

상기한 바와 같은 목적은 다층의 보호층의 증착전에 P-SiO층을 증착하고, 다층의 보호층을 메인셀영역에만 선택적으로 증착한 다음, 상기 P-SiO층에 콘택홀을 형성한 후, 패드를 형성하여 보호층에 공정진행시 발생되는 차지업현상에 의해 메인셀영역과 정전방전방지영역의 사이 기판에 채널이 형성되는 것을 원천적으로 방지함으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is to deposit a P-SiO layer before the deposition of the multilayer protective layer, selectively deposit the multilayer protective layer only in the main cell region, and then form a contact hole in the P-SiO layer, and then pad Is achieved by fundamentally preventing the channel from being formed in the substrate between the main cell region and the electrostatic discharge prevention region due to the charge-up phenomenon generated during the process in the protective layer. Detailed description with reference to the following.

도3은 본 발명 고체촬상소자의 단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 피형 불순물이온을 주입하여 다수의 웰을 형성하고, 그 웰에 고농도 엔형 및 고농도 피형 불순물 이온을 선택적으로 이온주입하여 메인셀영역(2)과, 정전방전방지영역(3)을 형성하는 단계와; 상기 메인셀영역(2)과, 정전방전방지영역(3) 및 기판(1)의 상부에 절연막(4)을 증착한 후, 콘택홀을 형성하여 특정영역을 노출시킨 후, 금속공정을 통해 금속배선(5)을 형성하는 단계와; 상기 금속배선(5)이 형성된 절연막(4)의 상부에 P-SiO층(8)을 증착하는 단계와; 메인셀영역(2)의 상부에 증착한 P-SiO층(8)의 상부에 다층의 보호층(6)을 순차적으로 적층하는 단계와; 상기 P-SiO층(8)의 일부를 선택적으로 식각하여 금속배선(5)의 일부를 노출시킨 후, 외부의 신호 인가를 위한 패드(7)를 형성하는 단계로 이루어진다.3 is a cross-sectional view of the solid-state image pickup device of the present invention, as shown therein, in which a plurality of wells are implanted by implanting impurity ions into an upper portion of the substrate 1, and high concentrations of Y-type and high concentrations of impurity ions are selectively formed in the wells. Ion implantation to form a main cell region (2) and an electrostatic discharge prevention region (3); After depositing an insulating film 4 on the main cell region 2, the electrostatic discharge prevention region 3 and the substrate 1, forming a contact hole to expose a specific region, and then metal Forming a wiring (5); Depositing a P-SiO layer (8) on top of the insulating film (4) on which the metal wiring (5) is formed; Sequentially stacking a multi-layered protective layer 6 on the P-SiO layer 8 deposited on the main cell region 2; A portion of the P-SiO layer 8 is selectively etched to expose a portion of the metallization 5, and then a pad 7 for external signal application is formed.

이하, 상기와 같은 종래 고체촬상소자 제조방법을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, a conventional solid state image pickup device manufacturing method as described above will be described in detail with reference to the accompanying drawings.

먼저, 엔타입의 기판(1)에 피형 불순물을 선택적으로 주입하여 메인셀영역(2)과 정전방전방지영역(3)을 형성하고, 상기 메인셀영역(2)과 정전방전방지영역(3)에 엔형 및 피형 불순물이온을 주입하여 금속전극과의 접촉저항을 감소시키거나, 외부의 입력신호에 비정상적으로 큰 신호가 입력되는 경우 소자를 보호하는 정전방전방지회로, 인가되는 광을 전기적인 신호로 출력하는 셀을 형성한다.First, the implanted impurities are selectively injected into the N-type substrate 1 to form a main cell region 2 and an electrostatic discharge preventing region 3, and the main cell region 2 and an electrostatic discharge preventing region 3. An electrostatic discharge prevention circuit that protects the device when an abnormally large signal is input to an external input signal or reduces contact resistance with a metal electrode by injecting N-type and impurity ions into the external electrode. Form an output cell.

그 다음, 상기 메인셀영역(2), 정전방전방지영역(3)과 기판(1)의 상부에 절연막(4)을 증착한다.Next, an insulating film 4 is deposited on the main cell region 2, the electrostatic discharge prevention region 3, and the substrate 1.

그 다음, 상기 절연막(4)에 콘택홀을 형성하여 상기 메인셀영역(2)과 정전방전방지영역(3)에 특정 이온이 주입된 영역을 노출시킨다.Next, a contact hole is formed in the insulating film 4 to expose a region where specific ions are injected into the main cell region 2 and the electrostatic discharge prevention region 3.

그 다음, 상기 절연막(4)의 상부에 금속을 증착하고, 선택적으로 식각하여 상기 노출된 영역에 접속되는 금속배선(5)을 형성한다.Next, a metal is deposited on the insulating film 4 and selectively etched to form a metal interconnect 5 connected to the exposed region.

그 다음, 상기 금속배선(5)이 형성된 절연막(4)의 상부에 P-SiO층(8)을 형성한다. 이와 같은 P-SiO층(8)은 공정의 진행시 차지업현상에 의해 음전하로 대전되어도, 패드의 형성 후, 디스차지 시킬 수 있어, 차지업현상에 의한 영향을 제거할 수 있다.Next, a P-SiO layer 8 is formed on the insulating film 4 on which the metal wiring 5 is formed. Such a P-SiO layer 8 can be discharged after the pad is formed even if it is negatively charged due to the charge up phenomenon at the time of the process, so that the influence of the charge up phenomenon can be eliminated.

그 다음, 상기 P-SiO층(8)의 상부에 다층의 보호층(6)을 증착하고, 도4에 도시한 마스크를 사용하여 상기 메인셀영역(2)의 상부에 위치하는 다층의 보호층(6)만을 남겨두고 모두 식각한다.Next, a multilayer protective layer 6 is deposited on top of the P-SiO layer 8, and the multilayer protective layer is positioned on the main cell region 2 using a mask shown in FIG. Etch everything except for (6).

그 다음, 상기 다층의 보호층(6)의 식각으로 노출된 P-SiO층(8)에 선택적으로 콘택홀을 형성하여 금속배선(5)의 일부를 노출시키고, 그 노출된 금속배선(5)의 상부에 금속을 증착하여 패드(7)를 형성한다.Then, a contact hole is selectively formed in the P-SiO layer 8 exposed by etching of the multilayer protective layer 6 to expose a part of the metal wiring 5, and the exposed metal wiring 5 is exposed. The pad 7 is formed by depositing a metal on the top.

상기한 바와 같이 본 발명 고체촬상소자 제조방법은 금속배선과 패드의 절연을 위한 층으로 P-SiO층을 사용하고, 다층구조의 보호층을 메인셀영역의 상부에만 선택적으로 형성함으로써, 차지업현상에 의해 메인셀영역과 정전방전방지영역이 채널에 의해 전기적으로 접속되는 것을 방지하여 고체촬상소자의 특성을 향상시키는 효과가 있다.As described above, the method of manufacturing a solid-state image pickup device according to the present invention uses a P-SiO layer as a layer for insulating the metal wiring and the pad, and selectively forms a protective layer having a multi-layer structure only on the upper part of the main cell region, thereby causing charge up phenomenon. This prevents the main cell region and the electrostatic discharge prevention region from being electrically connected by the channel, thereby improving the characteristics of the solid state image pickup device.

Claims (1)

기판(1)의 상부에 피형 불순물이온을 주입하여 다수의 웰을 형성하고, 그 웰에 고농도 엔형 및 고농도 피형 불순물 이온을 선택적으로 이온주입하여 메인셀영역(2)과, 정전방전방지영역(3)을 형성하는 단계와; 상기 메인셀영역(2)과, 정전방전방지영역(3) 및 기판(1)의 상부에 절연막(4)을 증착한 후, 콘택홀을 형성하여 특정영역을 노출시킨 후, 금속공정을 통해 금속배선(5)을 형성하는 단계와; 상기 금속배선(5)이 형성된 절연막(4)의 상부에 P-SiO층(8)을 증착하는 단계와; 메인셀영역(2)의 상부에 증착한 P-SiO층(8)의 상부에 다층의 보호층(6)을 형성하는 단계와; 상기 P-SiO층(8)의 일부를 선택적으로 식각하여 금속배선(5)의 일부를 노출시킨 후, 외부의 신호 인가를 위한 패드(7)를 형성하는 단계로 이루어진 것을 특징으로 하는 고체촬상소자 제조방법.A plurality of wells are formed by implanting the impurity ions into the upper part of the substrate 1, and ion implantation of high concentrations of Y-type and high concentrations of impurity ions into the wells is performed to selectively form the main cell region 2 and the electrostatic discharge prevention region 3 Forming a); After depositing an insulating film 4 on the main cell region 2, the electrostatic discharge prevention region 3 and the substrate 1, forming a contact hole to expose a specific region, and then metal Forming a wiring (5); Depositing a P-SiO layer (8) on top of the insulating film (4) on which the metal wiring (5) is formed; Forming a multilayer protective layer (6) on top of the P-SiO layer (8) deposited on the main cell region (2); Selectively etching a part of the P-SiO layer 8 to expose a part of the metal wiring 5, and then forming a pad 7 for applying an external signal. Manufacturing method.
KR1019970045519A 1997-09-02 1997-09-02 Method for manufacturing charge coupled device KR100259343B1 (en)

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