KR100259137B1 - Device for detecting and verifying polarity using comparator in vsb receiver - Google Patents

Abstract

PURPOSE: An apparatus for detecting/verifying a polarity in a vertical sideband receiver is provided to add a comparator to detect the polarity by using the comparator, so as to reduce a stabilization delay time caused by a wrong operation in a segment synchronous signal detecting process and to decrease wrong operations of a synchronous signal detection and a symbol timing restoration/DC remover. CONSTITUTION: A tuner(1) converts an RF signal into an IF signal. A SAW(Surface Acoustic Wave) filter(2) band pass-filters the IF signal. The first IF demodulator(3) demodulates the IF signal. An AFC(Automatic Frequency Control) filter(4) inputs an MXO+ signal and an MXO- signal in an initial mode, and filters the signals. A comparator(5) inputs the MXO+ signal and the MXO- signal in an initial mode to compare the signals, and outputs a polarity signal. The first segment synchronization detector/timing restorer(6) detects a polarity and restores the polarity to a normal polarity. An A/D(Analog to Digital) converter(7) converts analog data into digital data. A micro processor(8) monitors a system initialization and a system state.

Description

Polarity detection / verification device using comparator in residual sideband receiver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polarity detection / verification device using a comparator in a residual sideband receiver, and more particularly, by attaching a comparator and detecting polarity using a comparator, resulting in malfunction in detecting a segment sync signal. The present invention relates to a polarity detection / verification device using a comparator in a VSB receiver that can reduce the settling delay time.

As can be seen, the residual sideband receiver is used to receive the residual sideband data streams transmitted using terrestrial and cable modes, and is capable of receiving 16 and 8 residual sideband signals with a symbol rate of 10.76 MHz. Used to demodulate.

On the other hand, in the conventional residual sideband receiving apparatus, as shown in FIG. 1, a radio frequency signal (hereinafter referred to as RF) received through an antenna is referred to as an intermediate frequency (hereinafter referred to as IF). A tuner 1 for converting the signal into a signal and outputting the signal; A surface acoustic wave (SAW) filter connected to the signal output terminal of the tuner 1 for band-pass filtering the IF signal; It is connected to the signal output terminal of the SAW filter 2, demodulates the IF signal output from the SAW filter 2 to output analog baseband symbol data and outputs an automatic gain control signal. A second IF demodulator 18 for outputting Gain Control (hereinafter referred to as AGC) to the tutor (1); An analog / digital signal connected to the signal output terminal of the second IF demodulator 18 to convert analog baseband symbol data output from the second IF demodulator 18 into digital data and output the digital data; Hereinafter referred to as A / D; It is connected to the signal output terminal of the A / D converter 6 to detect input digital data for 8 segments, and if the phase continues to come into a constant state, the polarity is detected to detect the detected polarity A and B signals. 2 outputs to IF demodulator 18, when polarity is reversed, restores polarity and obtains GUP (Gain UP) signal for gain control, GDN (Gain DN; hereafter referred to as GDN) signal. Is connected to the signal input terminal of the second segment synchronous detection and timing recovery device 19 for outputting the second IF demodulator 18 to the second IF demodulator 18 and during the initialization mode. And a microprocessor (8) for outputting an automatic frequency control_SW (hereinafter referred to as AFC_SW) signal to the recovery device 19 and for monitoring system initialization and system status.

Referring to the operation process of the conventional residual sideband receiving device, first, during the initialization mode, the microprocessor 8 performs a system initialization operation, the second IF demodulator 18 and the second segment synchronous detection and The timing recovery device 19 outputs an AFC_SW signal.

In addition, when the RF signal is received through the antenna, the tuner 1 converts the RF signal into an IF signal and outputs it, and the SAW filter 2 performs band pass filtering on the IF signal output from the tuner 1. Output to the second IF demodulator 18.

The second IF demodulator 18 demodulates the IF signal output from the SAW filter 2 to output analog baseband symbol data to the A / D converter 6, and the A / D converter 6 Convert analog signals to digital data.

On the other hand, the second segment synchronous detection and timing recovery apparatus 19 detects the input digital data for eight segments, detects the polarity if the phase continues to be constant, and detects the detected polarity A and B signals. 2 It locks the phase by outputting to IF demodulator 18. If the polarity is reversed, the polarity is restored and output.

In addition, the second segment synchronous detection and timing recovery device 19 outputs GUP and GDN signals to the second IF demodulator 18 to adjust gain, and the second IF demodulator 18 adjusts the tuner 1. To adjust the gain by outputting the AGC signal.

However, the conventional residual sideband receiver as described above detects the polarity in the second segment synchronization detection and timing recovery apparatus, and thus detects the polarity resulting from performing other operations of the second segment synchronization detection and timing recovery apparatus. There was a problem in that malfunctions occur frequently and a large delay time is detected.

An object of the present invention is to solve the above-mentioned conventional problems, and in particular, by attaching a comparator and detecting a polar line using a comparator, the stabilization delay time due to a malfunction in detecting the segment synchronization signal is reduced. Rather, the present invention provides a polarity detection / verification apparatus using a comparator in a residual sideband receiver that can reduce synchronization signal detection, symbol timing recovery, and DC malfunction.

In order to achieve the above object, a polarity detection / verification apparatus using a comparator in a residual sideband receiver of the present invention includes: a tuner for converting and outputting an RF signal received through an antenna into an IF signal; A SAW filter connected to the signal output terminal of the tuner and band pass filtering the IF signal; Connected to the signal output terminal of the SAW filter, demodulates the IF signal output from the SAW filter to output analog baseband symbol data, outputs an AGC signal to the tuner, and, in the initialization mode, MXO + for polarity detection; A first IF demodulator for outputting an MXO- signal; Connected to the signal output terminal of the first IF demodulator and, when in the initialization mode, inputs and filters the MXO + and MXO- signals output from the first IF demodulator, and filters the AFC + and AFC- signals when the signal is not in the initialization mode. An AFC filter; Connected to the signal output terminal of the first IF demodulator, in the initialization mode, after comparing the MXO + and MXO- signals output from the first IF demodulator, and outputting a polarity signal. A comparator for comparing the AFC- signal and outputting a polarity signal; Connected to the signal output terminal of the A / D converter and the comparator, inputs the polarity signal output from the comparator, detects the polarity, and if the polarity is inverted, restores the polarity to the normal state to detect the segment synchronization signal; A first segment synchronization outputting polarity A and B signals detected by the first IF demodulator for phase locking of a first IF demodulator and outputting GUP and GDN signals for gain control to the first IF demodulator A detection and timing recovery device; An A / D converter connected to the signal output terminal of the first IF demodulator and converting analog baseband symbol data output from the first IF demodulator into digital data and outputting the digital data; Is connected to the signal input of the tuner, the first IF demodulator and the first segment synchronous detection and timing recovery device, and outputs an AFC_SW signal to the first IF demodulator and the first segment synchronous detection and timing recovery device during an initialization mode; It includes a microprocessor for monitoring initialization and system status.

On the other hand, the first segment synchronous detection and timing recovery apparatus includes: a polarity detection device connected to a signal output terminal of the comparator, inputting a polarity signal output from the comparator, and detecting a polarity; And a polarity verifying device for restoring the polarity when the polarity is inverted due to noise or impact when connected to the signal output terminal of the A / D converter.

The polarity detecting device may further include: a sampling unit connected to a signal output terminal of the comparator and sampling the polarity signal output from the comparator in units of segments; And a first polarity detector connected to the signal output terminal of the sampling unit to detect the polarity through the sampled polarity signal and output a polarity detection signal (Polarity Detected).

On the other hand, the polarity verification device, the DC output unit connected to the signal output terminal of the A / D converter, to remove the residual DC component; A correlator connected to the signal output terminal of the DC eliminator to determine whether the phase is a normal phase or an inverted phase in a segment synchronization period; A second polarity detector connected to the signal output of the correlator to restore polarity to detect normal polarity; An EX-OR unit connected to signal output terminals of the first and second polarity detectors to perform an exclusive OR operation (hereinafter referred to as EX-OR); And a buffer connected to the signal output terminal of the first polarity detector and the EX-OR unit, for buffering.

The polarity detection / verification apparatus using the comparator in the residual sideband receiver of the present invention is equipped with a comparator and detects the polarity using the comparator, thereby reducing the stabilization delay time due to a malfunction in detecting the segment synchronization signal. It has the effect of reducing the synchronization signal detection, symbol timing recovery, and DC canceller malfunction.

1 is a block diagram showing the configuration of a conventional residual side band receiving apparatus;

2 is a block diagram showing the configuration of a residual side band receiving apparatus according to an embodiment of the present invention;

3 is a block diagram showing the configuration of a segment synchronization detection and timing recovery apparatus in FIG.

4 is a view showing a polarity detection device,

5 is a view showing a polarity verification device,

6 shows signal waveforms for explaining the operation of the present invention;

* Explanation of symbols for main parts of the drawings

1: tuner 2: SAW filter

3: first IF demodulator 4: AFC filter

5: comparator 6: first segment synchronization detection and timing recovery apparatus

7: A / D converter 8: Microprocessor

9: polarity detection device 10: polarity verification device

11 sampling unit 12 first polarity detector

13: DC Eliminator 14: Correlator

15: second polarity detector 16: EX-OR section

17: buffer

Hereinafter, with reference to the accompanying drawings, the configuration and operation of the embodiment according to the technical idea of the polarity detection / verification device using a comparator in the residual sideband receiver of the present invention in detail as follows.

EXAMPLE

2, 3, 4, and 5, first, the signal output terminal of the tuner 1 is connected to the signal input terminal of the SAW filter 2, and then the SAW filter 2 is connected. And a signal output terminal of the first segment synchronous detection and timing recovery device 6 and a microprocessor 8 to a signal input terminal of the first IF demodulator 3 and a signal input terminal of the first IF demodulator 3. The signal output terminal of the comparator 5, the AFC filter 4, and the A / D converter 7, and the signal output terminal of the comparator 5 to the signal of the first segment Is connected to an input terminal, and the signal output terminal of the AFC filter 4 is connected to the signal output terminal of the first segment synchronous detection and timing recovery device 6, and the signal input / output terminal of the A / D converter 7 is A signal input / output terminal of the first segment synchronous detection and timing recovery device 6 is connected.

The signal output terminal of the comparator 5 is connected to the signal input terminal of the sampling unit 11 in the first segment synchronous detection and timing recovery device 6, and the signal output terminal of the sampling unit 11 is connected to the first polarity. A signal output terminal of the A / D converter 7 to a signal input terminal of the DC remover 13, and a signal output terminal of the DC remover 13 to the signal input terminal of the detector 12; The signal output terminal of the correlator 14 is connected to the signal input terminal of the second polarity detector 15, and the signal of the first polarity detector 12 and the second polarity detector 15 An output terminal is connected to a signal input terminal of the EX-OR unit 16, a signal output terminal of the first polarity detector 12 and the EX-OR unit 16 is connected to a signal input terminal of the buffer 17, and This embodiment by connecting the signal output terminal of the buffer 17 to the first IF demodulator 3 Constructs.

An operation process of the polarity detection / verification apparatus using the comparator in the residual sideband receiver configured as described above will be described with reference to FIG. 6.

First, during the initialization mode, the tuner 1 tunes the received RF signal and converts it into an IF signal, and the SAW filter 2 filters the IF signal and outputs it to the first IF demodulator 3. The first IF demodulator 3 outputs the MXO + and MXO− output signals with carrier recovery to the AFC filter 4 and the comparator 3.

The phase error of the IF signal is uncertain in phase as 0 ° or 180 °. Therefore, a voltage difference is generated between the AFC + signal and the AFC- signal filtered through the AFC filter 4 as shown in FIG. 6A. Since the AFC filter is in an unstable state because it is in the initialization mode for the previous 50ms, when the initialization mode ends, the asynchronous gain control mode starts with a voltage difference.

When the asynchronous gain control mode starts above, during the asynchronous gain control mode, the operation of the frequency-phase locked loop (hereinafter referred to as FPLL) in the first IF demodulator 3 is stable, as shown in FIG. 6A. A potential difference of about 40 to 50 mV is generated, and information on the polarity is obtained using this voltage difference.

That is, if the phase error is fixed at 0 °, the AFC + signal has a higher voltage than the AFC- signal, conversely, the phase error is fixed at 180 °, and the AFC + signal has a lower voltage than AFC-.

The comparator 5 compares the AFC + signal and the AFC- signal output from the AFC filter 4, and outputs a normal polarity signal (LOW signal) as shown in FIG. 6B when the AFC + signal has a higher voltage than the AFC- signal. When the AFC_SW signal output from the microprocessor 8 becomes low, the polarity signal is output using the voltage difference between the AFC + and AFC- signals applied to the comparator 5.

That is, as shown in FIG. 6A, when the initialization mode ends, the AFC + signal and the AFC- signal show the voltage difference as shown in FIG. 6A, and the comparator 5 outputs the polarity signal information using this potential difference as an input.

6B shows a state in which the FPLL of the first IF demodulator 3 is fixed to the correct polarity (0 °), and FIG. 6C shows a polarity (180 °) in which the FPLL of the first demodulator 3 is inverted. It shows the state fixed to).

On the other hand, the polarity signal output from the comparator 5 is input from the sampling unit 11 mounted in the polarity detecting device 9 to sample in segments, and the first polarity detector 12 is continuously If the 8th polarity information is the same, the polarity_D signal indicating that the polarity is found and the sign signal which determines that the polarity of which the output of the comparator 5 is locked in the FPLL are output to the EX-OR unit 16. .

After the polarity detection operation is completed, the polarity A and B signals are applied to the first IF demodulator 3 according to the direction of the detected polarity out of the high impedance state to help the polarity maintained in the FPLL not to be changed. After the instantaneous detection operation, the instantaneous A and B signals are applied to the AFC + signal and the AFC- signal by the first segment synchronous detection and timing recovery device 6 to push in different directions as shown in FIG. 6A.

That is, after the polar island detection operation, the potential difference between the AFC + signal and the AFC- signal is greatly different by pushing the first IF demodulator 3 so that the polarity of the first IF demodulator 3 does not change according to the detected polarity.

Further, after the polarity detection operation, the output data of the A / D converter 7 is brought into the correct phase, and then the first segment synchronous detection and timing recovery device 6 is operated.

On the other hand, the polarity verification device 10 operates like a gain control circuit, and if the data is correctly restored by the polarity detection device 9, the first segment is the data recovered by the polarity detection device 9. The synchronization detection and timing recovery device 6 searches for a segment synchronization signal, and after searching for the synchronization signal, the segment synchronization signal becomes high for one symbol in every segment where the synchronization signal exists.

The output of the segment sync correlation value is latched using the high signal, and the sync gain adjusting circuit uses the magnitude of the latched value, and the polarity verifying apparatus 10 uses the sign of this value.

In addition, the A / D converter 7 inputs analog baseband symbol data output from the first IF demodulator 3 to convert the digital data into digital data, and the DC eliminator 13 converts the A / D converter 7 into a digital signal. Remove residual data of digital data printed in).

On the other hand, when the polarity of the data changes due to a sudden channel change during system operation, the segment synchronization correlation value may be negative. In this case, the second polarity detector 15 has 8 segments of the polarity of the correlation value. If the signal is output with negative polarity continuously, the signal is determined to be inverted and the polarity is reversed.

The polarity verifying apparatus 10 is not necessary when the channel is stable or when the operation of the first IF demodulator 3 is stable. However, when the channel is unstable and the polarity is inverted, the segment correlation value is incorrectly accumulated to generate a synchronization signal. You need it because you can lose it.

In addition, when the first IF demodulator 3 is not stable, since the polarity information found by the polarity detector 9 is not reliable, the role of the polarity verification device 10 becomes important.

The normal polarity A signal output from the buffer 17 is shown in FIG. 6D, and the inverted polarity A signal is shown in FIG. 6E.

As described above, the polarity detection / verification apparatus using the comparator in the residual sideband receiver of the present invention is particularly equipped with a comparator, and detects the polarity using the comparator, thereby stabilizing the delay caused by a malfunction in detecting the segment synchronization signal. Not only does it save time, but it also reduces sync signal detection, symbol timing recovery, and DC rejector malfunction.

Claims (4)

A tuner for converting an RF signal received through an antenna into an IF signal and outputting the IF signal; A SAW filter connected to the signal output terminal of the tuner and band pass filtering the IF signal; Connected to the signal output terminal of the SAW filter, demodulates the IF signal output from the SAW filter to output analog baseband symbol data, outputs an AGC signal to the tuner, and, in the initialization mode, MXO + for polarity detection. A first IF demodulator for outputting an MXO- signal; Connected to the signal output terminal of the first IF demodulator and, when in the initialization mode, inputs and filters the MXO + and MXO- signals output from the first IF demodulator, and filters the AFC + and AFC- signals when the signal is not in the initialization mode. An AFC filter; Connected to the signal output terminal of the first IF demodulator, in the initialization mode, after comparing the MXO + and MXO- signals output from the first IF demodulator, and outputting a polarity signal. A comparator for comparing the AFC- signal and outputting a polarity signal; Connected to the signal output terminal of the A / D converter and the comparator, inputs the polarity signal output from the comparator, detects the polarity, and if the polarity is inverted, restores the polarity to the normal state to detect the segment synchronization signal; First segment synchronization detection and timing for outputting polarity A and B signals detected by the first IF demodulator for outputting a phase of a first IF demodulator, and outputting a GUP and GDN signal for gain control to the first IF demodulator. A restoring device; An A / D converter connected to a signal output terminal of the first IF demodulator and converting analog baseband symbol data output from the first IF demodulator into digital data and outputting the digital data; Is connected to the signal input of the tuner, the first IF demodulator and the first segment synchronous detection and timing recovery device, and outputs an AFC_SW signal to the first IF demodulator and the first segment synchronous detection and timing recovery device during an initialization mode; A polarity detection / verification device using a comparator in a residual sideband receiver comprising a microprocessor for monitoring initialization and system status. 2. The apparatus of claim 1, wherein the first segment synchronous detection and timing recovery device comprises: a polarity detection device connected to a signal output terminal of the comparator and inputting a polarity signal output from the comparator to detect polarity; Polarity detection / verification using a comparator in a residual sideband receiver comprising a polarity verification device for restoring the polarity when the polarity is inverted due to noise or shock connected to the signal output terminal of the A / D converter Device. 3. The apparatus of claim 2, wherein the polarity detecting device comprises: a sampling unit connected to a signal output terminal of the comparator and sampling the polarity signal output from the comparator in units of segments; A polarity detection / verification device using a comparator in a residual sideband receiver, comprising: a first polarity detector connected to a signal output terminal of the sampling unit to detect polarity through a sampled polarity signal and output a Polarity_D signal; . 3. The apparatus of claim 2, wherein the polarity verification device comprises: a DC remover connected to a signal output terminal of the A / D converter to remove residual DC components; A correlator connected to the signal output terminal of the DC eliminator to determine whether the phase is a normal phase or an inverted phase in a segment synchronization period; A second polarity detector connected to the signal output of the correlator to restore polarity to detect normal polarity; An EX-OR unit connected to signal output terminals of the first and second polarity detectors to perform an EX-OR operation; And a buffer configured to connect to the signal output terminal of the first polarity detector and the EX-OR unit, and a buffer to buffer the polarity detection / verification device using a comparator.

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