KR100324043B1 - Apparatus and method for symbol timing recovery of digital communication receiver - Google Patents

Abstract

The technical field to which the invention described in the claims belongs.

The present invention relates to a symbol timing recovery apparatus for a digital communication receiver.

B. Technical problem to be solved

Provided are a symbol timing recovery apparatus and method capable of accurately recovering symbol timing even in the presence of multipath in a digital communication receiver.

C. Summary of the Solution

The present invention relates to a symbol timing recovery apparatus of a digital communication receiver, comprising: a first phase error detector for detecting a phase error of a matched filtered signal output from a matched filter; and a phase error of an equalized signal output from a channel equalizer. A second phase error detection unit, a loop filter that averages and accumulates the input phase error value, two input terminals and one output terminal, respectively, for the first phase error detection unit and the second input terminal, respectively. A switch unit connecting the output of the phase error detection unit, and in the initial state, to connect the first phase error detection unit to a loop filter connected to the one output terminal, and applying a switching switching control signal to the switch unit. A switching controller for switching switching, and a frequency proportional to a voltage level of a signal output from the loop filter And a voltage controlled oscillator for generating a clock, to generate the necessary clock of an integral multiple from the base clock output from the voltage controlled oscillator, an analog-to characterized in that it comprises parts of a clock generator which is applied to digital converter.

D. Significant Uses of the Invention

It is used for symbol timing recovery in digital communication receivers.

Description

Apparatus and method for symbol timing recovery of digital communication receiver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital communication receiver, and more particularly, to an apparatus and method for recovering symbol timing of a digital communication receiver capable of accurately recovering symbol timing even in the presence of multipath.

1 is a block diagram of a conventional digital communication receiver. Referring to FIG. 1, the digital communication receiver firstly demodulates a received radio frequency (hereinafter referred to as "RF") signal into an intermediate frequency (hereinafter referred to as "IF") signal. 100) and an analog-to-digital converter (A / D), which converts the analog IF signal demodulated and output from the tuner 100 into a digital IF signal. A demodulator 104 for converting a digital IF signal into a baseband signal, and a matched filter 106 for matching and filtering a signal converted from the demodulator 104 to a baseband signal and outputted; In order to reduce the influence of noise due to the multi-path channel, a channel equalizer 108 for channel equalizing the output signal of the matched filter 106 and a signal error due to channel noise Forward Error Correction Decoder (110) , It consists of the symbol timing recovery unit 112 to recover symbol timing of a signal input receiving an output of the matched filter 106. The

2 illustrates a detailed block diagram of the symbol timing recovery apparatus of FIG. 1, wherein the symbol timing recovery apparatus 112 includes a phase error detection unit 200 for obtaining a sampling phase error from an input signal, and the phase error. A loop filter 202 that averages the phase error obtained from the detector 200 and a voltage controlled oscillator for generating a clock having a frequency proportional to the voltage level of the signal output from the loop filter 202. (Voltage Controlled Oscillator: hereinafter referred to as " VCO ") 204 and a clock generator 206 for generating an integral multiple of the required clock from the base clock generated from the VCO 204.

2, the phase error detection unit 200 calculates a phase error of the signal 208 output from the matched filter 106, which varies depending on the system. For example, in the US terrestrial broadcasting HDTV, a phase error is obtained by using a level difference between symbols of a segment synchronization signal having a length of 4 symbols repeated every 832 symbols. The phase error obtained as described above is accumulated and averaged in the loop filter 202 and applied to the VCO 204, and the VCO 204 has a frequency proportional to the voltage level of the signal output from the loop filter 202. Generate a reference clock. The clock generator 206 then multiplies the reference clock applied from the VCO 204 to generate various types of clocks used in the A / D converter 102 and the system.

Meanwhile, in a typical wireless communication system, multipath exists in most cases, and the matching filter of the digital communication receiver is inevitably affected by noise due to the presence of the multipath. In the case of the U.S. terrestrial broadcasting DTV (Digital Television) system, for example, the output of the matched filter and the output of the channel equalizer in the presence of a multipath will be described with reference to FIG. As shown, it can be seen that the output of the matched filter is much more mixed with the noise signal due to the multipath effect than the output of the channel equalizer shown in FIG.

However, conventionally, since the output of the matched filter is used as an input signal for symbol timing recovery even in the presence of the multipath as described above, the performance of the phase error detection unit of the symbol timing recovery device is degraded. The signal to noise ratio (SNR) of the overall system output is increased by increasing the amount of jitter of various clocks used in the system, including the A / D clock generated at the clock generator, which is the final output of the timing recovery apparatus. There was a problem that the reduction of signal-to-noise ratio.

As described above, since the output of the matched filter is used as an input signal for symbol timing recovery even in the presence of the multipath as described above, the performance of the phase error detection unit of the symbol timing recovery device is degraded. The drop is to increase the amount of jitter in the various clocks used in the system, including the A / D clock generated at the clock generator, which is the final output of the symbol timing recovery device, thereby reducing the signal-to-noise ratio of the overall system output. There was a problem brought about.

Accordingly, an object of the present invention is to provide an apparatus and method for recovering symbol timing that can accurately recover symbol timing even in the presence of multipath.

1 is a schematic block diagram of a conventional digital communication receiver;

FIG. 2 is a block diagram of a conventional symbol timing recovery apparatus provided in the digital communication receiver of FIG.

3 is a view schematically showing waveforms of signals output from a matched filter and a channel equalizer of a conventional digital communication receiver in the presence of multipath;

4 is a block diagram of an apparatus for recovering symbol timing according to an embodiment of the present invention;

5, 6, and 7 are flowcharts illustrating operations of a symbol timing recovery apparatus according to an embodiment of the present invention.

According to an aspect of the present invention, there is provided a symbol timing recovery apparatus for a digital communication receiver, comprising: a first phase error detector for detecting a phase error of a matched filtered signal output from a matched filter, and an equalization output from a channel equalizer. A second phase error detection unit for detecting a phase error of the received signal, a loop filter for averaging and accumulating the input phase error value, two input terminals and one output terminal, respectively; A switch unit connecting the output of the first phase error detection unit and the second phase error detection unit and connecting the first phase error detection unit to a loop filter connected to the one output terminal in an initial state; A switching control unit for switching a switching of the switch unit by applying a signal, and a voltage level of a signal output from the loop filter And a clock generator for generating a clock having an integer multiple of a required clock from a basic clock output from the voltage controlled oscillator and applying it to an analog-to-digital converter. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Many specific details are set forth in the following description and in the accompanying drawings, in order to provide a more thorough understanding of the present invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details. And a detailed description of known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

4 is a block diagram of a symbol timing recovery apparatus according to an exemplary embodiment of the present invention. Referring to FIG. 4, the first phase error detection unit 400 detects and outputs a phase error of the matched filtered signal output from the matched filter 106 of FIG. 1. The second phase error detector 402 detects and outputs a phase error of the equalized signal output from the channel equalizer 108. The switch unit 404 connects the first and second phase error detection units 400 and 402 to two a and b input terminals, respectively, and initially the first phase error detection unit 400 through an output terminal c. When the switching switching control signal 416 is applied, the switch is disconnected from the first phase error detection unit 400 and the loop filter 408, and the second phase error detection unit 402 is connected to the first phase error detection unit 402. The loop filter 408 is connected. The switching control unit 406 applies a switching switching control signal 416 to the switch unit 404 to switch the switching of the switch unit 404. The loop filter 408 averages and accumulates phase error values from the first phase error detection unit 400 or the second phase error detection unit 402 connected through the switch unit 404. The VCO 410 generates a clock having a frequency proportional to the voltage level of the signal output from the loop filter 408. The clock generator 412 generates an integer multiple of the required clock from the base clock output from the VCO 410 and applies the clock to the A / D converter 102.

5, 6, and 7 illustrate an operation control flowchart of the symbol timing recovery apparatus shown in FIG. 4 performing symbol timing recovery using the output of the channel equalizer according to an embodiment of the present invention. In the following description of embodiments of the present invention, it is assumed that the switch unit 404 of the symbol timing recovery apparatus 414 connects the first phase error detection unit 400 to the loop filter 408 in an initial state.

First, the first embodiment of the present invention will be described in detail with reference to FIG. 5, which is an operation control flowchart according to the first embodiment of the present invention. First, the switching control unit 406 includes an internal counter provided in step 500. The count value of (Counter) is initialized to "0", and the flow proceeds to step 502 to check whether the count value exceeds a predetermined predetermined value. The predetermined value typically means a time taken for the output of the channel equalizer 108 to stabilize and is preset by the user. At this time, if the count value is smaller than the predetermined predetermined value, the switching control unit 406 proceeds to step 504 and the switching state of the switch unit 404 maintains the initial state as it is, and the phase error detection value for the matched filter output. No switching switching control signal is applied to switch unit 404 to control switching so that 418 is applied to loop filter 408. Subsequently, the switching control unit 406 proceeds to step 506 to increase the count value of the counter by " 1 ", and then returns to step 502 and performs the steps 502 to 506 again while the counter value is increased. Check whether the preset value is exceeded.

On the contrary, when the count value of the counter exceeds the preset value in step 502, the switching controller 406 proceeds to step 508, where the phase error detection value 420 for the channel equalizer output is determined. A switching switching control signal for controlling the switching of the switch unit 404 to be applied to the loop filter 408 is applied to the switch unit 404. Accordingly, the switch unit 404 connects the second phase error detection unit 402 to the loop filter 408 so that the phase error detection value 420 for the channel equalizer output is applied to the loop filter 408.

Next, the second embodiment of the present invention will be described in detail with reference to FIG. 6, which is an operation control flowchart according to the second embodiment of the present invention. The count value of the counter is initialized to "0", and the process proceeds to step 602 to check whether the count value exceeds a predetermined constant value. As described above, the predetermined value means a time taken for the output of the channel equalizer 108 to stabilize, and is preset by the user. At this time, if the count value is smaller than a predetermined predetermined value, the switching control unit 406 proceeds to step 604 and the switching state of the switch unit 404 maintains the initial state as it is, and the phase error detection value for the matched filter output. No switching switching control signal is applied to switch unit 404 to control switching so that 418 is applied to loop filter 408. Subsequently, the switching control unit 406 proceeds to step 606 to increase the count value of the counter by " 1 ", and then returns to step 602 to perform the steps 602 to 606 again while performing the steps 602 to 606. It is checked whether or not the predetermined predetermined value is exceeded.

On the contrary, when the count value of the counter exceeds the preset value in step 602, the switching controller 406 proceeds to step 608, where the phase error detection value 418 for the matched filter output is changed to the channel. It is checked whether the phase error detection value 420 for the equalizer output is larger. At this time, if the phase error detection value 418 for the matched filter output is smaller than the phase error detection value 420 for the channel equalizer output, the switching controller 406 proceeds to step 610 to continue to the matched filter output. No switching switching control signal is applied to the switch unit 404 so that the phase error detection value 418 is applied to the loop filter 408. Accordingly, the phase error detection value 418 for the matched filter output is continuously applied to the loop filter 408 as in the initial state.

On the contrary, if the phase error detection value 418 for the matched filter output is larger than the phase error detection value 420 for the channel equalizer output in step 608, the switching controller 406 proceeds to step 612. A switching switching control signal 416 for controlling the switching of the switch 404 is applied to the switch 404 so that the phase error detection value 420 for the channel equalizer output is applied to the loop filter 408. Accordingly, the switch unit 404 connects the second phase error detection unit 402 to the loop filter 408 so that the phase error detection value 420 for the channel equalizer output is applied to the loop filter 408. Subsequently, the switching control unit 406 returns to step 608 to perform steps 608 to 612 again.

Finally, referring to FIG. 7, which is an operation control flowchart according to the third embodiment of the present invention, the third embodiment of the present invention will be described in detail. First, the switching controller 406 first outputs the channel equalizer output signal at step 700. The signal-to-noise ratio value of 422 is obtained, and the process proceeds to step 702 to check whether the signal-to-noise ratio value of the channel equalizer output signal 422 obtained in the step 700 exceeds the preset threshold. The threshold value is preset by the user to a value of the signal-to-noise ratio at which the output of the channel equalizer 108 is determined to be stable. At this time, if the signal-to-noise ratio value of the channel equalizer output signal 422 is smaller than the preset threshold in step 702, the switching control unit 406 proceeds to step 704 to the switching state of the switch unit 404. Does not apply any switching switching control signal for controlling the switching to the switch unit 404 such that the phase error detection value 418 for the matched filter output is applied to the loop filter 408 while maintaining the initial state. Accordingly, the phase error detection value 418 for the matched filter output is subsequently applied to the loop filter 408.

On the contrary, when the signal-to-noise ratio value of the channel equalizer output signal 422 exceeds the preset threshold in step 702, the switching controller 406 proceeds to step 706 to output the channel equalizer output. A switching switching control signal 416 for controlling the switching of the switch unit 404 is applied to the switch unit 404 so that the phase error detection value 420 is applied to the loop filter 408. Accordingly, the switch unit 404 connects the second phase error detection unit 402 to the loop filter 408 so that the phase error detection value 420 for the channel equalizer output is applied to the loop filter 408.

Therefore, the correct symbol timing is recovered by using the channel equalizer output signal whose noise is significantly reduced by channel equalization, instead of using the matched filter output signal that is affected by noise in the presence of multipath, for symbol timing recovery. You can do it.

As described above, the present invention can recover the correct symbol timing by using the channel equalizer output signal which is less affected by the noise in the presence of multipath in the digital communication receiver for symbol timing recovery, and reduces the amount of timing jitter to reduce the timing of the receiver. There is an advantage to improve performance.

Claims (7)

A tuner for demodulating a radio frequency signal received from an antenna into an intermediate frequency signal, an analog-to-digital converter for converting an analog signal demodulated with the intermediate frequency signal to a digital signal, and a baseband signal for demodulating the digitally converted intermediate frequency signal. A matched filter for matching and outputting the demodulator and the baseband signal, a channel equalizer for equalizing the matched filtered baseband signal, and an F.C.C. correcting error due to channel noise of the channelized signal. In the symbol timing recovery apparatus of a digital communication receiver having at least a decoder, A first phase error detector for detecting a phase error of the matched filtered signal output from the matched filter; A second phase error detector for detecting a phase error of the equalized signal output from the channel equalizer; A loop filter that averages and accumulates the input phase error value; A switch unit for inputting the outputs of the first phase error detection unit and the second phase error detection unit to respective input terminals to selectively apply the outputs to the loop filter; A switching control unit for switching the switching of the switch unit by applying a switching switching control signal to the switch unit; A voltage controlled oscillator for generating a clock having a frequency proportional to a voltage level of the signal output from the loop filter; And a clock generator for generating an integral multiple of the required clock from the basic clock output from the voltage controlled oscillator and applying it to the analog-to-digital converter. The method of claim 1, wherein the switching control unit, And a counter provided therein to output the switching switching control signal to the switch unit so that the second phase error detection unit and the loop filter are connected when the counter exceeds a predetermined value. Timing recovery device. The method of claim 1, wherein the switching control unit, After receiving and comparing the phase error values detected by the first phase error detection unit and the second phase error detection unit, the phase error value of the first phase error detection unit is greater than the phase error value of the second phase error detection unit. And outputting the switching switching control signal to the switch unit such that a second phase error detection unit and the loop filter are connected to each other. The method of claim 1, wherein the switching control unit, The signal-to-noise ratio (SNR) value of the equalized signal outputted from the channel equalizer is examined and the second phase error detection unit and the loop filter are connected to the switch unit when the signal-to-noise ratio value exceeds a preset threshold. A symbol timing recovery apparatus for a digital communication receiver, characterized by outputting a switching switching control signal. A tuner for demodulating a radio frequency signal received from an antenna into an intermediate frequency signal, an analog-to-digital converter for converting an analog signal demodulated with the intermediate frequency signal to a digital signal, and a baseband signal for demodulating the digitally converted intermediate frequency signal. A matched filter for matching and outputting the demodulator and the baseband signal, a channel equalizer for equalizing the matched filtered baseband signal, and an F.C.C. correcting error due to channel noise of the channelized signal. In a symbol timing recovery method of a symbol timing recovery apparatus comprising a first phase error detection unit, a second phase error detection unit, a switch unit, a switching control unit, a loop filter, a voltage controlled oscillator, and a clock generator in a digital communication receiver having at least a decoder. , Applying a phase error value of a signal filtered and matched from the matched filter to the loop filter until the count value of the internal counter in the switching controller reaches a predetermined value; If the count value of the internal counter exceeds a predetermined value, the phase error value of the signal output by channel equalization from the channel equalizer by switching the switching of the switch unit from the first phase error detection unit to the second phase error detection unit. The symbol timing recovery method comprising the step of applying to the loop filter. A tuner for demodulating a radio frequency signal received from an antenna into an intermediate frequency signal, an analog-to-digital converter for converting an analog signal demodulated with the intermediate frequency signal to a digital signal, and a baseband signal for demodulating the digitally converted intermediate frequency signal. A matched filter for matching and outputting the demodulator and the baseband signal, a channel equalizer for equalizing the matched filtered baseband signal, and an F.C.C. correcting error due to channel noise of the channelized signal. In a symbol timing recovery method of a symbol timing recovery apparatus comprising a first phase error detection unit, a second phase error detection unit, a switch unit, a switching control unit, a loop filter, a voltage controlled oscillator, and a clock generator in a digital communication receiver having at least a decoder. , Comparing the phase error value detected from the matched output signal from the matched filter with the channel equalized output signal from the channel equalizer; Applying a phase error value of the matched filtered output signal to the loop filter when the phase error value of the matched filtered output signal is smaller than the phase error value of the channel equalized output signal as a result of the comparison; If the phase error value of the matched filtered output signal is greater than the phase error value of the channel equalized output signal, applying the phase error value of the channel equalized output signal to the loop filter. Symbol timing recovery method. A tuner for demodulating a radio frequency signal received from an antenna into an intermediate frequency signal, an analog-to-digital converter for converting an analog signal demodulated with the intermediate frequency signal to a digital signal, and a baseband signal for demodulating the digitally converted intermediate frequency signal. A matched filter for matching and outputting the demodulator and the baseband signal, a channel equalizer for equalizing the matched filtered baseband signal, and an F.C.C. correcting error due to channel noise of the channelized signal. In a symbol timing recovery method of a symbol timing recovery apparatus comprising a first phase error detection unit, a second phase error detection unit, a switch unit, a switching control unit, a loop filter, a voltage controlled oscillator, and a clock generator in a digital communication receiver having at least a decoder. , Checking a signal-to-noise ratio of a signal received by the tuner and output by channel equalization through the channel equalizer; Applying a phase error value of the matched filtered output signal of the received signal to the loop filter when the signal to noise ratio value is smaller than a predetermined threshold value; And if the signal-to-noise ratio exceeds the predetermined threshold, applying the phase error value of the channel equalized output signal of the received signal to the loop filter. Way.