KR100252848B1 - Method of manufacturing dual gate oxidation film - Google Patents

Method of manufacturing dual gate oxidation film Download PDF

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KR100252848B1
KR100252848B1 KR1019970049214A KR19970049214A KR100252848B1 KR 100252848 B1 KR100252848 B1 KR 100252848B1 KR 1019970049214 A KR1019970049214 A KR 1019970049214A KR 19970049214 A KR19970049214 A KR 19970049214A KR 100252848 B1 KR100252848 B1 KR 100252848B1
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oxide film
dual gate
photoresist
forming
film
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KR1019970049214A
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KR19990026899A (en
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노재성
허윤준
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Formation Of Insulating Films (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A method for forming a dual gate oxide film is provided to improve the uniformity of an oxide film and to simplify the manufacture process. CONSTITUTION: A method for forming a dual gate oxide film oxidizes a silicon substrate(31) to form the first oxide film(32) having the first thickness. A nitride film(33) is deposited on the first oxide film(32). A photoresist is applied on the nitride film(33) and is then patterned by exposure and development process. The nitride film(33) is deposited by low temperature chemical vapor deposition method and has the thickness of 10 - 30 angstrom. The nitride film(33) and the first oxide film(32) are selectively removed using the patterned photoresist to expose one side surface of the silicon substrate(31). The photoresist is removed and a portion through which the surface of the silicon substrate(31) is exposed is oxidized to form the second oxide film(35). When the second oxide film(35) is formed, growth of the first oxide film(32) is prohibited by means of the nitride film(33) on the first oxide film(32).

Description

듀얼 게이트 산화막의 형성방법How to Form Dual Gate Oxide

본 발명은 반도체 소자의 제조방법에 관한 것으로 특히, 로직 디바이스(Logic Device)에 적당한 듀얼 게이트(Dual Gate) 산화막의 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of forming a dual gate oxide film suitable for a logic device.

이하, 첨부된 도면을 참조하여 종래의 듀얼 게이트 산화막의 형성방법을 설명하면 다음과 같다.Hereinafter, a method of forming a conventional dual gate oxide film will be described with reference to the accompanying drawings.

도 1a 내지 도 1c는 종래의 듀얼 게이트 산화막의 형성방법을 나타낸 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a conventional dual gate oxide film.

도 1a에 도시한 바와같이 실리콘 기판(11)을 산화시키어 표면에 제 1 두께를 갖는 제 1 산화막(12)을 형성하고, 상기 제 1 산화막(12)상에 포토레지스트(Photo Resist)(13)를 도포한 후, 노광 및 현상공정으로 포토레지스트(13)를 패터닝(Patterning)한다.As shown in FIG. 1A, the silicon substrate 11 is oxidized to form a first oxide film 12 having a first thickness on a surface thereof, and a photoresist 13 is formed on the first oxide film 12. After coating, the photoresist 13 is patterned by exposure and development.

도 1b에 도시한 바와같이 상기 패터닝된 포토레지스트(13)를 마스크로 이용하여 습식식각(Wet Etch) 공정으로 상기 제 1 산화막(12)을 선택적으로 제거하여 상기 실리콘 기판(11)의 일측 표면을 노출시키다.As shown in FIG. 1B, the surface of one side of the silicon substrate 11 is selectively removed by selectively removing the first oxide layer 12 by wet etching using the patterned photoresist 13 as a mask. Expose

도 1c에 도시한 바와같이 상기 포토레지스트(13)를 제거하고, 상기 제 1 산화막(12)이 제거된 실리콘 기판(11)의 표면을 산화시키어 실리콘 기판(11)의 표면에 제 2 두께를 갖는 제 2 산화막(14)을 형성한다.As shown in FIG. 1C, the photoresist 13 is removed, and the surface of the silicon substrate 11 from which the first oxide film 12 is removed is oxidized to have a second thickness on the surface of the silicon substrate 11. The second oxide film 14 is formed.

여기서 상기 제 2 산화막(14)을 형성시키기 위하여 산화시킬 때 상기 제 1 산화막(12)도 성장되어 표면이 불균일하게 된다.Here, when oxidizing to form the second oxide film 14, the first oxide film 12 is also grown, resulting in uneven surfaces.

도 2a 내지 도 2c는 종래의 또 다른 듀얼 게이트 산화막의 형성방법을 나타낸 공정단면도이다.2A to 2C are cross-sectional views illustrating a method of forming another conventional dual gate oxide film.

도 2a에 도시한 바와같이 실리콘 기판(21)상에 제 1 포토레지스트(22)를 도포한 후, 노광 및 현상공정으로 제 1 포토레지스트(22)를 패터닝한다.After the first photoresist 22 is applied onto the silicon substrate 21 as shown in FIG. 2A, the first photoresist 22 is patterned by an exposure and development process.

도 2b에 도시한 바와같이 상기 패터닝된 제 1 포토레지스트(22)를 마스크로 이용하여 상기 실리콘 기판(21)의 표면이 노출된 부분에 질소(Nitrogen)이온을 주입하여 제 1 두께를 갖는 제 1 산화막(23)을 형성한다.As shown in FIG. 2B, by using the patterned first photoresist 22 as a mask, a first thickness having a first thickness is injected by injecting nitrogen ions into an exposed portion of the surface of the silicon substrate 21. The oxide film 23 is formed.

도 2c에 도시한 바와같이 상기 제 1 포토레지스트(22)를 제거하고, 상기 제 1 산화막(23)을 포함한 실리콘 기판(21)의 전면에 제 2 포토레지스트(24)을 도포한 후, 노광 및 현상공정으로 상기 제 1 산화막(23)상에만 제 2 포토레지스트(24)가 남도록 패터닝한다.As shown in FIG. 2C, the first photoresist 22 is removed, and the second photoresist 24 is coated on the entire surface of the silicon substrate 21 including the first oxide film 23. In the developing step, the second photoresist 24 remains on the first oxide film 23 only.

이어, 상기 패터닝된 제 2 포토레지스트(24)를 마스크로 이용하여 실리콘 기판(21)의 표면이 노출된 부분에 불소(Fluorine)이온을 주입하여 제 2 두께를 갖는 제 2 산화막(25)을 형성한다.Subsequently, the second oxide film 25 having the second thickness is formed by injecting fluorine ions into the exposed portions of the silicon substrate 21 using the patterned second photoresist 24 as a mask. do.

그러나 이와 같은 종래의 듀얼 게이트 산화막의 형성방법에 있어서 다음과 같은 문제점이 있었다.However, the conventional method of forming the dual gate oxide film has the following problems.

첫째, 습식식각 및 산화막 성장으로 제 1, 제 2 두께를 갖는 산화막을 형성할 때 제 1 산화막을 형성한 후, 제 2 산화막을 형성하기 때문에 제 1 산화막의 두께가 불균일하고 공정이 복잡하다.First, when the oxide films having the first and second thicknesses are formed by wet etching and oxide film growth, the first oxide film is formed and then the second oxide film is formed.

둘째, 이온주입에 의해 산화막을 형성하기 때문에 기판의 손상으로 인한 디펙트(Defect)형성에 의하여 접합 누설 전류가 증가한다.Second, since the oxide film is formed by ion implantation, the junction leakage current increases due to defect formation due to damage to the substrate.

셋째, 이온주입에 의해 산화막 형성시 이온주입의 에너지 및 양의 조절이 어렵다.Third, it is difficult to control the energy and amount of ion implantation when the oxide film is formed by ion implantation.

본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 산화막의 균일도 및 제조공정을 간소화시키도록 한 듀얼 게이트 산화막의 형성방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and an object thereof is to provide a method of forming a dual gate oxide film to simplify the uniformity and manufacturing process of the oxide film.

도 1a 내지 도 1c는 종래의 듀얼 게이트 산화막의 형성방법을 나타낸 공정단면도1A to 1C are cross-sectional views illustrating a method of forming a conventional dual gate oxide film.

도 2a 내지 도 2c는 종래의 또 다른 듀얼 게이트 산화막의 형성방법을 나타낸 공정단면도2A through 2C are cross-sectional views illustrating a method of forming another conventional dual gate oxide film.

도 3a 내지 도 3c는 본 발명에 의한 듀얼 게이트 산화막의 형성방법을 나타낸 공정단면도3A to 3C are cross-sectional views illustrating a method of forming a dual gate oxide film according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

31 : 실리콘 기판 32 : 제 1 산화막31 silicon substrate 32 first oxide film

33 : 질화막 34 : 포토레지스트33: nitride film 34: photoresist

35 : 제 2 산화막35: second oxide film

상기와 같은 목적을 달성하기 위한 본 발명에 의한 듀얼 게이트 산화막의 형성방법은 기판상에 제 1 두께를 갖는 제 1 산화막을 형성하는 단계와, 상기 제 1 산화막상에 질화막을 증착하는 단계와, 상기 기판의 일측표면이 노출되도록 상기 질화막 및 제 1 산화막을 선택적으로 제거하는 단계와, 그리고 상기 기판의 표면이 노출된 부분에 제 2 두께를 갖는 제 2 산화막을 형성하는 단계를 포함하여 형성함을 특징으로 한다.A method of forming a dual gate oxide film according to the present invention for achieving the above object comprises the steps of forming a first oxide film having a first thickness on a substrate, depositing a nitride film on the first oxide film, and And selectively removing the nitride film and the first oxide film so that one surface of the substrate is exposed, and forming a second oxide film having a second thickness on the exposed part of the substrate. It is done.

이하, 첨부된 도면을 참고하여 본 발명에 의한 듀얼 게이트 산화막의 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a dual gate oxide film according to the present invention will be described in detail with reference to the accompanying drawings.

도 3a 내지 도 3c는 본 발명에 의한 듀얼 게이트 산화막의 형성방법을 나타낸 공정단면도이다.3A to 3C are cross-sectional views illustrating a method of forming a dual gate oxide film according to the present invention.

도 3a에 도시한 바와같이 실리콘 기판(31)을 산화시키어 제 1 두께를 갖는 제 1 산화막(32)을 형성한다.As shown in FIG. 3A, the silicon substrate 31 is oxidized to form a first oxide film 32 having a first thickness.

이어, 상기 제 1 산화막(32)상에 질화막(33)을 증착하고, 상기 질화막(33)상에 포토레지스트(34)를 도포한 후, 노광 및 현상공정으로 패터닝한다.Subsequently, a nitride film 33 is deposited on the first oxide film 32, a photoresist 34 is coated on the nitride film 33, and then patterned by exposure and development processes.

여기서 상기 질화막(33)은 저온화학기상법으로 증착하며, 그 두께는 10 ~ 30Å으로 증착한다.Here, the nitride film 33 is deposited by a low temperature chemical vapor deposition method, the thickness is deposited to 10 ~ 30Å.

도 3b에 도시한 바와같이 상기 패터닝된 포토레지스트(34)를 마스크로 이용하여 상기 질화막(33) 및 제 1 산화막(32)을 선택적으로 제거하여 상기 실리콘 기판(31)의 일측 표면을 노출시킨다.As shown in FIG. 3B, the nitride film 33 and the first oxide film 32 are selectively removed using the patterned photoresist 34 as a mask to expose one surface of the silicon substrate 31.

도 3c에 도시한 바와같이 상기 포토레지스트(34)를 제거하고, 상기 실리콘 기판(31)의 표면이 노출된 부분을 산화시키어 제 2 두께를 갖는 제 2 산화막(35)을 형성한다.As shown in FIG. 3C, the photoresist 34 is removed and the exposed portion of the silicon substrate 31 is oxidized to form a second oxide film 35 having a second thickness.

여기서 상기 제 2 산화막(35)을 형성할 때 상기 제 1 산화막(32)상의 질화막(33)에 의해 제 1 산화막(32)의 성장을 억제한다.Here, when the second oxide film 35 is formed, the growth of the first oxide film 32 is suppressed by the nitride film 33 on the first oxide film 32.

한편, 상기 제 1, 제 2 두께는 서로 다른 두께이다.Meanwhile, the first and second thicknesses are different thicknesses.

이상에 설명한 바와같이 본 발명에 의한 듀얼 게이트 산화막의 형성방법에 있어서, 제 1 두께를 갖는 산화막을 형성한 후, 기판을 산화시키어 제 2 두께를 갖는 산화막을 형성하더라도 제 1 산화막상의 질화막에 의해 제 1 산화막의 성장을 억제하기 때문에 균일도 및 제조공정을 간소화시킬 수 있는 효과가 있다.As described above, in the method for forming a dual gate oxide film according to the present invention, after forming an oxide film having a first thickness, the substrate is oxidized to form an oxide film having a second thickness. Since the growth of the oxide film is suppressed, the uniformity and the manufacturing process can be simplified.

Claims (3)

기판상에 제 1 두께를 갖는 제 1 산화막을 형성하는 단계;Forming a first oxide film having a first thickness on the substrate; 상기 제 1 산화막상에 질화막을 증착하는 단계;Depositing a nitride film on the first oxide film; 상기 기판의 일측표면이 노출되도록 상기 질화막 및 제 1 산화막을 선택적으로 제거하는 단계;Selectively removing the nitride film and the first oxide film to expose one surface of the substrate; 상기 기판의 표면이 노출된 부분에 제 2 두께를 갖는 제 2 산화막을 형성하는 단계를 포함하여 형성함을 특징으로 하는 듀얼 게이트 산화막의 형성방법.And forming a second oxide film having a second thickness on a portion where the surface of the substrate is exposed. 제 1 항에 있어서,The method of claim 1, 상기 질화막은 10 ~ 30Å 두께를 갖도록 저온화학기상법으로 증착하는 것을 특징으로 하는 듀얼 게이트 산화막의 제조방법.The nitride film is a method of manufacturing a dual gate oxide film, characterized in that the deposition by low temperature chemical vapor deposition method to have a thickness of 10 ~ 30Å. 제 1 항에 있어서,The method of claim 1, 상기 제 1, 제 2 두께는 서로 다른 두께로 형성하는 것을 특징으로 하는 듀얼 게이트 산화막의 제조방법.And the first and second thicknesses are formed to have different thicknesses.
KR1019970049214A 1997-09-26 1997-09-26 Method of manufacturing dual gate oxidation film KR100252848B1 (en)

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