KR100249786B1 - High voltage device having trench structure drain - Google Patents

Abstract

The present invention provides a field effect of 100V or more having a so-called lateral double diffused MOS (LDMOS) structure in which source, gate, drift region, and drain are horizontally disposed. A structure of a high voltage device, the drain of the drift region so that the drain is formed to extend in the vertical direction of the substrate in order to increase the breakdown voltage generated at the drain edge in contact with the drift region when the high voltage is applied to the high voltage device A trench was formed in the formation region, and a drain having a predetermined depth was formed along the inner wall surface of the trench.

According to the present invention, the breakdown voltage can be increased by dispersing the impact ionization of electrons traveling along the surface of the substrate from the source to the drain vertically at the edge of the drain when the high voltage is applied, thereby improving the operating voltage of the high voltage device.

Description

High Voltage Device with Trench Drain

The present invention relates to a high voltage device, and more particularly to a high voltage device having a drain of a trench structure in order to improve the voltage breakdown of the drain.

In general, hundreds of V class high voltage devices using silicon or the like are a kind of power devices and are used in display devices requiring high voltage operation, or drivers such as servo motors and actuators.

3 is a cross-sectional view of a conventional LDMOS high voltage device.

In the LDMOS type high voltage device of FIG. 3, the well region 42 and the drifting region 43 are formed on the substrate 41, and the gate 45 is insulated from the upper side of the well region 42 and the drifting region 43 by an insulating film. A drain 26 is formed in the surface portion, and a source 44 and a well-connected guide window 47 are formed in the well region.

In the conventional high voltage device of FIG. 3, when a high voltage is applied to the drain 46, when the gate voltage is 0V, i.e., "off", the voltage breakdown occurs in the area 55 from the stray area 43 to the substrate 41, or It occurs in the junction region 56 of the drift region 43 and the well region 42 or in the edge region 57 of the active region near it. In other words, at " off " of the gate voltage, voltage breakdown occurs in a region far from drain 46.

On the contrary, when the highest operating voltage is applied to the gate 45, that is, "on", the voltage breakdown moves toward the drain 46, and voltage breakdown occurs in the drain edge region 58.

The voltage breakdown of drain 46 at " on " of the device is such that when electrons flow from source 44 to drain 46, current flows along the surface and reaches drain 46, where electric field is driven to a strongly formed drain surface region. This is due to the impact ionization of electrons caused by the senses.

Therefore, in the conventional high voltage device, since the drain 46 is formed by doping impurities on the semiconductor surface, electrons at the "on" time of the device flow horizontally along the surface of the stray area 43 from the source 44 to the drain 46, and thus the electrons. Flow chart of the surface is driven to the surface edge of the drain 46, the impact ionization phenomenon easily occurs.

This impact ionization current increases exponentially with the strength of the electric field when the channel current from source 44 reaches the strong field-forming region of the surface edge of drain 46 and hits it intensively, resulting in secondary and tertiary impacts. Ionization also occurs, causing a so-called voltage breakdown in which the non-steady current rapidly increases in drain 46.

The electric field at the edge of the drain surface is related to the strength of the electric field spread horizontally in the drift region 43, the doping distribution of the drain, and the geometric structure between the oxide film 63 and the upper metal plate of the drain.

The most important horizontal electric field is shortening the horizontal length of the drift region 43 to reduce the internal resistance of the device, or the well junction voltage breakdown of the junction region 56 between the well region 42 and the drift region 43, or the edge voltage breakdown region of the active region 57. It is often formed when the depletion layer extends vertically in the drifting region 43 by thinning the thickness of the drifting region 43 to improve the voltage breakdown.

The reason is that in the conventional high voltage device, the drain 46 is formed by doping impurities on the surface of the semiconductor, so electrons at " on " of the device flow horizontally along the surface of the drift region mainly from the source 44 to the drain 46, and thus the electrons. The flow rate of P is driven to the surface edge of the planar drain, making shock ionization easier.

The electric field at the edge of the drain surface is related to the strength of the electric field spreading horizontally in the drift region, the doping concentration structure of the drain, and the geometrical structure between the oxide film and the drain electrode upper plate. The electric field is generated when the depletion layer is vertically extended by shortening the horizontal length of the drift region to reduce the internal resistance of the device, or by improving the voltage breakdown of the well junction voltage breakdown generation region 36 or the active voltage edge breakdown region 37. In order to reduce the operating resistance of the device is inevitable.

As a result, the conventional high voltage device has a disadvantage in that the breakdown voltage is low such that the drain breakdown voltage is only 35V when the gate voltage is 5V (Vg = 5V) as shown in FIG. 5.

The LDMOS type high voltage device according to the related art has a structure in which a drain is formed by doping impurities into a surface region of a semiconductor substrate, and electrons move along the surface region of the substrate from the source to the drain when a high voltage is applied to the gate. Due to the impact ionization of, voltage breakdown occurs in the surface area of the drain, thereby reducing the breakdown voltage of the high voltage device.

The present invention is to solve the above-mentioned problems of the prior art to provide a high-voltage device having a drain structure capable of manufacturing a device 100V or more by increasing the breakdown voltage of the drain.

According to the high voltage device of the present invention for achieving the object of the present invention, a well region and a drifting region in contact with each other on a semiconductor substrate, a source is formed in the well region, a drain is formed in the drifting region, In an LDMOS type high voltage device in which a gate having a predetermined width through an oxide film is formed over the well region and the upper region of the drifting region, the drain is predetermined from a surface of the drifting region formed by etching with a predetermined depth and width. It has a trench structure formed to a depth of the drain, characterized in that the drain connection wiring metal terminal is formed in contact with the surface of the drain to fill the trench.

1 is a plan view of a high pressure device according to the present invention;

2 is a cross-sectional view of a high voltage device according to the present invention;

3 is a cross-sectional view of a high voltage device according to the prior art,

4 is a drain voltage-current characteristic diagram of the high-voltage device of the present invention;

5 is a drain voltage-current characteristic diagram of a high voltage device of the prior art;

6 to 15 are cross-sectional views showing a manufacturing process sequence of the high-voltage device according to the present invention;

6 is a cross-sectional view after growth of a semiconductor substrate and an oxide film;

7 is a cross-sectional view after the formation of the drift region,

8 is a cross-sectional view after well formation;

9 is a cross sectional view after field oxide film growth;

10 is a cross-sectional view after the growth of a gate oxide film;

11 is a cross-sectional view after polysilicon coating and gate formation;

12 is a cross-sectional view after trench formation in the drain region;

FIG. 13 is a cross-sectional view after source / drain formation; FIG.

14 is a cross-sectional view after additional coating of an insulating film and opening of a metal terminal contact point;

15 is a cross-sectional view of the completed device after connecting the metal terminal,

<Explanation of symbols for main parts of drawing>

22,42: well area 23,43: drift area

24,44 source 25,45 polysilicon gate

26,46: Drain 27,47: Well Connected India Window

11 source connection point 12 gate connection point

13 drain connection point 14 well connection point

21 and 41: semiconductor substrate 28,48: source connection wiring metal terminal

29,49: gate connection wiring metal terminal

30,50: drain connection wiring metal terminal

35,55: area of bulk breakdown

36,56: Well junction breakdown occurrence area

37,57: Active edge breakdown generation area

38,58: Drain edge breakdown area

60,61,62,63: oxide film

A feature of the present invention for achieving the above object is to trench the drain region without forming a drain on the semiconductor surface as in the conventional high voltage device structure in order to suppress the drain voltage breakdown when the high voltage device is on. Dig deep into the structure to dope the inside, and has a structure in which the drain terminal is formed by filling the metal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of the LDMOS type high voltage device of the present invention, Figure 2 is a structural diagram showing a cross-section along the line AA 'of FIG.

1 and 2, in the LDMOS type high voltage device of the present invention, the drifting region 23 and the well region 22 are formed on the semiconductor substrate 21, the drain 26 having the trench structure is formed in the predetermined region of the drifting region 23, A source 24 is formed in the well region 22, a well guide window 27 is formed in contact with the source 24, and a gate 25 is formed through the insulating layer over the drift region 23 and the well region 22. The wiring metal terminals 28, 29, and 30 are formed in the openings exposing the well guide window 27, the gate 25, and the drain 26, respectively.

In addition, a source connection point 11 and a well connection point 14 are formed above the source 24 and the well delivery window 27, a gate connection point 12 is formed above the gate 25, and a drain connection point 13 is formed above the drain 26.

Hereinafter, each region of the high voltage device having the structure of FIG. 2 will be described in detail.

Reference numeral 21 is a substrate of a p-type semiconductor, and the impurity concentration of the substrate is about 1 × 10 ¹⁴ / cm ³ to 2 × 10 ¹⁵ / cm ³ of boron.

23 is a drift region, which is n ⁻ type as a region where the depletion is applied to internally support the applied voltage when a high voltage of 100 V or more is applied to the drain metal terminal 30. Is about 1 × 10 ¹⁵ / cm ³ to 2 × 10 ¹⁶ / cm ³ , and the bonding depth is about 0.5 μm to 6 μm. The higher the junction concentration, the smaller the junction depth; conversely, the lower the junction concentration, the deeper the junction depth should be. And the horizontal length of the drift region increases with the operating voltage and is about 4 μm in the 100V class but more than 10 μm in the several 100V class or more.

22 is a well region, a p-type region for supplying electrons and controlling the amount of electrons as a semiconductor channel current. The surface impurity concentration is about boron 1 × 10 ¹⁷ / cm ³ , and the diffusion depth is 4 μm. It is about -6 micrometers.

24 denotes a source in a well region, which supplies electrons during device operation. The n ⁺ type has a high concentration of arsenic of at least 10 ¹⁹ / cm ³ and a junction depth of about 0.2 μm to 0.4 μm.

25 is a gate made of polysilicon and controls the flow of electrons from the source. This gate has a thickness of about 0.3 µm to 0.4 µm, and is a conductive layer which is doped with an arsenic of at least 10 ¹⁹ / cm ³ in an n ⁺ type such as source / drain.

26 is a drain, which absorbs electrons during device operation, and has a n ⁺ type like source, which has a high doping concentration of 10 ¹⁹ / cm ³ or more, and a junction depth of about 0.2 μm to 0.4 μm. to be. In the present invention, the structure of the drain is not a planar structure such as a source, but a vertical three-dimensional structure of the trench. The trench has a depth of about 2 µm and a width of about 2 µm. If the depth of the trench is too shallow, the dispersing effect of the drain current is lost. On the contrary, if the depth is too deep, bulk voltage breakdown occurs easily in the region 35, and it is difficult to fill the trench with the metal terminal 30. If the width of the trench is too small, it is difficult to fill the metal. If the width of the trench is too large, the surface is uneven after filling the metal layer and a severe curved layer of the shape remains in the trench. This drain doping is formed by diffusion of impurities from the inside of the trench into the semiconductor substrate prior to filling the metal.

27 is a guiding window of the well region, which helps to make the potential of the well region equal to the source 24, and the doping concentration of boron in the p ⁺ type is higher than several 10 ¹⁹ / cm ³ and the junction depth is It is about 0.3 micrometer-about 0.5 micrometer.

28, 29, and 30 are source, gate, and drain connection wiring metal terminals, respectively, and the main metal is made of Al alloy. In particular, the metal of the drain wiring metal terminal 30 fills the trench and contacts the doping layer of the drain 26, so that heat dissipation can be efficiently performed.

35 denotes a pn junction voltage breakdown (bulk voltage breakdown) generation region that occurs from the stray region (n ⁻ type) to the substrate (p ⁻ type).

36 shows a pn junction voltage breakdown (well junction voltage breakdown) generation region of the stray region (n ⁻ type) and the well region (p type).

37 shows an area where voltage breakdown (active area voltage breakdown) occurs due to a sharp electric field distortion caused by a geometric structure at the edge of the active area of the gate 25 (that is, the area bent from the shallow gate oxide to the thick field oxide). Indicates.

38 shows a drain voltage breakdown (drain edge voltage breakdown) generating region caused by the impact ionization of electrons generated when electrons flow from the source to the drain and pass through the strongly formed drain surface edge region.

This drain voltage breakdown is relatively easy to occur when no current flows, i.e., when the current flows more than the "off" state, that is, when the device is "on".

62 represents an insulating layer of silicon dioxide (SiO ₂ ), and the thickness is about 1 μm.

As shown in FIG. 2, the high voltage device of the present invention having such a structure does not doped the drain 26 from the surface of the semiconductor as compared with FIG. 3, which is a conventional high voltage device, and digs deep into the semiconductor to form a trench. After the structure was formed, impurities were doped into the trench toward the semiconductor, and the trench was finally filled with the drain connection wiring metal 30.

Therefore, in the present invention, in order to suppress drain voltage breakdown when the device is “on”, as shown in FIG. 3, which is a conventional structure, the drain is not deeply formed on the surface of the semiconductor, but the drain region is dug deep into the trench to dope the inside. By filling the metal into the drain terminal, the flow of electrons concentrated only at the surface edge of the planar drain can be vertically dispersed in the conventional high voltage device, thereby reducing the impact ionization phenomenon and improving the drain breakdown voltage.

That is, in the high voltage device of the present invention, when a high voltage is applied to the drain 26, when the gate voltage is 0 V, i.e., "off", the voltage breakdown occurs in the region 35 in contact with the substrate 21 side in the drift region 23 as shown in FIG. Bulk voltage breakdown occurs, or well junction voltage breakdown occurs in junction surface region 36 between drift region 23 and well region 22, and active region edge voltage breakdown occurs in edge region 37 of the active region in the vicinity. In other words, when "off", voltage breakdown occurs in a region far from drain 26. In contrast, when the highest operating voltage is applied to the gate, i.e., " on, " the voltage breakdown moves to the drain 26 and voltage breakdown occurs at the edge region 38 of the drain 26.

At this time, in the trench drain structure of the present invention, the strength of the electric field at the edge of the drain surface is not different from the conventional structure, but the drain 26 is formed in the trench deep inside the substrate so that the electrons generated in the channel reach the drain 26. In this case, the impact ionization phenomenon is suppressed by dispersing to a depth deep vertically where the electric field strength is relatively weak compared to the surface, and also prevents secondary and tertiary growth. Computer simulation results for this are shown in FIGS. 4 and 5.

4 and 5 are typical 100V class devices, except for the device structure invented and the conventional device, except for the drain structure modification of the present invention, all of which are computer simulated drain voltage-drain current curves under the same conditions. 5, the drain breakdown voltage is only 35V when the gate maximum voltage is 5V (Vg = 5V). However, in the device of the present invention, as shown in FIG. There is a number.

In addition, the advantage of the device of the present invention is that the drain connection wiring metal terminal formed by being buried in the trench has a much higher thermal conductivity than the drain connection wiring metal terminal of the conventional device, thereby facilitating heat generated in the drain region easily. Emissions can also increase reliability during device operation. In this high voltage device, the current flows through the voltage of several 100V for the device of 5V or less, so the amount of heat generated per unit area is large in proportion to the voltage. Most of this heat is generated in the drain area where the area is relatively narrow and the current is concentrated. Therefore, this buried drain metal terminal structure can effectively suppress the heat generation of the device.

Hereinafter, a process of manufacturing the high voltage device of the present invention will be described with reference to FIGS. 6 to 15.

Referring to FIG. 6, a silicon substrate 21 doped with boron, which is a p-type impurity, of about 1 × 10 ¹⁴ / cm ³ to 2 × 10 ¹⁵ / cm ³ is oxidized at a high temperature of 900 ° C. or higher to form an oxide film on this surface. To form.

Subsequently, as shown in FIG. 7, in order to form the n ⁻ type drift region 23, a portion of the oxide film 60 is etched to a predetermined depth only by a photolithography method to form an impurity implantation window. Phosphorus 1 × 10 ¹² / cm ² to 2 × 10 ¹² / cm ² were injected with an initial impurity, and thermal diffusion was performed at 1150 ° C. for about 6 hours to form a drifting region 23 in a predetermined region in the substrate 21. do. At this time, the surface concentration of the drift region 23 is about 1 × 10 ¹⁵ / cm ³ to 2 × 10 ¹⁶ / cm ³ , and the bonding depth is about 0.5 μm to several μm.

Subsequently, as shown in FIG. 8, an initial impurity of about 3 × 10 ¹³ / cm ² is implanted into boron into the substrate 21 in contact with the drift region 23, and thermally diffused at about 1150 ° C. for about 10 hours. In this case, the surface concentration is about 1 × 10 ¹⁷ / cm ³ , and the diffusion depth is about 4 μm to 6 μm.

Next, as shown in FIG. 9, the upper surface of the portion where the well region 22 defined as the active region and the drifting region 23 are in contact with each other to remove the remaining oxide film 60 and define the field region and the active region. After forming a nitride film pattern (not shown) in a predetermined region of the upper surface of the film, the exposed portion was formed by oxidizing with a mixed gas of hydrogen + oxygen (H ₂ + O ₂ ) for about 160 minutes at a high temperature of 1000 ° C., The field oxide film 61 is formed and the nitride film pattern is removed. At this time, the field oxide film is formed to a thickness of about 0.7 mu m.

Through this process, the field region and the active region are defined, and the region where the nitride film pattern is formed is an active layer, and gate, source, and drain are formed in a subsequent process.

Next, as shown in FIG. 10, the surface of the exposed substrate, which is in contact with the well region 22 and the drift region 23, is subjected to a mixed gas of hydrogen + oxygen (H ₂ + O ₂ ) at a high temperature of 900 ° C. for about 20 to 60 minutes. Thermal oxidation is performed to form a gate oxide film 62. At this time, the thickness of the oxide film is about 200 kPa to 500 kPa.

Next, as shown in FIG. 11, polysilicon was applied on the entire surface of the substrate at about 600 ° C. by low pressure chemical vapor deposition (LPCVD) at about 3500 kPa, and then patterned by photolithography to form the well region 22 and the drift region 23. A gate 25 having a predetermined width is formed on the upper side of the gate.

Next, as shown in FIG. 12, the drift region 23 exposed by the diffusion film 61 is etched by reactive ion etching (RIE) to form a trench having a depth of 2 μm and a width of 2 μm.

Next, as shown in FIG. 13, phosphorus is ion-implanted into the trenches of the well region 22 and the drifting region 23 exposed to form the source / drain, and boron is added to the well region 22 in a number of 10, respectively. ¹⁵ / cm ² or more and heat treatment at 900 ° C. for 30 minutes or more to form drain 26 of n ⁺ and well guide window 27 of source 24 and p ⁺ , respectively. In this case, when implanting dopants into the trench, vertical and tilted ions are implanted using an ion implanter, and the surface concentration thereof is 10 10 ¹⁹ or more, and the junction depth is 0.3 µm to 0.5 µm. .

Next, as shown in FIG. 14, a boron phosphorus containing silicon oxide film (BPSG: B 2.7%, P 5.7% SiO2) at 380 ° C by plasma enhanced chemical vapor deposition (PECVD) to insulate the gate 25 on the front surface of the substrate. ) 62 is further applied about 1 μm, and then the oxide layers 62, 61, and 60 are selectively etched using a reactive ion etcher (RIE) to expose the source 24, the gate 25, and the drain 26.

Next, as shown in FIG. 15, to form metal terminals of the source / drain and the gate, platinum (Pt) is first deposited on the entire surface of the substrate and then heat treated at 460 ° C. for 30 minutes to form platinum silicide (PtSi). Next, TiW having a thickness of 2200 μs, Al having 1 μm to 2 μm and containing 1% of Si and 0.5% of Cu and TiW having a thickness of 1000 μs were sequentially deposited, and then selectively patterned to form a gate and a source. A metal terminal of the drain is formed, and the alloy is finally heat treated at 400 ° C. for 30 minutes. This platinum silicide reduces the electrical resistance with the contact metal, the next layer TiW promotes filling inside the trench bends, and the middle layer Al serves as the main conductor. In addition, the upper TiW not only facilitates patterning by acting as an anti-reflection film during Al exposure, but also when Al-layer metal wiring is required, when Al interlayer insulation is etched (this is referred to as "via etching" in a semiconductor process). ) It acts as an etch protection film for the lower Al layer, enabling stable multi-layer metal wiring.

In the present invention, as shown in Fig. 2, the drain structure is not formed on the semiconductor surface, but is deeply dug into the semiconductor, that is, the trench structure commonly referred to in the semiconductor process is formed, and then the dopant is doped in the trench. The inside is finally filled with the drain connection wiring metal terminal material.

The drain of this trench structure is a three-dimensional structure. When the channel electrons reach the drain, the flow of electrons is vertically dispersed to the vertical depth where the electric field is weaker than the edge of the drain surface, thereby suppressing the impact ionization phenomenon. Drain voltage breakdown is improved.

In addition, the advantage of the device of the present invention is that the buried drain connection metal terminal has a much higher thermal conductivity than the conventional semiconductor material, so that it is easy to dissipate heat generated in the drain region, thereby improving reliability during device operation. Can be.

Claims (2)

A well region and a drifting region in contact with each other on a semiconductor substrate; a source is formed in the well region; a drain is formed in the drifting region; and a predetermined region is formed through an oxide film over the upper region of the well region and the drifting region. In a LDMOS type high voltage device in which a gate having a width is formed, The drain has a trench structure formed to a predetermined depth from the surface of the drift region formed by etching to a predetermined depth and width, And a drain connection wiring metal terminal formed in contact with the drain surface to fill the trench. The method of claim 1, The drain connection wiring metal terminal has a structure in which platinum silicide (PtSi), TiW, Al, and TiW are sequentially stacked.

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