TWI470797B - Power transistor with protected channel - Google Patents

Description

Power transistor with protective channel

The present invention relates to a semiconductor device.

A voltage regulator such as a DC-DC converter is used to provide a stable voltage source for the electronic system. A switching voltage regulator (or simply "switching regulator") is known as an efficient DC-DC converter. The switching regulator generates an output voltage by converting the input DC voltage into a high frequency voltage signal, and generates an output DC voltage by filtering the high frequency input voltage signal. In particular, the switching regulator includes a switch for alternately coupling or eliminating coupling between an input DC voltage source (such as a battery) and a load (such as an integrated circuit). An output filter, typically including an inducer and a capacitor, is coupled between the input voltage source and the load to filter the output of the converter and thereby provide an output DC voltage. A controller, such as a pulse width modulator or a pulse frequency modulator, controls the exchanger to maintain a substantially constant output DC voltage.

Due to the performance measurement of the laterally diffused gold-oxide half (LDMOS) transistor in terms of characteristic on-resistance (R _dson ) and drain-to-source breakdown voltage (BV _{d_s} ), it can be used for conversion regulators. The on-resistance (R _dson ) and the long-term reliability of the device are another performance trade-off.

Referring to Fig. 1, a conventional LDMOS transistor 300 includes a p-type substrate 302 in which a high voltage n-well (HV n-well) 304 is formed. The HV n-well has an n-doped n+ region 312, a p-doped p+ region 314 and a p-doped p-body diffusion region (p-body) 316 source region 310, n-doped n+ region 322 A drain region 320 with a lighter doped n-type doped drain (NDD) 324, and a gate 330 with a gate oxide layer 332 and a polysilicon layer 334.

In conventional LDMOS designs, the high drain voltage potential is supported by the formation of a depletion region such that the region 340 between the n+ region 322 and the HV n-well 304 in the NDD below the gate 330 experiences the maximum electric field. Since region 340 is in the current path when conducting, a considerable degree of engineering effort has been made to reduce this high resistance region. However, reducing the high resistance region will further increase the electric field gradient and cause high collision liberation rates. Therefore, in the conventional LDMOS design, the area 340 is where the device collapses when it is turned off.

When region 340 collapses, this region 340 produces a large number of holes and electrons. These carriers are easily trapped in the gate oxide layer on the drain side of the device due to high energy, resulting in deterioration of the inherent characteristics of the device and affecting long-term reliability, such as a decrease in on-resistance of a field effect transistor (FET). One technique to avoid internal collapse of the power LDMOS device is to provide a second device with a small breakdown voltage in parallel with the LDMOS device to forcibly limit the gate voltage of the LDMOS device. But this approach requires more complex systems, more component counts, and higher costs.

In one aspect, the transistor comprises a p-type substrate having a p-type body, an n-well formed on the substrate, a source formed in the n-well, a drain formed in the n-well and separated from the source a channel region and a gate for supplying current from the drain to the source, for controlling the channel formation and the collapse region of the channel region between the source and the drain, and the high voltage n-well outside the channel region. The source includes a p-doped p-body, a p-doped p+ region in the p-body, and a first n-doped n+ region in the p-body. The drain includes a second n-doped n+ region. The collapse zone is located between the p-body and the p-body of the substrate. The channel zone has an internal breakdown voltage, and the collapse zone has an external collapse voltage that is less than the internal breakdown voltage.

In another aspect, the transistor comprises a p-type substrate having a p-type body, an n-well formed on the substrate, a source formed in the n-well, a germanium formed in the n-well and separated from the source A channel, a gate for supplying current from the drain to the source, a channel for forming a channel region between the source and the drain, and a collapse region, and a high-voltage n-well outside the channel region. The source includes a p-doped p-body, a p-doped p+ region in the p-body, and a first n-doped n+ region in the p-body. The drain includes a second n-doped n+ region. The collapse zone is located between the second n-doped n+ region and the p-type body of the substrate. The channel zone has an internal breakdown voltage, and the collapse zone has an external collapse voltage that is less than the internal breakdown voltage.

Embodiments of any of the above aspects may include one or more of the following features. The field oxide on the substrate can extend around the n-well and over a portion of the n-well. The field oxide can extend across a portion of the p-body. The drain may include an n-doped region that surrounds the second n-doped n+ region and is lighter doped. The field oxide can extend across a portion of the n-doped region. The first n-doped n+ region may be adjacent to the p+ region. The channel may extend along a first direction, the collapse zone extending in a second direction that is perpendicular to the first direction. The internal breakdown voltage is no more than about 10% greater than the external breakdown voltage. The internal breakdown voltage is approximately 1-2 volts than the external breakdown voltage. The drain may be a dispersed drain having a plurality of drain regions each including a second n-doped n+ region, and the gate may include a plurality of gate lines for controlling a plurality of sources between the source and the drain Vacant area. The source may be a decentralized source having a plurality of source regions each including a p-body, a p+ region, and a second n-doped n+ region, and the gate may include a plurality of gate lines for controlling the source A number of empty areas between the district and the bungee.

In still another aspect, the transistor includes a substrate, a well formed on the substrate, a drain, including a first impurity region, a source, and a second impurity region implanted in the well, and the first impurity The cells are separated by a channel for supplying current from the drain to the source, and a gate for controlling the depletion region between the source and the drain. The channel has an internal breakdown voltage, and the well, drain and source are configured to provide an external breakdown voltage that is less than the internal breakdown voltage, allowing the collapse to occur in a collapse zone located outside the channel and adjacent to the well of the drain or source.

Embodiments may include one or more of the following features. The drain may be a dispersed drain, having a plurality of drain regions each including a first impurity region, the source may be a distributed source, and having a plurality of source regions each including a second impurity region, the gate may include A plurality of gate lines are used to control a plurality of depletion zones between the source region and the drain region. A plurality of drains and a plurality of sources may be arranged in a plurality of rows and columns. Each row may extend along a first direction, and a collapse zone in the high pressure well may extend in a second direction that is perpendicular to the first direction. The collapse zone in the well can be located at the end of each rank. The drain may be a dispersed drain having a plurality of drain regions each including a first impurity region, and the gate may include a plurality of gate lines for controlling a plurality of depletion regions between the source and drain regions. The source may be a decentralized source having a plurality of source regions each including a second impurity region, and the gate may include a plurality of gate lines for controlling a plurality of depletion regions between the source region and the drain. The substrate can be a p-type substrate and the well can be an n-type well. The first impurity region may be an n-doped n+ region, and the second impurity region is an n-doped n+ region. The source can include a p-doped p+ region. The source may include a p-doped p-body, a first impurity region, and a p-doped p+ region formed in the p-body. The collapse zone in the high pressure well can be adjacent to the p-body. The drain may include an n-doped region that surrounds the second n-doped n+ region and is lighter doped. The field oxide on the substrate can extend around the n-well and over a portion of the p-body. The field oxide on the substrate can surround the high pressure well and extend across a portion of the high pressure well. The internal breakdown voltage is no more than about 10% greater than the external breakdown voltage. The internal breakdown voltage is approximately 1-2 volts than the external breakdown voltage. The gate may include a first conductive region and a second conductive region electrically isolated and independently biased from the first conductive region, the first conductive region controls channel formation on the p-body of the source, and the second conductive region controls the interior The potential of the collapse zone.

In still another aspect, a method of fabricating a transistor includes selecting a size and concentration of an impurity region in a source and a drain of the transistor, selecting an n-well concentration of the n-well, and a source and a drain are formed in the n- In the well, select the distance between the source and the bucking impurity interval, the size, concentration, distance, and n-well concentration, determine the internal breakdown voltage of the channel between the source and the drain, and select the portion that extends beyond the source. The width of the n-well causes the external collapse voltage of some of the n-wells to be less than the internal collapse voltage.

Embodiments may include one or more of the following features. The substrate can be implanted with an impurity region of selected size and concentration, and implanted with an n-well having a selected n-well concentration and width.

Embodiments may include one or more of the following features. When a crash occurs, the electron hole pair generated by the collision free can be far from the internal channel area. As such, the FET on-resistance does not need to be reduced due to sudden collapse. This method does not sacrifice important shackles.

One or more embodiments will be described in detail below in conjunction with the drawings. Other features, objects, and advantages will be apparent from the description and appended claims.

In general, this article is about power devices with inherent self-protection capabilities. That is, the device is designed such that when a crash occurs, the electron hole pair generated by the collision free will be away from the internal channel region (the direct current path from the n+ region of the drain to the n+/p+ region of the source).

In general, power devices are the fact that power LDMOS is not a one-dimensional application. In particular, the device can be designed to have the channel follow a first path (eg, along a first direction) and collapse in a second direction (eg, along a second, vertical direction).

FIG. 2 is a plan view of the LDMOS device 100. The LDMOS transistor 100 includes a P-type substrate 102 in which a high voltage n-well (HV n-well) 104 is formed. The HV n-well has a source region 110 and a drain region 120 separated by a gate 130. The length LS of the source region 110 extending along the gate is greater than the width WS of its vertical direction. Similarly, the length LD of the drain region 120 extending along the gate is greater than the width WD of its vertical direction. The size can be calculated from the boundary of the heavily doped region.

The source region 110 and the drain region 120 may be arranged in a plurality of rows and columns, and each row and column is separated by a gate 130. Although only one drain region 120 is shown, more than one of the drain regions 120 may be repeatedly arranged in the pattern. Similarly, although only the two source regions 110 are shown, the pattern may be repeatedly arranged with two or more source regions 110. Also, the opposite side of the single source region 110 can be configured with the second drain region 120. In operation, current flows from the drain to the source (as indicated by the arrow) via a channel extending along the length of the gate. In some embodiments, the length of the source region is equal to the length of the drain region.

Figure 3A is a cross-sectional view parallel to the width of the source and drain regions. Each gate 130 includes a gate oxide layer 132 and a conductive layer 134 (eg, a polysilicon layer) on the gate oxide layer 132. In some embodiments, the gate oxide layer includes a thicker region proximate to the adjacent drain region 120 and a thinner region proximate the adjacent source region 110. Each gate is connected to a common control voltage.

The source region 110 includes an n-doped n+ region 112, a p-doped p+ region 114, and a p-doped p-body diffusion region (p-body) 116. The p-body 116 surrounds the n+ region 112 and the p+ region 114. The n+ region 112 is adjacent to the p+ region 114, and the n+ region is adjacent to the drain region 120. The impurity concentration of the p-body 116 is lower than the p+ region 114. The p-body 116 and the n+ region 112 (as in the oblique region implanted in front of the oxide sidewall) extend below the gate oxide layer 132, and the p-body extends further than the n+ region. The contact pads 136 of the upper metal layer (see FIG. 2) are electrically connected to the n+ region 112 and the p+ region 114. In some embodiments, the individual contact pads simultaneously contact the n+ region 112 and the p+ region 114.

The drain region 120 includes an n-doped n+ region 122 and a lighter doped n-type doped drain (NDD) 124. NDD 124 surrounds n+ region 122. NDD extends below the gate oxide layer 132. The contact pads 138 of the upper metal layer (see FIG. 2) are electrically connected to the n+ region 122.

The impurity concentration of the HV n-well 104 is lower than the n+ regions 112, 122 and the NDD 124.

Figure 3B is a partial cross-sectional view parallel to the source length, for example parallel to the gate line passing through the p+ region 114. The p-body 116 extends further in the direction of the parallel gate line than the p+ region 114. Likewise, the HVn-well 104 extends further in the direction of the parallel gate line than the p-body 116.

A portion of the substrate outside the active region is covered by field oxide 150. The p-body 116 and the HV n-well 104 extend below the field oxide 150 adjacent the source region 110. Field oxide 150 can completely enclose HV n-well 104. Although not shown, the conductive contacts may be placed in direct contact with the p-type substrate 102 to serve as a substrate electrode further from the field oxide 150.

As shown, the termination region 140 includes a portion of the HV n-well 104 that is sandwiched between the p-body 116 and the p-type substrate 102. Since it is located on the side of the source region 110 (opposite the edge of the gate 130), this region is not considered a channel.

Figure 3C is a partial cross-sectional view parallel to the length of the drain, for example parallel to the gate line passing through the n+ region 122. The NDD 124 extends further in the direction of the parallel gate line than the n+ region 122. Likewise, HVn-well 104 extends further away from NDD 124 in the direction of the parallel gate line.

As noted above, a portion of the substrate outside the active region is covered by field oxide 150. NDD 124 and HV n-well 104 extend below field oxide 150 adjacent to drain region 120.

As shown, the termination region 142 includes a portion of the HV n-well 104 that is sandwiched between the NDD 124 and the p-type substrate 102. Since it is located on the side of the drain region 120 (opposite the edge of the gate 130), this region is not considered a channel.

The device is designed such that the external collapse voltage from the drain to the body (such as the p-body from the body to the substrate along the 3B-3B section) is slightly smaller than the internal breakdown voltage of the device (eg, along the 3A-3A section, through the channel) . The width (WHV) of the HV n-well 104 between the p-body 116 and the p-type substrate 102, and the concentration of the different impurity regions may be selected such that the breakdown voltage of the termination region 140 is less than the breakdown voltage of the channel. Alternatively or in addition, the width (WHV) of the HV n-well 104 between the NDD 124 and the p-type substrate 102, and the concentration of the different impurity regions may be selected such that the breakdown voltage of the termination region 142 is less than the breakdown voltage of the channel, such that the external breakdown voltage (eg, along the 3C-3C section, the p-type body from the NDD to the substrate) is slightly less than the internal breakdown voltage of the device. Thus, when a crash occurs, the pair of electron holes generated by the collision free will be far from the internal channel area. Therefore, the FET on-resistance is no longer reduced by sudden collapse.

In addition, although the 3B and 3C diagrams show that the collapse regions 140, 142 are respectively disposed on the source and drain sides as the outermost source or drain region in the array, and the vertical gate line is disposed, the collapse region can also be formed. On the source or drain side, it is configured with parallel gate lines 134, but further away from the gates and associated channels.

According to the primary evaluation, the breakdown voltage difference (ΔBV) between the external path and the internal path can be determined by the product of the maximum current of the crash event and the series resistance of the external collapse path. The breakdown voltage difference (ΔBV) can be chosen to be less than 10% of the external breakdown voltage. For example, if the device has a breakdown voltage of about 30 volts, the concentration and size of the implanted region can be selected to have an external collapse voltage of about 30 volts and an internal breakdown voltage of about 32 volts. This new device design approach achieves the device's self-protection, although it slightly loses the ΔBV (1-2 volts) of the breakdown voltage value, but does not sacrifice important 矽 area.

An example of a method for achieving an internal and external breakdown voltage difference will be described below. With the well-known power LDMOS design, the internal breakdown voltage can be adjusted to a predetermined crash value. The external collapse voltage of this particular device structure can be adjusted to a predetermined breakdown voltage minus the value of ΔBV by varying the high voltage n-well width placed between the p-type regions of the same potential.

FIG. 4 illustrates another embodiment in which each gate 130 includes two electrically isolated gates 130a, 130b that are biased at different potentials. Each of the gates 130a, 130b includes a gate oxide layer 132 and a conductive layer 134 (eg, a polysilicon layer) on the gate oxide layer 132. The gates 130a, 130b may extend in parallel. A gate 130a adjacent to the source region 110 is disposed on a portion of the p-body 116 that protrudes from the n+ region 112, and channel formation can be controlled by the p-body 116. A gate 130b adjacent to the drain is provided on a portion of the NDD 124 extending beyond the n+ region 122 and the remaining channel portion (which may be undoped except for the HVn-well 104) to control the voltage potential of the internal collapse region. Therefore, the voltage on the gates 130a, 130b can be selected to select the breakdown voltage value and the collapse location.

The present invention has been disclosed above in some embodiments. It is to be understood that various changes and modifications may be made without departing from the spirit and scope of the invention. For example, although a p-type body and a p-type substrate are described herein, the p-type substrate can be replaced by other p-type implants that are available. Therefore, other embodiments are also within the scope defined by the scope of the appended claims.

100. . . Transistor

102. . . Substrate

104. . . well

110. . . Source area

112, 114, 122. . . region

116. . . main body

120. . . Bungee area

124. . . Bungee

130, 130a, 130b. . . Gate

132. . . Gate oxide layer

134. . . Conductive layer

136, 138. . . Contact pad

140, 142. . . Termination area/crash area

150. . . Field oxide

300. . . Transistor

302. . . Substrate

304. . . well

310. . . Source area

312, 314, 322, 340. . . region

320. . . Bungee area

324. . . Bungee

330. . . Gate

332. . . Gate oxide layer

334. . . Polycrystalline layer

Figure 1 is a cross-sectional view of a conventional LDMOS transistor.

Figure 2 is a plan view of one embodiment of an LDMOS transistor.

3A, 3B, and 3C are cross-sectional views of the LDMOS transistor of Fig. 2.

Figure 4 is a cross-sectional view of another embodiment of an LDMOS transistor.

The same element symbols in the various figures represent similar elements.

102. . . Substrate

104. . . well

110. . . Source area

112, 114, 122. . . region

116. . . main body

120. . . Bungee area

124. . . Bungee

130. . . Gate

134. . . Conductive layer

136, 138. . . Contact pad

Claims (55)

A transistor comprising: a p-type substrate having a p-type body; an n-well formed in the substrate; a source formed in the n-well and comprising: a p-doped p- a body; a p-doped p+ region located within the p-body; and a first n-doped n+ region located within the p-body; a drain formed in the n-well and with the source Separated, the drain includes a second n-doped n+ region; a channel region for current to flow from the drain to the source, the channel region having an intrinsic breakdown voltage; a gate, Forming a channel for controlling the channel region between the source and the drain; and a collapse region located outside the channel region and between the p-body and the p-body of the substrate In the n-well, the doping and dimensions of the collapse zone and the channel zone are designed such that an extrinsic breakdown voltage of the collapse zone is less than the internal breakdown voltage. The transistor of claim 1, further comprising a field oxide on the substrate and surrounding the n-well and extending over a portion of the n-well. The transistor of claim 2, wherein the field oxide extends over a portion of the p-body. The transistor of claim 1, wherein the internal breakdown voltage is no more than about 10% greater than the external breakdown voltage. The transistor of claim 1, wherein the internal breakdown voltage is about 1-2 volts greater than the external breakdown voltage. The transistor of claim 1, wherein the drain includes an n-doped region surrounding the second n-doped n+ region and than the second n-doped n+ region Doped in a smaller amount. The transistor of claim 1, wherein the first n-doped n+ region abuts the p+ region. The transistor of claim 1, wherein the channel region extends along a first direction, the collapse region extending along a second direction perpendicular to the first direction. The transistor of claim 1, wherein the germanium is a decentralized drain having a plurality of drain regions each including the second n-doped n+ region, and the gate includes a plurality of gates a line for controlling a plurality of depletion regions between the source and the drain regions. The transistor of claim 1, wherein the source is a decentralized source having a plurality of source regions each including the p-body, the p+ region, and the first n-doped n+ region And the gate includes a plurality of gate lines for controlling a plurality of depletion regions between the source regions and the drain. A transistor comprising: a p-type substrate having a p-type body; an n-well formed in the substrate; a source formed in the n-well and comprising: a p-doped p- a body; a p-doped p+ region located within the p-body; and a first n-doped n+ region located within the p-body; a drain formed in the n-well and with the source Separated, the drain includes a second n-doped n+ region; a channel region for current flow from the drain to the source, the channel region having an internal breakdown voltage; and a gate for controlling the location Forming a channel in the channel region between the source and the drain; and a collapse region located outside the channel region and between the second n-doped n+ region and the p-type body of the substrate In the n-well, the doping and size design of the collapse zone and the channel zone may cause an external collapse voltage of the collapse zone to be smaller than the internal breakdown voltage. The transistor of claim 11, wherein the internal breakdown voltage is no more than about 10% greater than the external breakdown voltage. The transistor of claim 11, wherein the internal breakdown voltage is about 1-2 volts greater than the extraneous breakdown voltage. The transistor of claim 11, further comprising a field oxide on the substrate and surrounding the n-well and extending over a portion of the n-well. The transistor of claim 14, wherein the drain includes an n-doped region surrounding the second n-doped n+ region and than the second n-doped n+ region Doped in a smaller amount. The transistor of claim 15 wherein the field oxide extends over a portion of the n-doped region. The transistor of claim 11, wherein the first n-doped n+ region is adjacent to the p+ region. The transistor of claim 11, wherein the channel region extends along a first direction, the collapse region extending along a second direction perpendicular to the first direction. The transistor of claim 11, wherein the germanium is a decentralized drain having a plurality of drain regions each including the second n-doped n+ region, and the gate includes a plurality of gates a line for controlling a plurality of depletion regions between the source and the drain regions. The transistor of claim 11, wherein the source is a decentralized source having a plurality of source regions each including the p-body, the p+ region, and the first n-doped n+ region And the gate includes a plurality of gate lines for controlling a plurality of depletion regions between the source regions and the drain. A transistor comprising: a substrate; a well formed in the substrate; a drain comprising a first impurity region implanted in the well; a source comprising implanted in the well and a second impurity region separated by a first impurity region; a channel for supplying current from the drain to the source, the channel having an internal breakdown voltage; and a gate for controlling the source and the gate a depletion zone between the poles; in the collapse zone, the collapse zone is in the well, the collapse zone in the well being located outside the channel and adjacent to the drain or the source, wherein the well, the bungee and The source is doped and sized to cause the collapse zone An extraneous breakdown voltage is less than the internal collapse voltage so that the collapse occurs in the collapse zone located outside the channel and adjacent to the drain or the source. The transistor of claim 21, wherein the germanium is a decentralized drain having a plurality of drain regions each including the first impurity region, the source being a decentralized source having a plurality of Each of the source regions of the second impurity region is included, and the gate includes a plurality of gate lines for controlling a plurality of depletion regions between the source regions and the drain regions. The transistor of claim 22, wherein the plurality of drain regions and the plurality of source regions are arranged in an alternating row. The transistor of claim 23, wherein the columns extend along a first direction, the collapse region extending along a second direction perpendicular to the first direction. The transistor of claim 23, wherein the collapse zone in the well is at an end of the columns. The transistor of claim 21, wherein the crucible is a decentralized drain having a plurality of respective first impurity regions. a drain region, and the gate includes a plurality of gate lines for controlling a plurality of depletion regions between the source and the drain regions. The transistor of claim 21, wherein the source is a decentralized source having a plurality of source regions each including the second impurity region, and the gate includes a plurality of gate lines for A plurality of depletion regions between the source regions and the drain are controlled. The transistor of claim 21, wherein the substrate is a p-type substrate, and the well is an n-type well. The transistor of claim 28, wherein the first impurity region is a first n-doped n+ region, and the second impurity region is a second n-doped n+ region. The transistor of claim 29, wherein the source comprises a p-doped p+ region. The transistor of claim 30, wherein the source comprises a p-doped p-body, and the second impurity region and the p-doped p+ region are formed in the p-body. The transistor of claim 31, wherein the collapse zone is adjacent to the p-body. The transistor of claim 31, wherein the drain includes an n-doped region surrounding the first n-doped n+ region and than the first n-doped n+ region Doped in a smaller amount. The transistor of claim 31, further comprising a field oxide, located on the substrate and surrounding the n-well and extending over a portion of the p-body. The transistor of claim 21, further comprising a field oxide, located on the substrate and surrounding the well and extending over a portion of the well. The transistor of claim 21, wherein the internal breakdown voltage is no more than about 10% greater than the external breakdown voltage. The transistor of claim 21, wherein the internal breakdown voltage is about 1-2 volts greater than the extraneous breakdown voltage. The transistor of claim 21, wherein the gate comprises a first conductive region and a second conductive region electrically isolated from the first conductive region, the first conductive region is controlled A channel is formed on a p-body in the source, the second conductive region controlling a potential in an area where the interior collapses. A method of fabricating a transistor comprising the steps of: selecting a size and concentration of an impurity region for a source and a drain of the transistor; selecting an n-well concentration of an n-well, The source and the drain will be formed in the n-well; a distance between the source and the impurity regions of the drain is selected; from the dimensions, the concentrations, the distance, and the n-well a concentration to determine an internal collapse voltage of a channel region between the source and the drain; and selecting a width of the n-well extending across a portion of the source to provide a The internal breakdown voltage is small for an alien crash voltage of that portion of the n-well. The method of claim 39, further comprising the steps of: (i) implanting the substrate into the impurity regions having the selected size and concentration, and (ii) implanting the substrate The n-well having the selected n-well concentration and width. The method of claim 40, wherein the substrate has a p-type body, and the step of implanting the substrate into the impurity regions comprises the steps of: (i) implanting in a source region a p-doped p-body, (ii) implanting a p-doped p+ region in the p-body, (iii) implanting a first n-doped n+ region in the p-body, and (iv) planting in a bungee area Into a second n-doped n+ region. The method of claim 41, wherein the n-well is located outside the channel region and between the p-body and the p-body of the substrate. The method of claim 41, wherein the n-well is located outside the channel region and between the second n-doped n+ region and the p-body of the substrate. The method of claim 41, comprising the step of forming a gate to control channel formation in the channel region between the source and the drain. The method of claim 41, comprising the step of depositing a layer of oxide on the substrate and surrounding the n-well and extending over a portion of the n-well. The method of claim 45, wherein the field oxide is deposited to extend over a portion of the p-body. The method of claim 44, wherein the step of implanting the substrate into the impurity regions comprises the steps of: (i) forming the drain as if there are a plurality of drain regions each including a first impurity region Decentralized a drain, and (ii) forming the source as a decentralized source having a plurality of source regions each including a second impurity region, and the step of forming the gate includes the steps of: forming a plurality of gate lines, To control a plurality of depletion regions located between the source regions and the drain regions. The method of claim 47, comprising the steps of: forming the plurality of bungee regions arranged in a staggered column and the plurality of source regions. The method of claim 48, wherein the columns extend along a first direction and the n-well of the portion extends along a second direction perpendicular to the first direction. The method of claim 48, wherein the n-well of the portion is at one end of the columns. The method of claim 41, wherein the step of implanting the substrate into the impurity regions comprises the step of implanting an n-doped region in the drain, the n-doped region surrounding the first The n-doped n+ region is doped a little less than the second n-doped n+ region. The method of claim 51, wherein the first n-doped n+ region is deposited to adjoin the p+ region. The method of claim 41, comprising the step of implanting the impurity regions such that the channel region extends along a first direction and the portion is along a direction perpendicular to the first direction Extending in the second direction. The method of claim 39, wherein the selection of the dimensions, the concentrations, the distances, and the widths causes the internal collapse voltage to be no more than about 10% greater than the extraneous breakdown voltage. The method of claim 39, wherein the selection of the dimensions, the concentrations, the distances, and the width causes the internal breakdown voltage to be about 1-2 volts greater than the extraneous breakdown voltage.