KR100249631B1 - 데이터 처리장치 - Google Patents

데이터 처리장치 Download PDF

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Publication number
KR100249631B1
KR100249631B1 KR1019970033526A KR19970033526A KR100249631B1 KR 100249631 B1 KR100249631 B1 KR 100249631B1 KR 1019970033526 A KR1019970033526 A KR 1019970033526A KR 19970033526 A KR19970033526 A KR 19970033526A KR 100249631 B1 KR100249631 B1 KR 100249631B1
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KR
South Korea
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access
register
information
bit
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Expired - Fee Related
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KR1019970033526A
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English (en)
Korean (ko)
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KR19980069845A (ko
Inventor
토시유키 마루야마
마사히토 마츠오
Original Assignee
다니구찌 이찌로오
미쓰비시덴키 가부시키가이샤
기타오카 다카시
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Application filed by 다니구찌 이찌로오, 미쓰비시덴키 가부시키가이샤, 기타오카 다카시 filed Critical 다니구찌 이찌로오
Publication of KR19980069845A publication Critical patent/KR19980069845A/ko
Application granted granted Critical
Publication of KR100249631B1 publication Critical patent/KR100249631B1/ko
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G06F9/3552—Indexed addressing using wraparound, e.g. modulo or circular addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Executing Machine-Instructions (AREA)
  • Information Transfer Systems (AREA)
  • Advance Control (AREA)
KR1019970033526A 1997-02-19 1997-07-18 데이터 처리장치 Expired - Fee Related KR100249631B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP34960 1997-02-19
JP03496097A JP3789583B2 (ja) 1997-02-19 1997-02-19 データ処理装置

Publications (2)

Publication Number Publication Date
KR19980069845A KR19980069845A (ko) 1998-10-26
KR100249631B1 true KR100249631B1 (ko) 2000-03-15

Family

ID=12428726

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970033526A Expired - Fee Related KR100249631B1 (ko) 1997-02-19 1997-07-18 데이터 처리장치

Country Status (4)

Country Link
US (1) US5924114A (enExample)
JP (1) JP3789583B2 (enExample)
KR (1) KR100249631B1 (enExample)
DE (1) DE19738542A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7032100B1 (en) * 1999-12-17 2006-04-18 Koninklijke Philips Electronics N.V. Simple algorithmic cryptography engine
GB2363869B (en) * 2000-06-20 2004-06-23 Element 14 Inc Register addressing
US6647484B1 (en) * 2000-09-19 2003-11-11 3 Dsp Corporation Transpose address mode in general purpose DSP processor
GB2371641B (en) * 2001-01-27 2004-10-06 Mitel Semiconductor Ltd Direct memory access controller for circular buffers
JP3856737B2 (ja) * 2002-07-19 2006-12-13 株式会社ルネサステクノロジ データ処理装置
US20070094663A1 (en) * 2005-10-25 2007-04-26 Anbarani Hossein A Flexible ordered execution mechanism for multi-threaded processors
JP4973154B2 (ja) * 2006-11-29 2012-07-11 ヤマハ株式会社 演算処理装置、メモリアクセス方法、及びプログラム
US9325625B2 (en) 2010-01-08 2016-04-26 Citrix Systems, Inc. Mobile broadband packet switched traffic optimization
US8560552B2 (en) * 2010-01-08 2013-10-15 Sycamore Networks, Inc. Method for lossless data reduction of redundant patterns
US8514697B2 (en) * 2010-01-08 2013-08-20 Sycamore Networks, Inc. Mobile broadband packet switched traffic optimization
US20120185741A1 (en) * 2011-01-14 2012-07-19 Sergey Sergeevich Grekhov Apparatus and method for detecting a memory access error
US8502710B2 (en) * 2011-09-13 2013-08-06 BlueStripe Software, Inc. Methods and computer program products for providing a compressed circular buffer for efficient storage of network performance data
US9348558B2 (en) * 2013-08-23 2016-05-24 Texas Instruments Deutschland Gmbh Processor with efficient arithmetic units
US9478312B1 (en) 2014-12-23 2016-10-25 Amazon Technologies, Inc. Address circuit
US10180829B2 (en) * 2015-12-15 2019-01-15 Nxp Usa, Inc. System and method for modulo addressing vectorization with invariant code motion

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4908748A (en) * 1987-07-28 1990-03-13 Texas Instruments Incorporated Data processing device with parallel circular addressing hardware
US5623621A (en) * 1990-11-02 1997-04-22 Analog Devices, Inc. Apparatus for generating target addresses within a circular buffer including a register for storing position and size of the circular buffer
US5463749A (en) * 1993-01-13 1995-10-31 Dsp Semiconductors Ltd Simplified cyclical buffer

Also Published As

Publication number Publication date
DE19738542A1 (de) 1998-08-27
KR19980069845A (ko) 1998-10-26
US5924114A (en) 1999-07-13
JP3789583B2 (ja) 2006-06-28
JPH10232821A (ja) 1998-09-02

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