KR100248121B1 - Thin film transistor and method of fabricating the same - Google Patents

Abstract

The present invention relates to a thin film transistor and a method of manufacturing the same, and includes a source / drain electrode and a first gate electrode formed at predetermined intervals on a substrate, and a contact hole covering the first gate electrode on the substrate and exposing the source / drain electrode. A buffer oxide film formed on the buffer oxide film, an active layer formed on the buffer oxide film, and having a source region, an offset region, a channel region, an offset region, and a drain region, and a second gate electrode formed on the active layer with a gate insulating film interposed therebetween. Have

A method of manufacturing the thin film transistor of the present invention having the above structure comprises the steps of: first forming a source / drain electrode and a first gate electrode on a substrate at a predetermined interval, and covering the first gate electrode on the substrate, wherein the source / drain is covered. An intervening step of forming a buffered oxide film formed by each contact hole exposing the electrode, forming a second gate electrode on which the active layer and the gate oxide film are resumed on the buffered oxide film, and using the second gate electrode as a mask. And a process of forming a source / drain region doped with impurities and a field reduction region and a channel region not doped with impurities on the active layer.

Accordingly, in the present invention, the first gate electrode is added to control the off current and to increase the on current.

Description

Thin Film Transistor and Manufacturing Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) and a manufacturing method thereof, and more particularly, to a thin film transistor suitable for controlling off current and a manufacturing method thereof.

Generally, thin film transistors formed in liquid crystal display devices use amorphous silicon until now, but when polycrystalline silicon having high mobility of electrons or electrons is used compared to amorphous silicon, it is not necessary to attach a separate driving circuit on the panel. It is increasingly being replaced by polycrystalline silicon.

Therefore, instead of connecting by driving circuit IC bonding, a large portion of the driving circuit may be formed of a thin film transistor to be manufactured simultaneously with the thin film transistor formed in the pixel portion.

In addition, a liquid crystal display device using a polysilicon thin film transistor has a structure in which a driving circuit portion and a pixel portion are embedded on a glass substrate. The thin film transistor of the driving circuit portion can switch at a high frequency due to the characteristics of the polycrystalline silicon.

At this time, in terms of switching operation, the transistor is generally controlled to two conducting states, which can be referred to as an "on" state and an "off" state, and a short circuit when the switch is closed, that is, when the off current is present. In addition, it appears as an open circuit when it is open, i.e. when it is on-current. It is desirable that the device does not take much time to switch from one state to another between these states.

However, as the pixel switching thin film transistor in the pixel portion has a large drain current value in the off state, the operation thereof is disturbed. Therefore, in the pixel portion, a lightly doped drain is used to reduce the level of the off current to an appropriate level. A thin film transistor adopting a structure, an offset structure, a dual gate structure, or the like has been conventionally proposed.

1 is a cross-sectional view of a thin film transistor having an offset structure according to a first embodiment according to the prior art, and FIGS. 2A to 2C are manufacturing process diagrams of a thin film transistor having an offset structure according to the prior art.

Referring to FIG. 1, the thin film transistor according to the first embodiment of the present invention has source and drain electrodes 104 and 104 formed on the insulating substrate 100 at predetermined intervals, and the source / drain electrodes 102 ( 104 and an active layer 106 covering therebetween are formed.

The gate electrode 110 formed of the gate insulating film 108 is positioned on the active layer at a predetermined portion corresponding to the source / drain electrodes 102 and 104. A channel region 106-1 is formed in the active layer of the portion corresponding to the gate electrode, between the channel region 106-1 and the source electrode 102, and between the channel region 106-1 and the drain electrode 104. Offset regions 106-2 are formed in the active layers of the portions corresponding to the gaps.

The source region 106-4 and the drain region 106-5 are formed in the active layer of the portion corresponding to the source electrode 102 and the drain electrode 104, respectively. That is, in the drawing in order from the left, the active layer 106 is composed of the source region 106-4, the offset region 106-2, the channel region 106-1, the offset region 106-3, and the drain region. (106-5).

On the structure, an interlayer insulating film 112 having first and second contact holes H-1 and H-2 exposing the source electrode 102 and the drain electrode 104 is formed. The source electrode 102 and the drain electrode 104 are connected to the source wiring 114 and the drain wiring 116 through the first and second contact holes H-1 and H-2, respectively.

A manufacturing process of a thin film transistor having an offset region, which is the first embodiment of the related art, will be described.

Referring to FIG. 2A, a metal layer is formed on the insulating substrate 100 using a metal such as chromium (cr) or molybdenum (Mo), and an amorphous silicon layer doped with a high concentration of impurities is formed on the metal layer. Then, polycrystallization is performed by annealing using laser irradiation or the like.

Subsequently, the metal layer and the polycrystalline silicon layer are photo-etched at predetermined intervals to form respective ohmic contact insects 205 on the source electrode 202 and the drain electrode 204 and thereon.

Next, polysilicon is laminated on the insulating substrate 200 to cover each ohmic contact layer 205 to form an active layer 206. This active layer 206 is then patterned by photolithography to contact the substrate 200 between the source / drain electrodes 202 and 204.

At this time, the active layer 206 is formed by depositing a polysilicon layer as described above, or by depositing an amorphous silicon layer on a substrate and then annealing the amorphous silicon layer using laser irradiation or the like to form a polycrystalline crystal. do.

Referring to FIG. 2B, after the insulating film and the metal layer are sequentially formed on the insulating substrate 200 to cover the active layer 206, the source layer 202 and the drain electrode on the active layer 206 are formed by photolithography. Patterned so as to remain in a predetermined region between the (204) to form a gate electrode 201.

Next, the insulating film is patterned using the gate electrode 210 as a mask so as to remain only under the gate electrode 210 to form a gate insulating film 208.

In this case, the insulating film may be formed by depositing silicon oxide or silicon nitride by a chemical vapor deposition (CVD) method, and the like, or the metal layer may be formed by depositing aluminum or chromium by a sputtering method or the like.

Subsequently, the ion implantation mask M1 is formed to cover the active layer 206 between the source electrode 202 and the drain electrode 204, and then the active layer of the exposed portion is exposed using the ion implantation mask M1. (206-4, 206-5) is implanted with a high concentration of impurity ions by the method of ion doping. Heat treatment or laser irradiation is performed to activate the crystal structure of the active layer 206 damaged during the ion doping process.

In this case, in the active layer 206, offset regions 206-2 and 206-3 that are not doped with impurities are formed on both sides of the gate electrode 210. Therefore, these offset regions 206-2 and 206-3 are almost not conductive.

Referring to FIG. 2C, the ion implantation mask M1 is removed.

At this time, the channel region 206-1 is formed in the active layer of the portion corresponding to the lower portion of the gate electrode 210, and the respective offset regions 206- are not doped with impurities in the active layers on both sides of the channel region 206-1. 2 and 206-3 are formed, and a source region 206-4 and a drain region 206-5 are formed in the active layer around each of the offset regions 206-2 and 206-3. That is, the active layer 206 has a structure in the order of the source region 206-4, the offset region 206-2, the channel region 206-1, the offset region 206-3, and the drain region 206-5. Have In addition, the offset region 206-2 is almost non-conductive, and the current flows only when a certain amount of on current is applied, and serves to reduce the off current.

Next, after the interlayer insulating film 212 covering the gate electrode 210 and the active layer 206 is laminated on the insulating substrate 200, the active layer of a portion corresponding to the source electrode 202 and the drain electrode 204 is stacked. Each of the first and second contact holes H-1 and H-2 exposing 206 is formed.

Referring to FIG. 2D, a source wiring 214 and a drain wiring 216 are formed on the interlayer insulating film 212 to cover the first and second contact holes H-1 and H-2, respectively. At this time, the source wiring 214 is electrically connected to the lower source electrode 202 through the first contact hole H-1, and the drain wiring 216 is lower through the second contact hole H-2. Is electrically connected to the drain electrode 204.

In the first embodiment manufactured as described above, since the carrier is not actively moved in the offset regions 216-2 and 216-3 which are almost non-conductive, the off current is reduced, but in order to form the offset region. Increasing manufacturing cost and complexity of the process procedure by using a separate ion implantation mask has become a problem.

3 is a cross-sectional view of a thin film transistor having an LDD structure according to a second embodiment according to the prior art, and FIGS. 4A to 4D are manufacturing process diagrams of a thin film transistor having an LDD structure according to a second embodiment.

In the thin film transistor having the LDD structure according to the second embodiment of the present invention, referring to FIG. 3, the source electrode 302 and the drain electrode 304 are formed on the insulating substrate 300 at predetermined intervals. An active layer 308 is formed between the electrode 302 and the electrode. In addition, a gate electrode 310 is formed on the active layer 306 at a predetermined portion corresponding to between the source electrode 302 and the drain electrode 304, and between the active layer 306 and the gate electrode 310 a gate insulating film ( 308 is interposed.

A channel region 30 6-1 is formed in the active layer 308 at a predetermined portion corresponding to the gate electrode 310, and between the channel region 306-1 and the source electrode 302 and between the channel region 306-. Lightly doped dred (LDD) regions 306-2 and 306-3, which are lightly doped, are formed in the active layer 306 between 1) and the drain electrode 304. Source regions 306-4 and drain regions 306-5 are formed in the peripheral active layers 306 of the LDD regions 306-2 and 306-3, respectively. That is, in order from the left side in the figure, the active layer 306 is composed of a source region 306-4, an LDD region 306-3, and a drain region 306-5.

An interlayer insulating film 312 having third and fourth contact holes H-3 and H-4 exposing the source electrode 302 and the drain electrode 304 is formed on the structure. A source wiring 314 and a drain wiring 316 are formed to cover the third and fourth contact holes H-3 and H-4.

The source wiring 314 and the drain wiring 316 are electrically connected to the source electrode 302 and the drain electrode 304 through the third and fourth contact holes H-3 and H-4, respectively. do.

The manufacturing process of the thin film transistor according to the second conventional embodiment having the above structure will be described.

Referring to FIG. 4A, a metal layer is formed on the insulating substrate 400, and an amorphous silicon layer doped with a high concentration of impurities is formed on the metal layer, and then irradiated with laser to polycrystallize.

Then, the metal layer and the polycrystallized silicon layer are photo-etched at predetermined intervals to form the source / drain electrodes 402 and 404 and the ohmic contact layers 405 thereon.

Next, polysilicon is laminated on the insulating substrate 400 to cover each ohmic contact layer 405 to form an active layer 406. This active layer 4060 is then patterned by photolithography to contact the substrate 200 between the source / drain electrodes 402 and 404.

At this time, the active layer 206 is formed by depositing polysilicon as in the first embodiment. Alternatively, amorphous silicon is deposited on the substrate, and then the amorphous silicon is annealed using laser irradiation or the like to form polycrystallization.

Referring to FIG. 4B, an insulating layer and a metal layer are sequentially formed on the insulating substrate 400 to cover the active layer 406, and then the active layer between the source electrode 402 and the drain electrode 4 04 by a photolithography method. The gate insulating film 408 and the gate electrode 410 are formed by patterning the remaining portions at a predetermined portion of the 406.

Next, after forming an ion implantation mask M2 covering the active layers 406-1, 406-2 and 406-3 between the source electrode 402 and the drain electrode 404, the ion implantation mask M2 is formed. A high concentration of impurity ions of ion doping is doped into the active layer 40 6 of the exposed portion by using the mask M2.

Referring to FIG. 4C, the ion implantation mask M2 is removed.

LDD regions 406-2 and 406-3 are formed by doping a low concentration of impurity ions into the active layer 406 using the gate electrode 410 as a mask.

At this time, the active layer 406 has a channel region 406-1 formed under the gate insulating film 408, and LDD regions 406-2 doped with a low concentration of impurities on both sides of the channel region 406-1 ( 4 06-3) are formed, and source regions 406-4 and drain region 406-5 doped with a high concentration of impurity ions are formed around each of the LDD regions 406-2 and 406-3. Is formed.

That is, the active layer 406 is a source region 406-4-an LDD region 406-2-a channel region 406-1-an LDD region 406-3-sequentially from the left in FIG. 4C. Regions 406-5.

Since the LDD regions 406-2 and 406-3 are doped with low concentration of impurity ions, the carriers are not active, thereby reducing the off current.

Next, each of the third and fourth contact holes covering the active layer 406 and the gate electrode 410 on the insulating substrate 400 and exposing the source region 406-4 and the drain region 406-5. An interlayer insulating film 412 formed with (H-3, H-4) is formed.

Referring to FIG. 4D, a source wiring 414 and a drain wiring 416 are formed on the interlayer insulating film 412 to cover the third and fourth contact holes H-3 and H-4. The 414 is electrically connected to the lower source electrode 402 through the third contact hole H-3, and the drain wiring 416 is connected to the lower drain electrode 404 through the fourth contact hole H-4. ) Is electrically connected.

In the conventional second embodiment manufactured as described above, the carrier current is not active in the LDD region so that the off current is reduced, but when forming a source / drain region doped with a high concentration of impurities in the active layer, a separate ion implantation Since there is a need for a mask, there is a problem in that the cost increases and the process procedure increases.

5 and 6A through 6D are cross-sectional views of a thin film transistor having a dual gate structure and a thin film transistor manufacturing process according to a third embodiment of the prior art.

In the conventional thin film transistor having the dual gate structure according to the third embodiment, referring to FIG. 5, the source electrode 502 and the drain electrode 504 are formed on the insulating substrate 500 at predetermined intervals. Drain electrodes 502 and 504 and an active layer 506 are covered therebetween.

A first gate electrode 510 is formed on the active layer 506 corresponding to the source electrode 502 and the drain electrode 504 with a gate insulating film 508 interposed therebetween. In the active layer 506, a channel region 506-1 is formed at a portion corresponding to the first gate electrode 510, between the source electrode 502 and the first gate electrode 510, and the drain electrode 504. Field reduction regions 506-2 and 506-3 are formed at portions corresponding to between the first gate electrode 510 and the first gate electrode 510. That is, in order from the left side in the figure, the active layer 506 is composed of a field reduction region 506-2, a channel region 506-1, and a field reduction region 506-3.

An interlayer insulating film 5 12 is formed on the gate insulating film 508 to cover the gate electrode 510. The source electrode 502 is formed between the gate insulating film 508, the interlayer insulating film 508, and the interlayer insulating film 512. The fifth and sixth contact holes H-5 and H-6 exposing the drain electrode 504 are formed.

A source wiring 514 and a drain wiring 514 are formed to cover the fifth and sixth contact holes H-5 and H-6.

The source wiring 514 and the drain wiring 516 are connected to the source electrode 502 and the drain electrode 504 through fifth and sixth contact holes H-5 and H-6, respectively.

The manufacturing process of the thin film transistor according to the third conventional embodiment having the above structure will be described.

Referring to FIG. 6A, an amorphous silicon layer doped with a high degree of doping with a metal layer and an impurity is sequentially stacked on the insulating substrate 600, and then the amorphous silicon layer is irradiated with laser to polycrystallize.

next. The metal layer and the polycrystalline silicon layer are patterned at predetermined intervals by a photolithography method to form the source / drain electrodes 602 and 604 and the ohmic contact layer 605 thereon.

After forming an amorphous silicon layer that is not doped with impurities to cover the ohmic contact layer 605 on the substrate 600, the entire surface is crystallized while being locally melted by irradiation with a laser to form an active layer 606. Subsequently, the active layer 606 is patterned to cover the source electrode 602 and the drain electrode 604 by a photolithography method.

Referring to FIG. 6B, a gate insulating layer 608 is formed on the insulating substrate 600 to cover the source electrode 602, the drain electrode 604, and the patterned active layer 606.

And depositing a metal such as aluminum or chromium on the gate insulating film 608 by a sputtering method to form a metal layer. The first gate insulating layer is formed as a first gate insulating layer by patterning the photolithography method so as to remain on the gate insulating layer 608 corresponding to a predetermined region between the source electrode 602 and the drain electrode 604 by a photolithography method.

Referring to FIG. 6C, after forming the interlayer insulating film 612 on the gate insulating film 608 to cover the first gate electrode 610, the source electrode 602 and the drain electrode 604 may be formed by an acid etching method. The fifth and sixth contact holes h-5 and h-6 are formed by patterning the gate insulating layer 608 and the interlayer insulating layer 612 to expose the upper ohmic contact layer 605.

Referring to FIG. 6D, a metal layer is stacked on the interlayer insulating layer 612 to cover the fifth and sixth contact holes H-5 and H-6, and then the fifth contact hole H-5 and the fifth contact hole H-5 and the sixth contact hole H-5 and H-6. Each of the source wirings 6140 and the drain wiring 616 and the second gate electrode 618 are formed by patterning the sixth contact holes H-6 and remaining portions corresponding to the first gate electrodes 610.

The source wiring 614 and the drain wiring 616 are electrically connected to the lower source electrode 602 and the drain electrode 604 through the fifth and sixth contact holes H-5 and H-6.

In the active layer 606, a channel region 6 06-1 is formed at a portion corresponding to the first gate electrode 610, between the source electrode 602 and the first gate electrode 610, and the drain electrode 604. Field reduction regions 606-2 and 606-3, which are high resistance regions, are formed at portions corresponding to between the and first gate electrodes 601.

Accordingly, when the reverse bias is applied, the active layer 606 simultaneously generates positive charge and negative charge, thereby reducing off current as electrons push holes to the lower side of the substrate to complete the electric field strength. That is, the active layers 606-2 and 606-3 on both sides of the channel region 606-1 reduce the movement of carriers to the charge reduction region, thereby reducing the off current.

However, in the conventional third embodiment, the step coverage is poor because the contact force between the source / drain electrode as the metal layer and the active layer as the silicon layer is not good. Therefore, when the active layer is formed, the thickness of the thin film becomes thinner on the inclined side of the source / drain electrode, which causes a problem that the thin film on the inclined side of the source / drain electrode falls or the crystallization property deteriorates during laser crystallization.

In order to solve the above problems, the present invention is to provide a thin film transistor having a dual gate capable of effectively controlling the off current and a method of manufacturing the same.

Accordingly, in order to achieve the above object, the thin film transistor of the present invention covers a source / drain electrode and a first gate electrode formed at small intervals on the substrate, and a first gate electrode on the substrate to expose the source / drain electrode. A buffer oxide film having contact holes formed therein, an active layer formed on the buffer oxide film having a source region, an offset region, a channel region, an offset region, and a drain region; and a second gate electrode formed with a gate insulating layer interposed therebetween. Has a structure.

A method of manufacturing the thin film transistor of the present invention having the above structure comprises the steps of first forming a source / drain electrode and a first gate electrode on a substrate at a predetermined interval, and covering the first gate electrode on the substrate, Forming a buffer oxide film having respective contact holes exposing the drain electrodes, forming a second gate electrode having an active layer and a gate oxide film interposed therebetween, and forming a second gate electrode on the active layer using the second gate electrode as a mask And forming a source / drain region doped with impurities, a field reduction region and a channel region not doped with impurities.

1 and 2a to 2d is a first embodiment according to the prior art, a cross-sectional view and a manufacturing process diagram of a thin film transistor having an offset structure,

3 and 4A to 4D are cross-sectional views and manufacturing process diagrams of a thin film transistor having an L _DD structure according to a second embodiment according to the prior art.

5 and 6a to 6d are a third embodiment according to the prior art, which is a cross-sectional view and a manufacturing process diagram of a thin film transistor having a dual gate,

7 and 8a to 8d and 9 are a cross-sectional view, a manufacturing process diagram and a plan view of a thin film transistor having a dual gate according to the present invention,

10 is another embodiment according to the present invention. A plan view of a thin film transistor having a dual gate.

* Explanation of symbols for main parts of the drawings

100, 200, 300, 400, 500, 600, 700, 800: substrate

102, 202, 302, 402, 502, 602, 702, 802, 902, 1002, source electrode

104. 204 304 404 504 604 704 804 904 1004: Rain electrode

105, 205, 305, 405, 605, 705, 805: ohmic contact layer

106, 206, 306, 406, 506, 706, 806, 906, 1006: active layer

108, 208, 308, 408, 508, 608, 708, 808: gate insulating film

110, 210, 310, 410, 510, 610, 710, 810, 820, 910, 920, 1010, 1020: gate electrode

112, 212, 312, 412, 512, 612, 712, 812: buffer oxide film

H-1, H-2, H-3, H-4, H-5, H-6, H-9, H-10, H-11, H-12, s. Contact Hall

Hereinafter, the present invention will be described with reference to the accompanying drawings.

7 and 9 are cross-sectional views and plan views of a thin film transistor having a dual gate according to the present invention, and FIGS. 8A to 8D are manufacturing process diagrams of a thin film transistor having an Ekfs dual gate according to the present invention.

7 and 9, a thin film transistor having a dual gate according to an embodiment of the present invention may include source electrodes 702, 902, drain electrodes 704, 904, and first electrodes on an insulating substrate 700 at predetermined intervals. Gate electrodes 720 and 910 are formed.

The source electrodes 702, 902, drain electrodes 704, 904, and first gate electrodes 720, 910 are covered, and the source electrodes 702, 902, and first gate electrodes 720 ( In contact with the substrate 700 between the 910 and the first gate electrode 720, 910 and the drain electrode 704, each source electrode 702, 902 and drain electrode 704, 904 A buffer oxide film 712 is formed having the seventh and eighth contact holes H-7, H-8, H-9, and H-10 to be exposed. On the buffer oxide film 712, active layers 706 and 906 covering the seventh and eighth contact holes H-7, H-8, H-9, and H-10 are formed.

Second gate electrodes 710 and 920 having a gate insulating film 708 are formed on the active layer 706. The active layer 706 is divided into several regions. First, a channel region 706-1 is formed at a portion corresponding to the first gate electrodes 720 and 910, and the first gate electrodes 910 and 720 are formed. Field-reduction regions 76-2 and 706-3 are respectively formed between the source electrode 702 and the first gate electrode 720, 910 and the drain electrode 704, respectively. Source regions 706-4 and drain regions 706-5 are formed in portions corresponding to the source electrodes 702 and the drain electrodes 704.

A manufacturing process of a thin film transistor having a dual gate of the present invention having the above structure will be described.

Referring to FIG. 8A, a metal layer is laminated on the insulating substrate 800 using a metal such as chromium or molybdenum by sputtering or the like, and then a source electrode 802 and a drain electrode having a predetermined interval using a photolithography method. 804 and the first gate electrode 820 are formed.

In the above, an amorphous silicon layer doped with a high concentration of impurities is sequentially formed on the metal layer, and then the amorphous silicon layer is irradiated with a laser to polycrystallize, and the polycrystalline silicon layer is patterned by photolithography. An ohmic contact layer 805 may be formed on the source electrode 802, the first gate electrode 82, and the drain electrode 804.

Subsequently, a buffer oxide film 812 is formed on the insulating substrate 800 to cover the source electrode 802, the drain electrode 804, and the first gate electrode 820, and then the source electrode 802 and the drain electrode 804. ) Are respectively formed to the seventh and eighth contact holes (H-7, H-8).

Referring to FIG. 8B, an amorphous silicon layer is deposited on the buffer oxide film 812 to cover the seventh and eighth contact holes H-7 and H-8, and then irradiated with a laser to locally melt the front surface. Crystallized to form an active layer 806. Since the active layer 806 has a structure surrounding the source / drain electrodes 802 and 804, the thin film on the inclined side of the source / drain electrodes may fall or the crystallization characteristics deteriorate during laser crystallization.

Referring to FIG. 8C, the active layer 806 is patterned to cover the source electrode 802, the drain electrode 804, and the first gate electrode 820 by photolithography. The silicon oxide layer and the metal layer are sequentially stacked to cover the patterned active layer 806 on the buffer oxide film 812, and then patterned to cover the active layer of the portion corresponding to the first gate electrode 820 by a photolithography method. Thus, the gate insulating film 808 and the second gate electrode 810 are formed.

In this case, the width of the second gate electrode 810 is at least larger than that of the first gate electrode 820 to surround the first gate electrode 820.

The source region 806-4 and the drain region, which are high concentration impurity regions, are formed on the active layer 806 by doping PH ₃ ions using the second gate electrode 810 as a mask or by plasma treatment using a PH ₃ gas. 806-5).

Referring to FIG. 8D, an annealing process such as laser irradiation is performed to activate the crystal structure of the active layer 806 damaged during the ion doping process.

In this case, the active layer 806 has a channel region 8 06-1 formed at a portion corresponding to the first gate electrode 820, that is, on both sides of the channel region 806-1, that is, the first gate electrode 820. And field reducing regions 806-2 and 806-3 in the region between the second gate electrodes, and sources on both sides of the field reducing regions 806-2 and 806-3, which are high resistance regions, respectively. / Drain regions 806-4 and 806-5.

That is, the active layer 806 has a source region 806-4-a field reduction region 8 06-2-a channel region 806-1-a field reduction region 806-3 from the left side of FIG. 8D. 806-5 has a structure in which the reverse bias is applied, and when the reverse bias is applied, the electric field strength is relaxed in the field reduction region 806-2 which is a high resistance region, thereby reducing the off current.

For example, when a voltage of −10 V is applied to the first gate electrode 820, 10 V is applied to the second gate electrode 810, and 5 V is applied to the drain electrode 804, that is, the thin film transistor of the present invention has four terminals. As the carrier moves less in the charge reduction regions 806-2 and 806-3 on both sides of the channel region 806-1, the off current eventually decreases.

Referring to FIG. 10, the off current is controlled by connecting the first gate electrode 1020 and the second gate electrode 1010 with a contact hole S to form a three-terminal thin film transistor using one gate. You may. Reference numeral 1002 denotes a source electrode, numeral 1004 denotes a drain electrode, and numeral 1006 denotes an active layer.

As described above, in the present invention, the active layer surrounds the source / drain electrodes and forms a first gate electrode that is narrower than the second gate electrode between the source / drain electrodes, thereby controlling the off current and increasing the on current. There is an advantage.

Claims (4)

A thin film transistor having a dual gate, comprising: a source / drain electrode and a first gate electrode formed on a substrate at predetermined intervals, and a contact hole covering the first gate electrode on the substrate and exposing the source / drain electrode; A thin film transistor having a buffer oxide film, an active layer formed on the buffer oxide film and having a source region, an offset region, a channel region, an offset region, and a drain region, and a second gate electrode formed on the active layer with a gate insulating film interposed therebetween. . A method of manufacturing a thin film transistor having a dual gate, the method comprising: forming a source / drain electrode and a first gate electrode on a substrate at a predetermined interval, and covering the first gate electrode on the substrate, wherein the source / drain electrode is formed; Forming a buffer oxide film having respective contact holes exposed; forming a second gate electrode having an active layer and a gate oxide film interposed on the buffer oxide film; and forming a second gate electrode on the active layer with the second gate electrode as a mask. Forming a source / drain region doped with an impurity, a field reduction region and a channel region not doped with an impurity. The method of claim 2, wherein the width of the second gate electrode is larger than that of the first gate electrode. The method of claim 2, wherein a contact hole is formed in the second gate electrode, the buffer oxide layer, the active layer, and the gate insulating layer to connect the second gate electrode and the first gate electrode.

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