KR100246768B1 - Device and method for transmitting changeable format data - Google Patents

Abstract

The present invention relates to testing a particular chip by varying clocks and protocols, and in particular, an ISA bus 10 for sending AC-3 data from a PC to a transmission device; An input data buffer unit 20 configured as a FIFO to buffer the AC-3; A signal generator 30 for generating a control signal and outputting an appropriate control signal according to the host interface unit 40 and the error / full signal and FF and EF; A host interface 40 which receives a command from a PC and applies a signal to the signal generator 30; A clock divider 50 for dividing a clock to change a reference clock; A parallel / serial conversion unit 60 for converting 16-bit parallel data into serial data; An output interface unit 70 for generating a character clock or a serial clock and synchronizing with data; An output port 80 for stably outputting output data and a clock; An air / pull detector (90) for receiving an error or full signal from an AC-3 decoder and applying it to a signal generator; A variable format data transmission device comprising an oscillator 100 for generating a clock and applying it to a clock divider, which can shorten a test period of a chip and reduce an amount of unnecessary work. will be.

Description

Format variable data transmission apparatus and method

The present invention relates to testing a specific chip by varying a clock and a protocol (protocol, a protocol that defines a format communication method for data for communication between computers), and in particular, data in a data format corresponding to a specific chip. It is designed to test decoder chip by applying to AC-3 using application such as DVD (Digital Video Disk).

As shown in FIG. 1, the conventional apparatus includes a PC 1 for applying a bitstream; A decoder unit 2 for decoding MPEG-2 data applied from the PC 1; A central processing unit (3) for controlling the decoder (2); An interface unit 4 for correcting data appropriately for a chip to be tested with data applied from the decoder unit 2; It consists of an AC-3 decoder section 5 which decodes the AC-3 from the data corrected by the interface section 4.

Such a conventional apparatus separates data applied from a PC into MPEG-2 and AC-3, and then decodes MPEG-2 data in a decoder unit.

The interface unit decodes MPEG-2 data and corrects the data to fit the chip to be tested and applies the data to the chip to be tested.

The central processing unit transmits a control signal to the decoder to decode MPEG-2 data.

However, the conventional device configured as described above not only needs many devices to test the chip, but also needs to correct the data to be suitable for the chip to be tested, and again to interface data to correct the data to the chip to be tested. There was a problem that must invest a lot of time due to the inconvenience to configure.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems, and in particular, it is possible to adjust the division ratio of the clock divider and change the reference clock value by writing an address value in the address line of the PC bus. It is possible to convert the configuration of the output interface outputted to the configuration, and the setting of the configuration is to provide an apparatus and method for a variable format data transmission is performed by operating a specific flip-flop according to the value of the address.

In order to achieve the above object, the present invention provides a format variable data transmission device comprising: an ISA bus for controlling the configuration and operation of the transmission device through a role and an address for transmitting AC-3 data from a PC to the transmission device; An input data buffer configured to comprise First In First Out (FIFO) and buffering AC-3; A signal generator for generating a control signal and outputting an appropriate control signal according to a host interface, an error / full signal, and FF and EF; A host interface for receiving a command from a PC and applying a signal to the signal generator; A clock divider for dividing a clock to change a reference clock; A parallel / serial converter for converting 16-bit parallel data into serial data; An output interface unit for generating a character clock or a serial clock and synchronizing with data; An output port for stably outputting output data and a clock; An error / full detector receiving an error or full signal from the AC-3 decoder and applying it to a signal generator; And an oscillator generating a clock and applying the clock to a clock divider.

1 is a block diagram showing a conventional device for testing a MEPG-2 or AC-3 chip.

2 is a block diagram showing an apparatus and method for transmitting a variable format data according to an embodiment of the present invention.

3 is a flow chart showing the operation of the present invention.

4 is a flow chart showing operation in a PC of the present invention.

* Explanation of symbols for main parts of the drawings

10: ISA bus 12: PC

20: input data buffer unit 30: signal generator

40: host interface unit 50: clock divider

60: parallel / serial converter 70: output interface

80: output port 90: error / full detection unit

100: oscillator 110: IC chip

Hereinafter, with reference to the accompanying drawings for an embodiment according to the technical spirit of the present invention and the format variable data transmission apparatus configured as described above in detail.

As shown in FIG. 2, in the ISA bus 10, AC-3 data is applied from the PC 12 to the transmission device, the configuration and operation of the transmission device are controlled through the address, and the input data buffer unit 20 is provided. In buffering AC-3 data and sends FF (Full Flag), EF (Empty Flag) to the signal generator 30, all control signals such as reset, read, write, etc. are inputted from the signal generator 30 to operate. The signal generator 30 generates a control signal and transmits a control signal according to the host interface 40, an error / full signal, and the FF and EF, and the host interface 40 issues a command from the PC. It is applied to output to the signal generator 30, the clock divider 50 divides the clock to change the reference clock, the count is operated according to the reference clock used for the control signal, the parallel / serial converter 60 Converts 16-bit parallel data into serial data In the output interface unit 70, a character clock or a serial clock is generated to synchronize with data, and the output port 80 stably transmits the output data and the clock, and the error / full detector unit AC- An error or full signal is received from 3 and sent to the signal generator. The oscillator 100 forms a clock and supplies the clock divider to configure the present embodiment.

EXAMPLE

Hereinafter, the operation of the present embodiment configured as described above will be described.

First, when the PC 12 sends a transfer command to the ISA bus 10, the AC-3 data is stored in the memory of the PC in units of pages on the PC's hard disk.

Then, the ISA bus 10 applies the 16-bit parallel AC-3 data applied from the PC to the host interface 40 and controls the host interface 40 through the address, thereby providing an input data buffer 20 ) Will transmit the data from the PC.

Then, when the input data buffer unit 20 buffers AC-3 data and sends FF and EF to the signal generator 30, the signal generator 30 receives all control signals such as reset, read, and write, and operates to control. The signal, that is, the host interface unit 40, an error / full signal, and an appropriate control signal according to the FF and EF are outputted to the PC 12.

On the other hand, when the host interface 40 receives the address value from the PC and outputs the signal to the signal generator 30, the clock divider 50 divides the clock generated from the oscillator 100 to change the reference clock. The counter is operated in accordance with the reference clock to synchronize all operations of the transmitter with the reference clock.

When the parallel / serial converter 60 converts 16-bit parallel data into serial data and applies it to the output interface 70, the output interface 70 outputs the signal applied from the parallel / serial converter. When applied to the output port 8 in synchronization with the output port 80, the output interface 70, the output data and clock is stably sent to the IC chip 110 to test the applied signal.

Then, when the error / full detection unit 90 receives an error or a full signal from the AC-3 output from the IC chip 110 and applies a signal to the signal generator 30, the error-full detection unit 90 receives the AC- to the ISA bus 10. The state of the IC chip 110 is transmitted to the PC 12 by transmitting three signals.

As shown in FIG. 3 and FIG. 4, the present invention provides a format variable data transmission method comprising: a tenth step (S10) of inputting a clock division ratio; A twentieth step (S20) of inputting a protocol; A thirtieth step (S30) of inputting the number of bits; A 40th step (S40) of inputting a delay time; Resetting a FIFO for storing data (S50); A sixty step S60 of releasing an interrupt signal; In operation 70, data is processed by the PC.

On the other hand, the seventieth step (S70), step 71 (S71) for determining whether the data file has been read; A step 72 in which the operation of the program is terminated when the file is not read in step 71 (S71) and an input routine is set when the data file exists when the file is read; Step 73 (S73) for comparing and determining whether an EMS memory exists in a file; A 74th step (S74) of terminating the program if the EMS memory does not exist in the 73rd step (S73) and determining an area of the memory if the EMS memory exists; A seventy-fifth step S75 of determining whether data transmission is completed; A step 76 (S76) of terminating the program routine when the transmission is terminated in the 75 th step (S75), and determining whether the transmitted page is the end when the data transmission is not finished; Step 77 (S77) of transmitting data to the EMS memory when the number of pages of data transmitted in the 76th step (S76) is not the last; Step 78 (S78) of outputting data and transmitting the data to the transmission card when the number of pages of the transmitted data is the last; A seventy-seventh step of determining whether an interrupt has occurred; If the interrupt is not generated in the 79th step S79, the determination is made until there is an interrupt signal. When the interrupt signal is generated, the operation returns to the 75th step S75.

As described above, the apparatus and method of the present invention can be used in general, and can be easily used and can shorten the test period of the chip by transmitting data of various formats without hardware replacement. In addition, it can be used for various purposes, such as price, and can reduce the amount of unnecessary work.

Claims (3)

An ISA bus that controls the configuration and operation of the transmission device through its role and address of sending AC-3 data from the PC to the transmission device; An input data buffer configured as a FIFO to buffer the AC-3; A signal generator for generating a control signal and outputting an appropriate control signal according to a host interface, an error / full signal, and FF and EF; A host interface for receiving a command from a PC and applying a signal to the signal generator; A clock divider for dividing a clock to change a reference clock; A parallel / serial converter for converting 16-bit parallel data into serial data; An output interface unit for generating a character clock or a serial clock and synchronizing with data; An output port for stably outputting output data and a clock; An error / full detector that receives an error or full signal from an AC-3 decoder and applies it to a signal generator; And an oscillator for generating a clock and applying the clock to a clock divider. A tenth step (S10) of inputting a clock division ratio; A twentieth step (S20) of inputting a protocol; A thirtieth step (S30) of inputting the number of bits; A 40th step (S40) of inputting a delay time; Resetting a FIFO for storing data (S50); A sixty step S60 of releasing an interrupt signal; The variable format data transmission method of claim 70, wherein the data is processed in step 70 (S70). The method as claimed in claim 2, wherein the seventy-seventh step (S70) comprises: a seventy-first step (S71) for determining whether a data file has been read; A step 72 in which the operation of the program is terminated when the file is not read in step 71 (S71) and an input routine is set when the file exists when the file is read; Step 73 (S73) for comparing and determining whether an EMS memory exists in a file; A 74th step (S74) of terminating the program if the EMS memory does not exist in the 73rd step (S73) and determining an area of the memory if the EMS memory exists; A seventy-fifth step S75 of determining whether data transmission is completed; A step 76 (S76) of terminating the program routine when the transmission is terminated in the 75 th step (S75), and determining whether the transmitted page is the end when the data transmission is not finished; Step 77 (S77) of transmitting data to the EMS memory when the number of pages of data transmitted in the 76th step (S76) is not the last; Step 78 (S78) of outputting data and transmitting the data to the transmission card when the number of pages of the transmitted data is the last; A seventy-seventh step of determining whether an interrupt has occurred; If the interrupt is not generated in the seventy-seventh step (S79), the determination is made until there is an interrupt signal, and if the interrupt signal is generated, the method returns to the seventy-seventh step (S75).

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