KR100233478B1 - Spread spectrum signal receiving apparatus - Google Patents

Abstract

The spread spectrum signal receiving apparatus includes a radio frequency processing circuit 32 for converting a spread spectrum signal into an intermediate frequency signal, a binary encoder 35 for encoding the intermediate frequency signal, and a pseudo-random noise code generator 51; A code driver 54 for controlling the phase and chip speed of the code generator, a first multiplier 36 for multiplying the binary signal to an output of the code generator, and a numerically controlled oscillator for outputting first and second carrier signals ( 61) a second and third multipliers 62 and 63 for multiplying the output signal of the first multiplier by the first and second carrier signals, respectively, and a second provided with the output signals of the second and third multipliers, respectively. A microcomputer having first and second low pass filters 64 and 65, and functions 101 and 102 for generating a control signal for controlling the numerically controlled oscillator and functions for generating a signal for controlling the code driver 103-113. Computer 100.

Description

Spread Spectrum Signal Receiver

1 (a) and 1 (b) are block diagrams of an exemplary embodiment showing a spread spectrum signal receiving apparatus according to the present invention.

2 (a) to 2 (c) are graphs showing the correlation output levels between the pseudo random noise code of the received signal and the pseudo random noise code on the receiver side.

3 to 7 are flowcharts sequentially showing microcomputer operations realized by the embodiment of FIG.

8 is a diagram for explaining the principle of operation in the flow chart of FIG.

9 is a block diagram of a conventional spread spectrum signal receiving apparatus.

* Explanation of symbols for main parts of the drawings

32: RF processing CCT 35: binary encoder

36: signal multiplier 51: code generator

54: clock generator 61: carrier generator

The present invention relates to an apparatus for receiving spread spectrum signals, such as satellite signals used in mobile positioning systems and the like.

Systems for determining the position of a moving object using orbit around the earth or using several satellites are known, which use spread spectrum modulation in processing satellite signals. For example, in a positioning system called GPS (Global Positioning System), the 50-bps orbital parameter data (including orbital data to indicate the time and position of the satellite) is pseudo-bite with a chip speed of 1.023 MHz and a period of 1 msec. The satellite signal is transmitted with spread spectrum modulation according to a random noise code (e.g. GOLD code) and with two carriers of 1575.42 MHz and 1227.6 MHz being processed with quadrature phase modulation (two-phase PSK modulation). It is done.

The GPS receiver modulates the orbital parametric data of each satellite by processing input signals received from at least three satellites with follow-up and spectral reversal of the two carriers to obtain a signal arrival time (i.e., time of arrival of this satellite). From this, you can see the distance between satellite and user) and satellite location data. The position of the user can be determined three-dimensionally from the intersection of the sphere defined by the coordinates with the center corresponding to the position of the satellite and the radius corresponding to the measured distance.

9 shows a typical configuration of a conventional GPS receiver. The signal received at the antenna 1 is applied to the radio frequency processing circuit 2, in which the carrier wave is converted into an intermediate frequency signal of 10.7 MHz (signal band 10.7 ± 1.023 MHz).

The intermediate frequency signal is applied to a demodulator to be described later. The demodulator has a feedback loop for reverse evolution to demodulate the spread spectrum modulation and another feedback loop for demodulating two-phase modulation according to the orbital parameter data bits.

In this example, a technique known as [tau] -ditter tracking is applied to the reversal demodulation feedback loop. The code generator 20 is for generating a pseudo-random noise code on the receiver side and includes an electrical code Me having a phase difference of 1-chip time and a late code Md. Electrical code Me and late code Md from code generator 20 are supplied to electrical / late code selector 21, which is selectively switched every millisecond by electrical / late switch 22. From the code selector 21 a synthesized pseudo-random noise code is obtained. The synthesized pseudo-random noise code thus obtained is then supplied to the balance modulator 3. The intermediate frequency signal from the radio frequency processing circuit 2 is fed to a balanced modulator 3 which is modulated by a synthetic pseudo-random noise code.

The code generator 20 is controlled by a clock pulse, which is generated by the clock generator 23 as a code driver and controlled by the frequency and phase which will be described later, such methods include electrical and late pseudo-random noise code Me. And the phase and frequency (chip rate) of Md coincide with the phase and frequency (chip rate) of the pseudo-random noise code included in the intermediate frequency signal obtained from the radio frequency processing circuit 2.

The feedback loop that demodulates the data bits consists of a Costas loop in this example. This Costas loop consists of a voltage controlled variable frequency oscillator (hereinafter referred to as VCO) and a carrier generator (4) consisting of at least 90 °, first and second analog multipliers (5 and 6), low pass filters (7 and 8), And a third analog multiplier 9 and a loop filter 10.

The first and second carrier signals cos wt and sin wt of quadrature phases are generated from the carrier generator 4 so that the first and second multipliers 5 and 6 are supplied to each to obtain the equilibrium modulator 3. It is multiplied by the reversal intermediate frequency signal (± A cos (wt + ø)). The outputs of the first and second multipliers 5 and 6 are fed to the third multiplier 9 via the low pass filters 7 and 8 respectively and multiplied with each other. The output level of the third multiplier 9 represents the phase difference between the carrier component of the received signal and the carrier generated from the carrier generator 4. The output of the multiplier 9 is supplied to the carrier generator 4 via the loop filter 10 so that the VCO of the carrier generator 4 is such that the phase of the output carrier signal of the carrier generator 4 follows the carrier component of the signal Si. Controlled.

The outputs (± 1/2 A cosø and ± 1/2 sinø) of the first and second low pass filters 7 and 8 in the Costas loop are fed to the square law detectors 11 and 12, respectively, where square law detection is performed. do. The outputs of these detectors are supplied to an adder 13 and added to each other. The output of adder 13 indicates the correlation level between the received pseudo-random noise code and the pseudo-random noise code obtained from code generator 20.

The output of the adder 13 is supplied via the analog switch 14 to the electrical data output 15 and the late data output 16, each of which is composed of an integrator. The analog switch 14 is changed by a switching signal from the electrical / late switch 22 at the same time as the electrical / late code selector 21 changes. Therefore, if the pseudo-random noise code from the code generator 20 is the electrical code Me, the obtained correlation level output is stored in the electrical data holder 15. On the other hand, if the pseudo-random noise code from the code generator 20 is the late code Md, the obtained correlation level output is stored in the late data holder 16.

The correlation level outputs of the electrical data holder 15 and the late data holder 16 are supplied to a subtractor 17 composed of a differential amplifier or the like, whereby a difference between the two correlation level outputs can be obtained. This output difference represents the phase error of the received pseudo-random noise code and the pseudo-random noise code from the code generator 20. This output difference is fed to the VCO of the clock generator 23 operating as a code driver via a loop filter 18 so that the output pseudo-random noise code from the code generator 20 is received as above. It is controlled to follow.

The correlation level output from the adder 13 is supplied to the search / sync detector 19, and the frequency of the output clock signal from the clock generator 23 is the pseudo- received during the phase lock process for the pseudo-random noise code. For a random noise code, it varies widely until a certain correlation is obtained by the detector 19, and also the frequency and phase of the pseudo-random noise code from the code generator 20 vary widely to perform the search. do. Once a certain correlation is obtained, the search is stopped and the clock generator 23 is then controlled by the output of the loop filter 18.

In the above-described manner, a signal received according to spread spectrum modulation is demodulated by an inverse feedback feedback loop, while data bits are demodulated by a Costas loop. The demodulated data bit output is generated from the low pass filter 7 and supplied to a data demodulator (not shown) and the trajectory parameter data is demodulated.

However, since the conventional spread spectrum signal receiving apparatus requires a balanced modulator 3 to obtain a predetermined correlation with the pseudo-random noise code at the receiver side, it is necessary to maintain the proper balance of the balanced modulator 3. The need for an analog signal is increased.

In addition, since the VCO is provided in each of the carrier generator 4 and the clock generator 23, circuit technology and circuit elements are required to maintain the desirable linearity of the VCO. Therefore, the structure of the receiving device is complicated along with other disadvantages that result in an increase in manufacturing cost. In addition, there is another disadvantage that the dimensions of the device are increased.

In addition to the above drawbacks, there arises a problem that the parameters of the reversal feedback loop and the data bit demodulation feedback loop are numerically fixed as circuit elements or parts and therefore cannot be easily changed for control.

It is therefore an object of the present invention to provide an improved spread spectrum signal receiving apparatus suitable for eliminating the above disadvantages by digital high density integration and application of software.

It is another object of the present invention to provide an improved wideband spectral signal that can produce satisfactory correlation levels despite the use of digital circuit configurations.

According to an aspect of the present invention, a binary frequency signal supplied from a radio frequency processing circuit and a radio frequency processing circuit for converting a spread spectrum signal whose carrier is modulated by a pseudo-random noise code into an intermediate frequency signal are binary. A binary encoder for encoding, a pseudo-random noise code generator, a code driver for controlling the phase and chip rate of the output pseudo-random noise code from the pseudo-random code generator, and a binary signal from the binary encoder And a first multiplier for multiplying to an output pseudo-random noise code from a pseudo-random noise code generator, and first and second tracking frequency-converted carriers having a π / 2 phase difference and included in an intermediate frequency signal. Π / 2 phase difference between the numerically controlled oscillator for outputting the carrier signal and the output signal of the first multiplier Second and third multipliers for multiplying the first and second carrier signals, the first and second low pass filters each of which is provided with a counter and to which an output signal of each of the second and third multipliers is supplied; For controlling the numerically controlled oscillator such that the frequency and phase of the output carrier signal of the numerically controlled oscillator follow the frequency and phase of the half-single component included in the frequency signal in response to the count output of the filter of the second and third low pass filters. Provided is a spread spectrum signal receiving apparatus having a microcomputer with a function of generating a control signal, the microcomputer also having a phase of an output pseudo-random noise code from a pseudo-random noise code generator based on a count output. Control the code driver to match the phase of the pseudo-random noise code contained in the spread spectrum signal It has a function to generate a control signal for doing so.

In the present invention having the above-described configuration, the received spread spectrum signal is converted to an intermediate frequency signal and then binary encoded, and the configuration of the reverse feedback feedback loop and the data bit demodulation feedback loop after such binary encoding is digitalized. . The control signal of this feedback loop is also formed by software.

Therefore, the balance modulator used in the conventional apparatus is no longer needed, and the use of a numerically controlled variable frequency oscillator eliminates the need for a VCO, making it possible to manufacture a simplified spread spectrum signal receiver of low cost.

Other features and advantages of the invention will appear from the detailed description with reference to the accompanying drawings.

1 is a block diagram of a spread spectrum signal receiving apparatus for implementing the present invention. This embodiment represents a receiving device for use with a global positioning system (GPS).

The satellite signal (spread spectrum signal) received at the antenna 31 is supplied to the radio frequency processing circuit 32. In the meantime, the output of the reference oscillator 33, which is an 18.414 MHz quartz oscillator, is supplied to the local oscillator 34 generating a local oscillation output, where the output frequency of the reference oscillator and the frequency ratio therefrom are fixed.

The local oscillation output thus obtained is supplied to the frequency processing circuit 32, where the satellite signal is converted into a first intermediate frequency 19.437 MHz signal and again by the oscillation output of the reference oscillator 33, the second intermediate frequency of 1.023 MHz. The second intermediate frequency signal Sif is converted.

The second intermediate frequency Sif obtained from the radio frequency processing circuit 32 is supplied to the binary encoder 35 and compared with a predetermined threshold level so as to be converted into a binary signal.

The binary output Sd of the binary encoder 35 is supplied to a signal multiplier 36 composed of an exclusive OR circuit.

In this embodiment, similar to the conventional example described above, the τ-dither tracking technique is used for the reverse development demodulation feedback loop 50 and the costas loop is used as the data bit demodulation feedback loop 60. Each of these two loops is formed in a digital circuit configuration, and the control signal for the loop is generated by means of software in the microcomputer 100.

The reversal demodulation feedback loop 50 has a code generator 51 for generating a pseudo-random noise code on the receiver side, where an initial code Me and a late code Md having a phase difference of 1-chip time are generated ( In GPS satellite signals, 50-bps orbital parametric data is processed by spread spectrum modulation according to a pseudo-random noise code with a chip rate of 1.023 MHz and a period of 1 msec.

The initial code Me and the late code Md from the code generator 31 are fed to the early / late code selector 52, so that a composite pseudo-random noise code is obtained from the code selector 52. Change every millisecond by the switching speed. The complex pseudo-random noise code is then fed to a multiplier 36 where the noise code is multiplied by a binary intermediate frequency signal Sd obtained from the binary encode 35.

In this example, the clock generator 54 which generates a drive clock signal to control the output code phase and frequency (chip rate) of the code generator 51 consists of a numerically controlled variable frequency oscillator (hereinafter referred to as NCO). . The reference clock signal is supplied from the reference oscillator 33 to the clock generator 54 to generate a drive clock signal for controlling the code generator 51 under microcomputer control from the reference clock signal.

In code generator 51, the phase and frequency of the early and late pseudo-random noise codes are controlled by clock signals of controlled phase and frequency obtained from clock generator 54. As a result, the pseudo-random noise code output from the code generator 51 is controlled to match the phase and frequency of the pseudo-random noise code included in the intermediate frequency signal Sd obtained from the binary encoder 45, so that the reverse development is performed. Is performed.

The Costa feedback loop 60 for demodulating the data bits includes a carrier generator 61 consisting of an NCO and a 90 ° right-side shifter, first and second multipliers 62 and 63 consisting of an exclusive OR gate, and a low pass filter. 64 and 65, a microcomputer 100 for generating a control signal for the carrier generator 61 is provided. The carrier generator 61 receives a reference clock signal from the reference oscillator 33 and generates a carrier signal in response to the reference clock signal under the control of the microcomputer 100.

The microcomputer 100 executes the respective functions shown in FIG. 1 as functional blocks using program software. The processing functions of the microcomputer 100 will now be described in detail below in connection with the functional blocks of FIG. A multiplication means 101 is provided for multiplying the calculated values of the low pass filters 64, 65 consisting of a counter, thereby matching a phase difference between the carrier component of the received signal and the carrier obtained from the carrier generator 61. Generate the output. The loop filter means 102 forms a signal from the output of the multiplication means 101 and supplies a signal to the carrier generator 61 for controlling the carrier generator 61. The means partly constitutes a Costa feedback loop 60.

The absolute value detecting means 103, 104 respectively detect the count output absolute value of the low pass filters 64, 65, and the detection outputs are added to each other in the adding means 105. The adding means 105 generates a signal indicative of the correlation level between the pseudo-random noise code and the pseudo-random noise code in the signal received from the code generator 51. For the output of the low pass filters 64, 65, absolute value detection is performed instead of square-law detection based on the following reasons.

In the conventional analog configuration of FIG. 9, the outputs of the low pass filters 7, 8 are as indicated by dashed lines a and b respectively in FIG. 2 (a) when the correlation described above is maintained between them. Likewise, there is a relationship between cosine and sine. Therefore, if the two outputs are added to each other after square-low detection, a fixed level of signal can be obtained. However, in this embodiment, the output of the low pass filters 64, 65 is a binary signal. The correlation output of the low pass filters 64, 65 is thus a triangular waveform as indicated by the thick lines c and d in FIG. 2 (a) when the correlation described above is maintained between them. Therefore, when the outputs of the low pass filters 64, 65 are added to each other after square-low detection as in the known example, the added output levels are related to a predetermined correlation as shown in Fig. 2 (b). Without being fixed, it becomes impossible to identify between reaching and not reaching a correlation.

In light of this, the added output obtained after the absolute value detection as in this embodiment has a fixed level as shown in Fig. 2 (c), thereby enabling accurate identification of whether or not proper correction is made. .

The output of the adding means 105 is transmitted to the switch means 106, which is initially initialized synchronously with the selector 52 such that the switched output is stored in the initial data holding means 107 or the later data holding means 108. By the switching signal at the late switch 53. In practice no switch means 106 are required. In this case, the memory area for the initial data and the memory area for the late data are selected in response to a switching signal at the initial / late switch 53, and such initial data and late data are stored in each of the selected areas. The output of the initial data holding means 107 and the output of the late data holding means 108 are supplied to a subtraction means 109 where subtraction of the two outputs is performed. The result of such subtraction is supplied to the loop filter means 110, which forms a numerical control signal for controlling the phase of the drive clock signal output from the clock generator 54 with respect to the code generator 51.

The output of the adding means 105 is supplied to the search signal generating means 111 and also to the synchronizing signal detecting means 112. The search signal generating means 111 generates a search signal to perform a search by sliding the output code of the code generator 5 by one cycle until a predetermined correlation is reached. The synchronization signal detecting means 112 maintains the added output monitoring and supplies a switching signal to the switch means 113 which determines one of the search or phase control according to the output of the loop filter 110 and the search signal generating means ( One of the output of 111 and the output of loop filter means 110 is selected. The output of the switch means 113 is supplied to a clock generator 54.

The actual processing of the microcomputer 100 will next be described with reference to the flowcharts of FIGS. 3-7, wherein the reference number of the functional means corresponds to that used in FIG. The operations shown in FIGS. 3-7 are repeated every millisecond in accordance with the chip rate of the pseudo-random noise code. Therefore, each of the low pass filters 64, 65 has a counter configuration and is reset every millisecond.

Referring to FIG. 3, I data from the low pass filter 64 of the counter configuration is input (step 201), and its absolute value is calculated (step 202). Similarly, Q data from the low pass filter 65 of the counter configuration is input (step 203) and its absolute value is calculated (step 204).

The absolute value of the I data calculated in step 202 and the absolute value of the Q data calculated in step 204 are then added together to obtain result A (step 205). And according to the switching signal from the early / late switch 53, a determination is made as to whether the current operating mode is the initial mode, where the code generator 51 generates an initial code Me (step 206). If the result of such a decision indicates an initial mode, the addition result A is recorded in the initial data storage area of the RAM (step 207). In the case where the result of such a determination indicates the initial mode, the addition result A is recorded in the initial data storage area of the RAM (step 207). When the result of the determination indicates a late mode in which the code generator 51 generates the late code Md, the addition result A is recorded in the late data storage area of the RAM (step 208).

The operation then proceeds to the flowchart of FIG. The partial progress shown in FIG. 4 coincides with the operation performed by the synchronization detecting means 112 in FIG. In particular, first, a determination is made whether or not the addition result A obtained in step 205 exceeds a predetermined threshold level (step 211). This determination is made so that the feedback loop 50 knows whether or not a predetermined correlation is made between the pseudo-random noise code of the received signal and the pseudo-random noise code from the code generator 51.

If the result of such a determination indicates reaching a predetermined correlation, the first timer S is set to "10" (10 msec) (step 212) and the second timer P is "30000" (30sec) (step 213). ), The operation then proceeds to the flowchart of FIG. 6 to form a control signal for the Costa Loop 60.

If the result of the determination in step 211 indicates non-correlation of the desired correlation, the set value of the first timer S is increased by “1” (step 214), and the value of the first timer S is “0”. A determination as to whether or not is made (step 215). If the result of the determination is negative, this means that the first timer S is not "0" and the operation proceeds to the flowchart of FIG.

If the result of the determination indicates that the value of the first timer S is not "0", the timer S is set to "1" (step 216), and the determination as to whether or not the value of the second timer P is "0" is determined. (Step 217). If the value of the second timer P is "0", the operation proceeds to the flowchart of FIG. 5 with respect to the irradiation signal generating means 11 and the loop filter means 102 in the irradiation mode. If the value of the second timer P is not "0", the value is decreased by "1" (step 218) and proceeds to the flowchart of FIG. 7 with respect to the loop filter means 110 of the feedback loop 50. .

In this case, if the arrival of the predetermined correlation is detected (correlation fixed) in the feedback loop 50, the first timer repeats the determination result in step 211 10 times for 10 ms continuously in the flowchart of FIG. It does not play a role in determining the uncorrelated relationship unless a certain correlation is not achieved.

If a correlation lock is detected once in the feedback loop 50, the second timer P may be for example a preset time of 30 seconds despite the non-correlation determination (meaning non-correlation of a predetermined correlation for 10 msec continuously). Will remain in this state for a while. In this state, however, the control of the output of the carrier generator by the loop filter 102 of the feedback loop 60 and the phase and frequency of the output of the clock generator 54 by the loop filter 110 of the feedback loop 50. Control is performed. If the predetermined correlation is not reached even after the elapse of 30 seconds, the operation proceeds to the flowchart of FIG. 5 in relation to the correlation investigation.

When the correlation lock state is detected in the feedback loop 50, the correlation non-fixation state is not immediately determined even if the determination result in step 211 implies that the predetermined correlation is not reached, and the determination of correlation non-fixation is made. Nevertheless, the operation does not proceed immediately to the correlation investigation mode. Therefore, even if correlation unfixing is detected during a period where true correlation does not substantially disappear, such as in the case where an obstacle such as an airplane is temporarily present between the satellite and the receiving device, the operation requires an undetermined correlation that requires a relatively long time. It does not proceed with relationship investigation. According to this design, the feedback loop 50 is hardly influenced by the presence of any momentary interference at the time of reception, thereby making it possible to maintain a stable reception state.

The flowchart of FIG. 5 will now be described with respect to the loop filter means 102 and the irradiation signal generating means 111 in the irradiation mode.

The investigation in this embodiment is carried out in the following manner. The received signal converted to the intermediate frequency signal Sif is in the range 1.023 MHz ± 15 MHz. Therefore, a predetermined correlation can be reached by examining the above range. However, since the bandwidth of the loop filter means 102 is in a narrower frequency range than the above irradiation range, in this example ± 350 MHz, correlation investigation can be performed within the bandwidth of the loop filter means 102.

Therefore, in this embodiment, the electrical and late codes from the code generator 51 are controlled to slide by one period at the center frequency fc corresponding to the output of the carrier generator 61. When the predetermined correlation is not reached by such one-cycle slide control, the oscillation center frequency fc of the carrier generator 61 is shifted by 700 Hz, and the slide control for the code generator 51 is executed again. . Such control actions are carried out continuously in the range of ± 15 kHz. In this process, a change of 700 Hz for the frequency fc is carried out in an alternating positive and negative direction.

In Fig. 5, since a predetermined correlation has not been reached in the feedback loop 50 (step 221), the correlation unfixed state is first adjusted to an initial value. A determination is then made (step 222) as to whether or not the one-cycle slide (phase control) of the early and late codes from the code generator 51 has been completed. For example, a predetermined time of 4 seconds is required to perform correlation investigation as outputting a complete 1-cycle of the pseudo-random noise code from the code generator 51. Therefore, a decision regarding the end of the 1-cycle slide is made by monitoring a 4 second timer.

When the result of the determination at step 222 indicates four seconds have elapsed, it means that a certain correlation has not been achieved by a one-cycle investigation of the output from the code generator 51. Therefore, a numerical control signal is formed to change the oscillation center frequency fc of the carrier generator NCO in the Costas loop with a predetermined step width f = 700 Hz (step 223). This numerical control signal is then supplied to the carrier generator 61 (step 224). Thereafter, a numerical control signal is formed to slide the output of the code generator 51 in one cycle again, and is supplied to the clock generator 54 (step 225).

The result of the determination in step 222 does not represent the passage of 4 seconds, which means that one cycle of sliding of the output of the code generator 51 has not yet been completed. Thus, the oscillation center frequency of the carrier generator 61 remains unchanged in the Costas loop, and operation proceeds to step 225, where a numerical control signal for sliding the output of the code generator 51 in one cycle is continuous. Is supplied to the clock generator 54. After the end of step 225, the operation returns to step 201 in FIG. 3 (see FIG. 7).

As a result of the correlation investigation, the correlation fixed state is reliably detected anywhere.

Under the detection of the predetermined correlation arrival in step 211 of FIG. 4, the operation proceeds to the flowchart of FIG. 6 with respect to the loop filter means 102 in order to finely control the carrier generator 61. The operation in this flowchart for controlling the carrier generator 61 in the correlation fixed state is executed in the following manner.

First, the carrier generator 61 is set to the oscillation center frequency with reaching a predetermined correlation. Then, according to the output of the multiplication means 101, which is an error signal serving as a reference signal for controlling the carrier generator 61, the oscillation frequency of the carrier generator 61 has a positive side (which is higher than the oscillation frequency). , Which is lowered toward the center frequency fc by a predetermined frequency width of, for example, 30 Hz. In contrast, when the multiplied output is negative (which indicates that the oscillation frequency is shifted toward the lower side), the oscillation frequency of the carrier oscillator 61 is raised by a predetermined frequency width of, for example, 30 Hz with respect to the center frequency fc. This frequency shift is performed every mS per operation in this flowchart. This frequency shift is repeated for a time of, for example, 50 mS, and the number of positive multiplication outputs and the number of negative multiplication outputs are counted and compared with each other during 50 mS. This operation can be performed with a single counter that counts up the positive output or counts down the negative output.

If the oscillation center frequency fc of the carrier frequency 61 is fixed to the carrier of the received signal, the count value becomes " 0 " for 50mS. On the other hand, when the oscillation center frequency fc is higher than the fixed frequency, the coefficient value becomes positive, and when it is lower than the fixed frequency, it becomes negative. As a result, if the count value is positive for 50 mS, the oscillation center frequency fc of the carrier oscillator 61 is shifted low by a predetermined step width of about 1 Hz, and the operation is performed at the shifted oscillation center frequency fc. When the coefficient value is negative for 50 mS, the oscillation center frequency fc is shifted by a predetermined step width as high as about 1 Hz, and the operation is performed at the shifted oscillation center frequency fc. The control causes the oscillation center frequency fc of the carrier oscillator 61 to follow up the carrier of the received signal accurately.

In the flowchart of FIG. 6, the coefficient values coming from the low pass filters 64 and 65 are multiplied with each other, and a determination is made as to whether the multiplied output is negative or not (step 231). If the result of the determination indicates that the output is positive, the count COSCNT for the Costas loop is increased by " 1 " (step 232), and the oscillation frequency of the carrier generator 61 is increased by about 30 Hz with respect to the center frequency fc at that moment. A numerical control signal for lowering by the predetermined frequency width is formed (step 233). The numerical control signal is then supplied to a carrier oscillator 61 (step 234). If the result of the determination in step 231 indicates that the output is negative, the count COSCNT is increased by " 1 " (step 235), and the oscillating frequency of the carrier generator 61 is set to about 30 Hz with respect to the center frequency fc at that moment. A numerical control signal is formed to increase by frequency (step 236). The generated numerical control signal is then supplied to the carrier generator 61 (step 234).

Then, the value of the third timer C (initial value = 50) is decreased by "1" (step 237). A determination is then made as to whether or not the value of the third timer C is "0" (step 238). If the result of the determination indicates that the value of the third timer C is not “0”, this means that a predetermined time of 50 mS has not elapsed since the setting or changing the oscillation center frequency fc, and the operation is performed. Proceed to the flowchart of 7 degrees.

If the result of the determination in step 238 indicates that the value of the third timer C is "0", it means that 50 mS of time has already passed after setting or changing the oscillation center frequency fc, and then the count COSCNT is A determination is made as to whether or not "0" (step 239). When the count COSCNT is “0”, the oscillation center frequency fc is not changed, and the operation proceeds to step 244 where the third timer C is set to its initial value 50.

On the other hand, if the count COSCNT is not "0", a determination is made as to whether the count COSCNT is positive or not (step 240). If the determination result indicates a positive value, a control signal for lowering the oscillation center frequency fc of the carrier generator 61 by 1 Hz is formed (step 241) and supplied to the carrier generator 61 (step 243).

The operation then proceeds to step 244 where the third timer C is initialized and also to step 245, where the count COSCNT is set to "0" for the next count operation execution for 50mS. The operation then proceeds to the flowchart of FIG.

The flowchart of FIG. 7 shows the operation of the subtraction means 109 and the loop filter means 110. In this example, the code generator 51 is controlled in the following manner.

The difference between the initial data EA and the late data LA output from the adding means 105 is calculated as DI = EA-LA. If the difference DI is positive and larger than a predetermined value, this indicates that the initial code Me is of a higher correlation level, and a control operation for increasing the output phase of the code generator 51 is executed. On the other hand, if the difference DI is negative and larger than a predetermined value, this indicates that the late code Md is at a higher correlation level, and a control action is executed to delay the output of the code generator 51. When the difference DI is in a predetermined range with “0” at the center, the current state remains unchanged.

In the practical operation of FIG. 7, in this embodiment, the difference DI is represented by the count PNCNT of the counter associated with the control of the code generator 51. The above-mentioned predetermined values are regarded as counts + PN and -PN, and as shown in FIG. 8, the count PNCNT is preset to be + PN when greater than count + PN or -PN when smaller than count -PN.

In addition to the control, the chip speed (frequency) of the output code of the code generator 51 is checked based on the output frequency of the carrier generator 61 in the Costas loop 60. This check is performed by using a predetermined relationship between the output frequency of the clock generator 54 and the frequency of the carrier generator 61, which serve as drive circuits for the code generator 51. In particular, the predetermined oscillation frequency of the carrier generator 61 in the Costas loop 60 can be calculated when the feedback loop 50 is fixed. Conversely, if the Costas loop 60 is fixed, the set frequency of the code generator 51 can be calculated from the resolution of the carrier generator 61 in the Costas loop 60. Since the ratio of these two frequencies is 1: 1500, high-precision control of the frequency of the feedback loop 50 is possible with an improved accuracy of nearly 1500 times.

In the flowchart of FIG. 7, the difference between the initial data EA and the late data LA output from the adding means 105 is first calculated, and a determination is made whether the difference EA-LA is negative (step 251). As a result of such a determination, if the difference points to a positive, this means that the correlation level of the initial code Me is higher, so that the count PNCNT is increased by “1” (step 252). It is then determined whether the count PNCNT is equal to or not equal to the predetermined value + PN described above (step 253). And three control output values X, Y and Z for clock generator 54 are determined according to the result of such a determination.

If the result of the determination in step 253 means that the count PNCNT is + PN, the control output X is set to the control value Nowf so that the current output phase of the code generator 51 does not change, while the control outputs X and Z are code generators. A control value Fast for clock generator 54 is set to advance the output phase of 51 (step 254).

If the determination result at step 253 indicates that the count PNCNT is not equal to PN, this indicates that -PN < PNCNT < + PN. Therefore, the control output X is set to the control value Slow for the clock generator 54 to delay the output phase of the code generator 51, while the control output Y is set to the control value Nowf for maintaining the current state, Another output Z is set to the control value Fast for the clock generator 54 to advance the output phase of the code generator 51 (step 255).

If the determination result in step 251 indicates that the difference DI is negative, the count PNCNT is reduced by “1” because the correlation level of the late code Md is high (step 256). A determination is then made as to whether the count PNCNT is equal to the predetermined value -PN (step 257). If the determination result in step 257 indicates that count PNCNT is equal to -PN, control outputs X and Y are set to control value Slow for clock generator 54 to delay the output phase of the code generator 51. On the other hand, another control output X is set to the control value Nowf to maintain the current output phase of the code generator 51 (step 258). When the determination result at step 257 indicates that the count PNCNT is not equal to -PN, it indicates -PN < PNCNT < + PN, so the operation proceeds to step 255.

Subsequently, the output frequency of the code generator 51 in the feedback 50 is calculated by using the output frequency of the carrier generator 61 in the Costas loop 60, and the clock generator 54 with respect to the calculated output frequency. Is set in advance (step 258). With respect to the code generator 51, the current control value for the clock generator 54 is compared with such a preset control value and then it is determined whether the difference between them is within a predetermined range or not (step 260). If the determination result indicates that the difference is within a predetermined range, the control value Y is selected for the clock generator 54 (step 261). In fact, in the case of -PN < PNCNT < + PN, the current state remains without any change. On the other hand, in the case of PNCNT = + PN, the control value Fast is selected to advance the output phase of the code generator 51, and in the case of PNCT = -PN, the control value Slow in order to delay the output phase of the code generator 51. Is selected.

If the result of the determination at step 260 indicates that the difference exceeds a predetermined range, a determination is made as to whether the frequency shift is towards the higher or not depending on the positive or negative of the difference (step 262). If the determination result indicates that the frequency shift is toward the higher side, the control value X is selected as a value for controlling the clock generator 54 (step 263). In practice, in the case of -PN < PNCNT < + PN or PNCNT = -PN, the control value Slow is selected to delay the output phase of the code generator 51. On the other hand, in the case of PNCNT = + PN, the current output phase of the code generator 51 remains unchanged.

If the decision result in step 262 indicates that the frequency shift is toward the lower side, then the control output Z is selected as a value for controlling the clock generator 54 (step 264). When -PN < PNCNT < + PN or PNCNT = + PN, the control value Fast is selected so that the output phase of the code generator 51 is advanced. On the other hand, in the case of PNCNT = + PN, the output of the code generator 51 is kept in the current state.

The operations shown in the flowcharts of FIGS. 3-7 are repeated every millisecond.

It will be appreciated that the present invention is not limited to global positioning system (GPS) but can be applied to any spread spectrum signal receiving apparatus.

The modulation of the carrier is not limited to the quadrature phase modulation mentioned in the above embodiment, and it is apparent that various other modulation methods may be adopted. Moreover, in the above embodiment, data such as orbital parameters need not be exactly superimposed on the carrier, and the transmission of the carrier can also be used.

According to the present invention, as described above, the spread spectrum signal receiving apparatus can be configured by applying digital high density integration and software, so that low production, size reduction, low power consumption and high quality are realized.

According to the invention, in which a feedback loop is fitted to obtain a predetermined correlation between the pseudo-random noise code of the received signal and the output of the pseudo-random noise code generator, the intermediate frequency signal is encoded in binary, and the pseudo- Multiplied by the output of the random noise code generator, the balance modulators used in conventional devices are therefore no longer needed and eventually no circuit technology is needed to balance the modulators.

Moreover, the digital configuration allows the use of a numerically controlled oscillator (NCO) as a variable frequency oscillator without the need for a voltage controlled oscillator (VCO) previously used conventionally. This has the advantage of not requiring circuit technology to maintain the linearity of the voltage controlled oscillator.

In addition, due to the digital configuration described, stable reception is secured without the need for any analog circuit technology, so that interference or crosstalk between channels does not occur when the present invention is applied to a multi-channel receiver. In addition, the parameters determined by the loop filter can be easily changed by software application.

Claims (2)

A spread spectrum signal receiving apparatus comprising: a radio frequency processing circuit for converting a spread spectrum signal modulated by a pseudo random noise code into an intermediate frequency signal, and binary encoding the intermediate frequency signal supplied from the radio frequency processing circuit A binary coder, a pseudo random noise code generator, a code driver for controlling the phase and chip speed of the output pseudo random noise code from the pseudo random noise code generator, and the binary signal and the pseudo random noise code generator from the binary coder Numerical control for outputting a first multiplier multiplying the output pseudo random noise code obtained from the first multiplier and a first and second carrier signal having a π / 2 phase difference therebetween and following the frequency-converted carrier signal included in the intermediate frequency signal. Oscillator and the first multiplier First and second multipliers for multiplying the first and second carrier signals having a π / 2 phase difference with each other by an output signal, and a first counter configured to receive output signals of the second and third multipliers And in response to the count outputs of the second low pass filter and the second and third low pass filters, the frequency and phase of the output carrier signal of the numerically controlled oscillator adjust the frequency and phase of the carrier component included in the intermediate frequency signal. Has a function of generating a control signal for controlling the numerically controlled oscillator in a manner to be followed, and the phase of the output pseudo random noise code from the pseudo random noise code generator is equal to the phase of the pseudo random noise code included in the spread spectrum. Generating a control signal based on the count output that controls the code driver in a matching manner. An apparatus for receiving spread spectrum signals, comprising a microcomputer having a function. A spread spectrum signal receiving apparatus comprising: a radio frequency processing circuit for converting a spread spectrum signal modulated by a pseudo random noise code into an intermediate frequency signal, and binary encoding the intermediate frequency signal supplied from the radio frequency processing circuit A binary coder, a pseudo random noise code generator, a code driver for controlling the phase and chip speed of the output pseudo random noise code from the pseudo random noise code generator, the binary signal and the pseudo random noise code from the binary coder A numerical value for outputting a first multiplier multiplying the output pseudo random noise code obtained from the generator and a first and second carrier signal having a π / 2 phase difference therebetween and following the frequency-converted carrier signal included in the intermediate frequency signal; A control oscillator and the first multiplier First and second multipliers for multiplying the first and second carrier signals having a π / 2 phase difference with each other by an output signal, and a first counter configured to receive output signals of the second and third multipliers And first and second absolute value detecting means for detecting an absolute value of the second low pass filter and the count outputs of the second and third low pass filters, and adding means for adding the outputs of the absolute value detecting means to each other. And means for adding a control signal for controlling the code driver in such a manner that the phase of the output pseudo random noise code from the pseudo random code generator matches the phase of the pseudo random noise code included in the received spread spectrum signal. And spreading means for generating based on the output of the spread spectrum signal.