JP2689977B2 - Spread spectrum signal receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for receiving a spread spectrum signal such as a satellite signal used in a system for measuring the position of a moving object.

[0002]

2. Description of the Related Art A system for measuring the position of a mobile object using a plurality of artificial satellites orbiting the earth has been proposed. In this type of system, a satellite signal is subjected to spread spectrum modulation. ing. For example, GPS (Global
In a position measurement system called Positioning System, a satellite signal is composed of 50 bps orbit parameter data (orbit data indicating the time and position of the satellite), a chip speed of 1.023 MHz, and a pseudo-noise code (for example, a GOLD code) having a period of 1 msec. Is spread-spectrum modulated by
Two carrier waves of 1575.42 MHz and 1227.6 MHz are transmitted after being subjected to quadrature phase modulation (two-phase PSK modulation).

[0003] A GPS receiver receives signals from at least three satellites, performs tracking and despreading processing on the carrier, demodulates orbit parameter data of each satellite, and obtains the arrival time of each signal. Data (the distance between the satellite and the user is obtained from the arrival time of the satellite signal) and the satellite position are obtained. The user's position can be determined three-dimensionally by drawing a sphere centered on each satellite with the measured position of the satellite as the origin, the measured distance as the radius, and the intersection.

FIG. 9 shows a configuration example of a conventional GPS receiver. The signal received by the antenna 1 is transmitted to a high-frequency processing circuit 2
And the carrier is 10.7 MHz (the signal bandwidth is 10.7 ± 1.
023 MHz).

[0005] The intermediate frequency signal is supplied to a reception demodulation unit as described below. This receiving / demodulating unit includes a feedback loop for despreading for demodulating spread spectrum modulation and a feedback loop for demodulating two-phase modulation based on orbit parameter data bits.

In the case of this example, a so-called tau dither tracking method is used in the feedback loop of the despread demodulation. That is, reference numeral 20 denotes a code generator for generating a pseudo-noise code on the receiver side, which generates a leading (early) code Me and a lagging (rate) code Md having a phase difference of one chip time. The early code Me and the rate code Md from the code generator 20 are supplied to a leading / lagging code selector 21, and the code selector 21 is switched by an early rate switch 22 every 1 msec. A synthetic pseudo-noise code is obtained from the selector 21 and supplied to the balanced modulator 3. Then, the intermediate frequency signal from the high frequency processing circuit 2 is supplied to the balanced modulator 3 and is balanced-modulated by the synthesized pseudo-noise code.

The code generator 20 is controlled by a clock whose phase and frequency are controlled as described later from a clock generator 23 as a code driving device to generate the phase and frequency (chip) of pseudo noise codes Me and Md of early and rate. (Speed) is controlled to match the phase and frequency (chip speed) of the pseudo-noise code included in the intermediate frequency signal from the high-frequency processing circuit 2. Then, as a result of the closed loop control, a de-spread signal Si is obtained from the balanced modulator 3.

As a feedback loop for demodulating data bits, a Costas loop is used in this example. The Costas loop includes a carrier generator 4 comprising a voltage-controlled variable frequency oscillator (hereinafter referred to as VCO) and a 90 ° phase shifter, and first and second analog multipliers 5 and 6.
, Low-pass filters 7 and 8, a third analog multiplier 9, and a loop filter 10.

The carrier generator 4 outputs first and second quadrature carrier signals (cos ωt and si
nωt), which are supplied to first and second multipliers 5 and 6, respectively, and multiplied by the despread intermediate frequency signal (± Acos (ωt + φ)) from the balanced modulator 3, respectively. The outputs of the first and second multipliers 5 and 6 are passed through low-pass filters 7 and 8,
Is supplied to the multiplier 9 for multiplication. The output level of the third multiplier 9 reflects the phase difference between the carrier component of the received signal and the carrier from the carrier generator 4. The output of the multiplier 9 is supplied to the carrier generator 4 via the loop filter 10, whereby the VCO of the carrier generator 4 is controlled, and the phase of the output carrier signal of the carrier generator 4 is changed in the signal Si. Is made to follow the carrier component.

The outputs (± 1 / 2Acosφ) of the first and second low-pass filters 7 and 8 of the Costas loop are used.
And ± １ ／ sin φ) are supplied to the square detectors 11 and 12, respectively, and are square-detected. Then, the respective square detection outputs are supplied to the adder 13 and added. The added output of the adder 13 indicates the correlation level between the received pseudo noise code and the pseudo noise code from the code generator 20.

The added output of the adder 13 is supplied via an analog switch 14 to an early data holding unit 15 and a rate data holding unit 16 each composed of an integrator. The analog switch 14 is an early rate switch 2
2 is switched in synchronization with the switching of the lead / lag code selector 21 by the switching signal from 2. Therefore, the early data holding unit 15 accumulates the correlation level output when the pseudo noise code from the code generator 20 advances and the code is Me, and the rate data holding unit 16 stores the pseudo noise code from the code generator 20. Is the delay code Md, the correlation level output is accumulated.

The correlation level outputs of the early data holding unit 15 and the rate data holding unit 16 are supplied to a subtractor 17 composed of, for example, a differential amplifier, and a difference between the two correlation level outputs is obtained. The output of this difference reflects the phase error between the received pseudo-noise code and the pseudo-noise code from code generator 20. The output of this difference is
The pseudo-noise code output from the code generator 20 is supplied to the VCO of the clock generator 23 as a code driving device via the control unit 8 so as to follow the received pseudo-noise code as described above.

The correlation level output from the adder 13 is supplied to a search / synchronization detector 19.
In the phase pull-in process of the pseudo-noise code by the synchronization detector 19, the frequency of the output clock from the clock generator 23 is greatly changed until a predetermined correlation with the received pseudo-noise code is obtained. The frequency and phase of the pseudo-noise code from the detector 20 are greatly moved to perform the search. Then, once the correlation is obtained, the search is stopped, and thereafter, the clock generator 23
Is controlled by the output of the loop filter 18.

As described above, the received signal subjected to the spread spectrum modulation is demodulated by the despreading feedback loop.
Also, the data bits are demodulated by the Costas loop. Then, the demodulated output of the data bits is obtained from the low-pass filter 7, and the data bits are supplied to a data demodulation circuit (not shown) to demodulate the orbit parameter data.

[0015]

However, the above-mentioned conventional spread spectrum signal receiving apparatus requires a balanced modulator 3 to obtain a correlation with a pseudo-noise code on the receiver side. There is a problem that an analog circuit technique for maintaining the balance of the device 3 is required.

Further, the carrier generator 4 and the clock generator are provided with VCOs, and circuit technology and circuit elements for maintaining the linearity of each VCO are required. For this reason, the receiving device is complicated in configuration, expensive, and
The device had become large.

Furthermore, a despreading feedback loop and data
The feedback loop for demodulating bits has a problem that parameters are fixed by circuit elements or components, and it is not easy to change parameters for control.

In view of the above, an object of the present invention is to improve the above points by digital integration and software.

[0019]

In order to achieve the above object, a spread spectrum signal receiving apparatus according to the present invention converts a spread spectrum signal in which a carrier is spread spectrum modulated by a pseudo noise code into an intermediate frequency signal. A high frequency processing circuit, a binarization circuit for binarizing the intermediate frequency signal from the high frequency processing circuit, a pseudo noise code generator, an output pseudo noise code phase of the pseudo noise code generator, and a chip speed. A code driving device for controlling, a first multiplication circuit for multiplying the binarized signal from the binarization circuit by the pseudo noise code output from the pseudo noise code generator, and the intermediate frequency signal in the intermediate frequency signal. A first that follows the included low-frequency-converted carrier wave and has a phase difference of π / 2 from each other.
And a numerically controlled variable frequency oscillator for outputting a second carrier signal; an output signal of the first multiplication circuit;
Second and third multiplication circuits for respectively multiplying the first and second carrier signals having phases different from each other by π / 2, and output signals of the second and third multiplication circuits are supplied. A first and a second low-pass filter, and the first
And a second low-pass filter output, the numerical control variable frequency oscillator so that the frequency and phase of the output carrier signal of the numerical control variable frequency oscillator follow the carrier component included in the intermediate frequency signal. The phase of the pseudo noise code output from the pseudo noise code generator is based on the outputs of the first control signal generation circuit that generates a control signal to be controlled and the first and second low pass filters, and the spread spectrum signal. And a second control signal generation circuit for generating a control signal for controlling the code driving device so as to match the phase of the pseudo-noise code included in the above.

According to the configuration of the present invention, the received spread spectrum signal is converted into an intermediate frequency signal and then converted to an intermediate frequency signal.
The feedback loop for the quantification and subsequent despreading and the demodulation of the data bits are digitally configured. The control signal of each feedback loop can be formed by software.

Therefore, a conventional balanced modulator is not required, and a numerically controlled oscillator is used as the variable frequency oscillator. Therefore, there is no need to use a conventional VCO, and a simple and inexpensive spectrum spreader is used. It becomes possible to realize a signal receiving device.

[0022]

FIG. 1 is a block diagram showing an embodiment of a spread spectrum signal receiving apparatus according to the present invention.
This example is an example in the case of a GPS receiving device.

The satellite signal (spread spectrum signal) received by the antenna 31 is supplied to a high frequency processing circuit 32. The output of the reference oscillator 33 composed of a crystal oscillator of 18.414 MHz is supplied to the local oscillation circuit 34, whereby a local oscillation output having a fixed output frequency and a fixed frequency ratio is obtained.

The local oscillation output is supplied to the high frequency processing circuit 32, and the satellite signal is converted to the first intermediate frequency 19.437.
The low frequency is converted to MHz, and further the low frequency is converted to the second intermediate frequency signal Sif having the second intermediate frequency of 1.023 MHz by the oscillation output from the reference oscillator 33.

The second intermediate frequency signal Sif from the high frequency processing circuit 32 is supplied to a binarization circuit 35, and is binarized by comparing the level with a predetermined threshold value.

The binarized output Sd of the binarizing circuit 35 is
A signal multiplier 36 composed of an exclusive OR circuit
Supplied to

In this example, similarly to the above-described example, the feedback loop 50 for despreading demodulation uses a so-called tau dither tracking method, and the feedback loop 60 for demodulating data bits is used. , And Costas loops, which are digitized, and whose control signals are formed by the microcomputer 100 by software processing.

That is, in a feedback loop 50 for despread demodulation, reference numeral 51 denotes a code generator for generating a pseudo-noise code on the receiver side, which is one chip time (a GPS satellite signal has an orbital parameter of 50 bps). The data generates an early code Me and a late (rate) code Md having a phase difference of (spread spectrum modulation by a pseudo-noise code having a chip speed of 1.023 MHz and a period of 1 msec).

The early code Me from the code generator 51
And the rate code Md are supplied to a leading / lagging code selector 52, and this code selector 52
The signal is switched every 1 msec by the switching signal from 3 to obtain a synthesized pseudo-noise code from the code selector 52, which is supplied to the multiplier 36. The multiplier 36 multiplies the synthesized pseudo-noise code by the binarized intermediate frequency signal Sd from the binarization circuit 35.

In this case, the clock generator 54 for generating a drive clock for controlling the phase and frequency (chip speed) of the output code of the code generator 51 is constituted by a numerically controlled variable frequency oscillator (hereinafter referred to as NCO). Is done. The clock generator 54 is supplied with a reference clock from the reference oscillator 33. The clock generator 54 forms a drive clock for the code generator 51 from the reference clock under the control of the microcomputer 100.

In the code generator 51, the phase and frequency of the pseudo noise code of the early and rate are controlled by the clock whose phase and frequency are controlled from the clock generator 54. As a result, the pseudo noise code output from the code generator 51 is controlled so as to coincide with the phase and frequency of the pseudo noise code included in the intermediate frequency signal Sd from the binarization circuit 35, whereby despreading is performed. You.

The Costas loop of the feedback loop 60 for demodulating data bits includes a carrier generator 61 comprising an NCO and a 90 ° phase shifter, and first and second multiplications comprising an exclusive OR gate. Vessels 62 and 63;
It comprises low-pass filters 64 and 65 each composed of a counter, and a microcomputer 100 that generates a control signal to the carrier generator 61. A reference clock from the reference oscillator 33 is supplied to the carrier generator 61, and the carrier generator 61 generates a carrier according to the control of the microcomputer 100 from the reference clock.

The microcomputer 100 executes each function as shown in FIG. 1 as a function block by the program software. That is, the processing function of the microcomputer 100 will be described with reference to the functional block of FIG. 1. An output corresponding to the phase difference between the carrier component and the carrier from the carrier generator 61 is obtained. The loop filter means 102 forms a signal for controlling the carrier generator 61 from the multiplied output from the multiplication means 101 and supplies the signal to the carrier generator 61. The above constitutes a part of the Costas loop 60.

Next, absolute value detection means 103 and 104
The absolute value detection is performed on the count value outputs from the low-pass filters 64 and 65, respectively, and the detection outputs are added by the adding means 105. From the adding means 105, a signal indicating the correlation level between the pseudo noise code from the code generator 51 and the pseudo noise code of the received signal is obtained. Here, the outputs of the low-pass filters 64 and 65 are subjected to absolute value detection without square detection, for the following reason.

That is, in the conventional analog configuration shown in FIG. 9, the correlation outputs of the low-pass filters 7 and 8 are:
If the correlation is obtained, the broken lines (a) and (b) in FIG.
As shown by the equation, there is a relationship between cosine wave and sine wave. Therefore, when these are square-detected and added to each other, a signal of a certain level is obtained. However, in the case of this example, the outputs of the low-pass filters 64 and 65 are binary signals. The correlation outputs of the low-pass filters 64 and 65 are
When the correlation is obtained, a solid line (c) in FIG.
As shown in FIG. For this reason, when the outputs of the low-pass filters 64 and 65 are square-detected and added in the same manner as in the related art, the added output is, as shown in FIG. Therefore, it is difficult to determine whether the correlation is obtained.

On the other hand, after the absolute value detection as in this example, the added output has a constant output level as shown in FIG. 2C, and it is possible to reliably determine whether or not the correlation is obtained.

The output of the adding means 105 is switched to the switching means 106 in synchronization with the selector 52 in response to a switching signal from the early rate switch 53, and is stored in the early data holding means 107 and the rate data holding means 108. Is done. Practically, the switching means 106 is unnecessary, and the memory area of the early data and the memory area of the rate data are selected in accordance with the switching signal from the early rate switch 53, and these early data and rate data are stored in each area. To accumulate. Then, the output of the early data holding means 107 and the output of the rate data holding means 108 are subtracted by the subtracting means 1
09 to be subtracted. Then, the result of the subtraction is supplied to the loop filter means 110, and a numerical control signal for controlling the phase of the driving clock of the code generator 51 which is the output of the clock generator 54 is formed.

The output of the adding means 105 is supplied to the search signal generating means 111 and also to the synchronizing signal detecting means 112. The search signal generating means 111
Until a predetermined correlation is obtained, a search signal for performing a search is generated by sliding the output code of the code generator 51 for one cycle. The synchronization detecting means 112 monitors the added output and performs a search or the loop filtering means 11
It is determined whether the phase control is to be performed based on the output of 0, and a switching signal is generated by the switching means 113 for switching between the output of the search signal generating means 111 and the output of the loop filter means 110. The output of the switching means 113 is supplied to the clock generator 54.

Next, the actual processing flow of the microcomputer 100 will be described with reference to the flowcharts of FIGS. 3 to 7 in which reference numerals of the respective functional means in FIG. 1 are compared. The operations shown in FIGS. 3 to 7 are repeated every 1 msec which is the chip speed of the pseudo noise code. Therefore, the low-pass filters 64 and 65 having the counter configuration are
It is reset every 1 ms.

First, referring to FIG. 3, I data from the low-pass filter 64 having a counter configuration is fetched (step 201), and its absolute value is obtained (step 2).
02). Similarly, a low-pass filter 65 having a counter configuration is used.
(Step 203), and its absolute value is obtained (step 204).

Next, the absolute value of I data obtained in step 202 and the absolute value of Q data obtained in step 204 are added to obtain an addition result A (step 205). And
Referring to the switching signal from the early rate switch 53,
It is determined whether or not the current mode is the early mode in which the code generator 51 outputs the early code Me (step 20).
6). As a result of the determination, if the mode is the early mode, the addition result A is written to, for example, the early data storage area of the RAM (step 207). If the rate mode is the rate mode in which the rate code Md is output from the code generator 51, the addition result A is written into, for example, a rate data storage area of a RAM (step 208).

Next, the flow moves to the flowchart of FIG. 4 corresponds to the operation of the portion of the synchronization detecting means 112 in FIG. That is, first, it is determined whether or not the addition result A obtained in step 205 exceeds a predetermined threshold value (step 211). This is to determine whether or not the feedback loop 50 has a correlation between the pseudo noise code of the received signal and the pseudo noise code from the code generator 51.

As a result of the determination, if it is determined that the correlation is obtained, the first timer S is set to, for example, "10" (10 m
(Step 212) and the second timer P is set to "30000" (30 seconds) (step 213) to form a control signal of the Costas loop 60 of FIG. 6 described later. Move on to

If it is determined in step 211 that the correlation is not obtained, the first timer S
Is reduced by “1” (step 214), and it is determined whether or not the value of the timer S is “0” (step 215).
If the result of the determination is that the timer S is not "0", the flow moves to the flowchart of FIG.

As a result of the determination, the value of the timer S becomes "0".
If not, the value of the first timer S is set to "1" (step 216), and it is determined whether the value of the second timer P is "0" (step 217). Timer P value is "0"
If so, the procedure moves to the flowchart of the operation of the search signal generating means 111 and the loop filter means 102 at the time of search in FIG. If the value of the timer P is not "0", the value of the timer P is reduced by "1" (step 218), and the loop filter means 11 of the feedback loop 50 of FIG.
Move to the flowchart for performing the operation of 0.

In this case, if the first timer S detects once that the correlation has been obtained (correlation lock) in the feedback loop 50, the flowchart of FIG. 4 continues ten times, that is, continuously for 10 ms. This is to prevent detection of non-correlation unless it is determined in step 211 that correlation has not been obtained.

Further, once the feedback loop 50 has detected the correlation lock, the timer P determines whether or not the feedback loop 50 has detected the non-correlation (determined that the correlation has not been continuously obtained for 10 ms). The state is held for the time set by the timer P, for example, 30 seconds (the control of the output of the carrier generator 61 by the loop filter 102 in the feedback loop 60 and the output of the clock generator 54 by the loop filter 110 in the feedback loop 50). The phase and frequency control is performed.). If it is detected that the correlation has not yet been obtained even after 30 seconds have elapsed, the processing shifts to the correlation search flowchart of FIG.

That is, once it is detected that the correlation is locked in the feedback loop 50, the correlation is not unlocked immediately even if it is determined in step 211 that the correlation is not obtained. Does not move to correlation search. For this reason, in a state where the correlation is not actually broken, for example, an obstacle such as an airplane temporarily enters between the satellite and the receiving device, the correlation non-locking occurs for an instant for some reason. Even if it is detected, the operation is not shifted to a correlation search operation which takes a relatively long time, which will be described later. Thus, even if there is an instantaneous reception failure, the feedback loop 50 is hardly affected by the influence, and stable reception can be performed.

Next, a flow chart of a part corresponding to the search signal generating means 110 and the loop filter means 102 at the time of searching in FIG. 5 will be described.

The search in this example is performed as follows.
That is, the received signal exists in the range of 1.023 MHz ± 15 kHz when viewed from the intermediate frequency signal Sif. Therefore, a correlation can be obtained by searching within this range. However, the bandwidth of the loop filter means 102 is generally only in a frequency range smaller than the search range, in this example, ± 350 Hz.
It can only be done in this loop filter bandwidth range.

Therefore, in this example, the carrier generator 6
At the center frequency fc where the output of 1 is present, one cycle of the early and rate codes from the code generator 51 is slid. If the correlation cannot be obtained by the one-cycle slide control, the oscillation center frequency fc of the carrier generator 61 is shifted by 700 Hz, and the slide control of the code generator 51 is performed again. This is sequentially performed in the range of ± 15 kHz. The change of the frequency fc which differs by 700 Hz is performed alternately in the plus direction and the minus direction.

That is, in FIG. 5, since the correlation is not obtained in the feedback loop 50, the correlation unlocked state is initialized (step 221). next,
It is determined whether the sliding (phase control) for one cycle of the early and rate codes from the code generator 51 has been completed (step 222). For example, it takes a predetermined time, for example, 4 seconds in this example to perform the correlation search by outputting all the periods of the pseudo noise code from the code generator 51. Therefore, it is determined whether the slide for one period is completed. The judgment is made by monitoring the 4-second timer.

As a result of the determination in step 222, if 4 seconds have elapsed, it means that the correlation was not obtained even though the output of the code generator 51 was searched for one cycle.・ Loop carrier generator (NC
O) A numerical control signal for changing the oscillation center frequency fc of 61 by a predetermined step width frequency Δf = 700 Hz is formed (step 223). Then, the numerical control signal is supplied to the carrier generator 61 (step 224).
Thereafter, a numerical control signal for sliding the output of the code generator 51 once again is formed, and the control signal is supplied to the clock generator 54 (step 225).

If the result of the determination in step 222 is that four seconds have not elapsed, it means that the one-cycle sliding of the output of the code generator 51 has not yet been completed, so the carrier generator of the Costas loop While leaving the oscillation center frequency fc of 61 as it is, jumping to step 225,
The output of the code generator 51 is continuously supplied to the clock generator 54 with a numerical control signal for sliding the output by one cycle. After step 225, the process returns to step 201 in FIG.
reference).

As a result of the above correlation search, a correlation lock is always detected somewhere.

When it is detected in step 211 in FIG. 4 that the correlation has been obtained, the process proceeds to the flow chart of the loop filter means 102 in FIG. 6 for finely controlling the carrier generator 61 as described above. . The operation of this flowchart, that is, the control of the carrier generator 61 in the correlation locked state is performed as follows.

That is, first, the carrier generator 61 is set to the oscillation center frequency fc in which the correlation is obtained. The output of the multiplying means 101, which is an error signal which is a reference signal for controlling the carrier generator 61, is referred to. When the multiplied output is positive (indicating that the oscillation frequency is shifted to a higher one), The oscillation frequency of the generator 61 is
A predetermined frequency width, for example, 30 with respect to the center frequency fc at that time,
Hz. Conversely, when the multiplication output is negative (indicating that the oscillation frequency is shifted to the lower side), the oscillation frequency of the carrier generator 61 is lowered by a predetermined frequency width, for example, 30 Hz from the center frequency fc at that time. This frequency shift is performed every time the operation of this flowchart is performed, that is, every 1 ms. And this frequency shift,
For example, it is performed for 50 ms, and the number of positive and negative times of the multiplication output during the 50 ms is counted, and both numbers are compared. This one
If the multiplication output is positive, the count should be up, and if the multiplication output is negative, the count should be down.

If the oscillation center frequency fc of the carrier generator 61 at that time is locked to the carrier of the received signal, the count value for 50 ms becomes "0", while the oscillation center frequency fc becomes "0". When the frequency fc is higher than the lock frequency, the count value becomes positive, and when the oscillation center frequency fc is lower than the lock frequency, the count value becomes negative. Therefore, when the count value for 50 ms is positive, the oscillation center frequency fc of the carrier generator 61 is shifted lower by a predetermined step width, for example, 1 Hz, and the same operation is performed at the shifted oscillation center frequency fc. When the count value for 50 ms is negative, the oscillation center frequency fc is shifted higher by a predetermined step width, for example, 1 Hz, and the same operation is performed at the shifted oscillation center frequency fc. By the above control operation, the carrier generator 6
Fine tracking control is performed on the carrier of the received signal having the oscillation center frequency fc of 1.

That is, in FIG. 6, the count value outputs from the low-pass filters 64 and 65 are multiplied by each other, and it is determined whether or not the multiplied output is a negative value (step 231). As a result of the determination, when it is determined to be positive, the count value COSC for the Costas loop
NT is incremented by "1" (step 232),
A numerical control signal for lowering the oscillation frequency of the carrier generator 61 by a predetermined frequency width, for example, 30 Hz, from the center frequency fc at that time is formed (step 233), and this is supplied to the carrier generator 61 (step 234). Also,
As a result of the determination in step 231, when it is determined that the value is negative, the count value COSCNT is down-counted by "1" (step 235), and the oscillation frequency of the carrier generator 61 is changed with respect to the center frequency fc at that time. A numerical control signal for lowering by the predetermined frequency width, that is, 30 Hz is formed (step 236), and supplied to the carrier generator 61 (step 234).

Next, the value of the third timer C (the initial value is 50) is reduced by "1" (step 237). And
It is determined whether or not the value of the timer C is "0" (step 238). As a result of this determination, the value of the timer C is "0"
If not, that is, if 50 milliseconds have not yet elapsed since the oscillation center frequency fc was set or changed, the flow shifts to the next flowchart in FIG.

When it is determined in step 238 that the value of the timer C is "0", that is, 50 m after the oscillation center frequency fc is set or changed.
When the second has elapsed, it is determined whether or not the count value COSCNT is “0” (step 239). And the count value COSC
If NT is "0", the process proceeds to step 244 while maintaining the oscillation center frequency fc, and the value of the timer C is set to the initial value =
Set to 50.

On the other hand, if the count value COSCNT is not "0", it is determined whether or not the count value COSCNT is positive (step 240). As a result of the determination, when it is determined to be positive, the oscillation center frequency f of the carrier generator 61 is determined.
A control signal for lowering c by 1 Hz is formed (step 24).
1) This is output to the carrier generator 61 (step 243). If it is determined in step 240 that the signal is negative, a control signal for raising the oscillation center frequency fc of the carrier generator 61 by 1 Hz is formed (step 242), and the control signal is output to the carrier generator 61 (step 242). Step 243).

Thereafter, the flow advances to step 244 to set the initial value of the timer C, and then to step 245, where the count value COSCNT is set to "0" for counting for the next 50 ms. Then, the process proceeds to the next flowchart in FIG.

The flowchart shown in FIG.
And the operation of the portion of the loop filter means 110. In the case of this example, the control of the code generator 51 is performed as follows.

That is, the adding means 105 which is a correlation output.
DI between early data EA and rate data LA
= EA-LA, and when the value of the difference DI is positive and exceeds a predetermined value, that is, when the Early code Me has a stronger correlation, the output phase of the code generator 51 is advanced. When the value of the difference DI is negative and exceeds a predetermined value, that is, when the correlation of the rate code Md is stronger, the output of the code generator 51 is controlled to be delayed. When the value of the difference DI is within a predetermined range around “0”, the state is maintained as it is.

In the actual operation of FIG. 7, in this case, the count value PNCNT of the counter related to the control of the code generator 51 is considered as the difference DI. The predetermined values are count values + PN and -PN. As shown in FIG. 8, the count value PNCNT is always + PN when the count value is larger than + PN, and is always -PN when it is smaller than the count value -PN. It is set so that

In addition to the above phase control, the code generator 51
Is checked on the basis of the output frequency of the carrier generator 61 of the Costas loop 60. This utilizes the fact that a predetermined relationship is established between the output frequency of the clock generator 54, which is the drive circuit of the code generator 51, and the frequency of the carrier generator 61. That is, when the feedback loop 50 is locked, the frequency at which the carrier generator 61 of the Costas loop 60 should oscillate can be obtained by calculation. Conversely, if the Costas loop 60 is locked, the set frequency of the code generator 51 can be obtained with the resolution of the carrier generator 61 of the Costas loop 60. That is, since the frequency ratio between the two is 1: 1500, about 15
The frequency control of the feedback loop 50 can be performed with a precision of 00 times.

That is, in the flowchart of FIG. 7, first, the early data E which is the output of the adding means 105 is output.
A and the difference between the rate data LA and the difference EA−LA
It is determined whether or not is negative (step 251). As a result of the determination, if the difference is positive, the correlation level at the time of the early code Me is larger, so that the count value PNCNT is set to “1”.
Is incremented by one (step 252). And
It is determined whether or not the count value PNCNT is equal to the predetermined value + PN (step 253). Then, according to the result of the determination, the control output value to the clock generator 54 is changed to X,
Three types of Y and Z are prepared.

Then, as a result of the determination in step 253,
When the count value PNCNT = + PN, the control output value X is a control value Nowf for keeping the output phase of the code generator 51 as it is, and the control output values Y and Z advance the output phase of the code generator 51. The control value Fast of the clock generator 54 to be set is set (step 254).

If the result of determination in step 253 is that count value PNCNT ≠ PN, then -PN <PNCNT
<+ PN, the control output value X is
Is used as the control value Slow of the clock generator 54 for delaying the output phase of the clock generator 54, the control output value Y is used as the control value Nowf to keep the state as it is, and the control output value Z is used to advance the output phase of the code generator 51. Clock generator 5
A control value Fast of 4 is set (step 255).

If it is determined in step 251 that the difference DI is negative, the correlation level for the rate code Md is larger, so that the count value PNCNT
Is down-counted by "1" (step 256).
Then, it is determined whether or not the count value PNCNT is equal to the predetermined value -PN (step 257). Then, as a result of the determination in step 257, the count value PNCNT = -P
When N, the control output values X and Y are
A clock generator 54 for delaying the output phase of 1
, And the control output value Z is calculated by the code generator 5
The control value Nowf for keeping the output phase of No. 1 as it is is set (step 258). If the result of determination in step 257 is that count value PNCNT ≠ −PN,
Since −PN <PNCNT <+ PN, the process proceeds to step 255.

Next, the output frequency of the code generator 51 of the loop 50 is calculated using the output frequency of the carrier generator 61 of the Costas loop 60, and the control value of the clock generator 54 for the output frequency value is set. (Step 258). Then, the control value is compared with the current control value of the clock generator 54 for the code generator 51,
It is determined whether the difference is within a predetermined range (step 2).
60). If the difference is within the predetermined range, the control value for the clock generator 54 is set to the control value Y (step 261). That is, -PN <PNCNT
<+ PN, keep the same state
When T = + PN, the control value Fast is used to advance the output phase of the code generator 51, and the count value
When PNCNT = −PN, the control value Slow is set to delay the output phase of the code generator 51.

If it is determined in step 260 that the difference is out of the range, it is determined whether the frequency is shifted to a higher frequency depending on whether the difference is positive or negative (step 262). . As a result of the determination, if it is shifted to the higher one, the control value for the clock generator 54 is set to the control value X (step 263). That is, -PN <
When PNCNT <+ PN and when PNCNT = −PN, the control value Slow is set to delay the output phase of the code generator 51. When PNCNT = + PN, the output phase of the code generator 51 remains unchanged.

If it is determined in step 262 that the frequency is shifted to a lower frequency, the control value for the clock generator 54 is set to the control value Z (step 264). That is, -PN <PNCNT <+ P
When N and PNCNT = + PN, a control value Fa for causing the output phase of the code generator 51 to advance.
st. When PNCNT = −PN, the output phase of the code generator 51 is kept as it is.

The flow charts shown in FIGS.
It is repeated every second.

The present invention can be applied not only to a position measuring system such as a GPS, but also to all spread spectrum signal receiving apparatuses.

Further, the modulation method of the carrier wave is not limited to the quadrature phase modulation as in the above-described example, and it is needless to say that various modulation methods can be used. Further, it is not necessary to superimpose data such as the trajectory parameter data in this example on the carrier, and only the carrier may be transmitted.

[0078]

As described above, according to the present invention, a receiving apparatus for a spread spectrum modulated signal can be configured by digital integration and software, thereby reducing cost, size, and power consumption. , High quality can be realized.

Further, according to the present invention, in the feedback loop for correlating the pseudo-noise code of the received signal with the output of the pseudo-noise code generator of the receiving apparatus, the intermediate frequency signal is binarized to generate the pseudo-noise code. Since the output is multiplied by the output of the code generator, there is no need for a conventional balanced modulator, and therefore, no circuit technique for maintaining the balance of the balanced modulator is required.

Also, because of the digitized configuration, an NCO can be used as the variable frequency oscillator, and the VC
There is an advantage that there is no need to use O and no circuit technology for maintaining the linearity of the VCO is required.

Further, since the digital configuration is used as described above, the analog circuit technology as described above is not required, and
Stable reception is possible, and when applied to a multi-channel receiver, there is no interference and variation between channels. Further, various parameters determined by the loop filter can be easily changed by software.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a spread spectrum signal receiving apparatus according to the present invention.

FIG. 2 is a diagram illustrating a level output according to a correlation between a pseudo-noise code in a received signal and a pseudo-noise code on the receiving device side.

FIG. 3 is a flowchart of a part of the operation of the microcomputer 100 of the embodiment of FIG. 1;

FIG. 4 is a flowchart of an operation of a part of the microcomputer 100 of the embodiment of FIG. 1;

FIG. 5 is a flowchart of a part of the operation of the microcomputer 100 of the embodiment of FIG. 1;

FIG. 6 is a flowchart of an operation of a part of the microcomputer 100 of the embodiment of FIG. 1;

FIG. 7 is a flowchart of a part of the operation of the microcomputer 100 of the embodiment of FIG. 1;

FIG. 8 is a diagram for explaining the operation principle of the flowchart of FIG. 7;

FIG. 9 is a block diagram of an example of a conventional spread spectrum signal receiving apparatus.

[Explanation of symbols]

32 ... RF processing circuit, 33 ... Reference oscillator, 35 ... Binarization circuit, 36 ... Signal multiplication circuit, 50 ... Feedback loop for despreading, 51 ... Code generator for generating pseudo noise code on the receiving device side, 54: a clock generator (NCO) for driving the code generator 51, 60: Costas loop, 61
... Carrier generators (NCO), 62, 63 ... signal multiplying circuits, 64, 65 ... low-pass filters, 100 ... microcomputer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Eiichiro Morinaga 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Within Sony Corporation (56) References JP-A-61-57142 (JP, A) JP-A 2-14635 (JP, A) JP-A-2-301336 (JP, A) JP-A 64-24532 (JP, A) JP-A 64-81538 (JP, A)

Claims (1)

(57) [Claims] 1. A high-frequency processing circuit for converting a spread-spectrum signal in which a carrier is spread-spectrum-modulated by a pseudo-noise code into an intermediate frequency signal, and a binarizing means for binarizing the intermediate frequency signal from the high-frequency processing circuit.
A binarizing circuit, a pseudo noise code generator, a code driving device for controlling the phase and chip speed of the output pseudo noise code of the pseudo noise code generator, and a binarizing signal from the binarizing circuit. And a pseudo-noise code output from the pseudo-noise code generator, a first multiplication circuit, which follows a low-frequency-converted carrier wave included in the intermediate frequency signal, and has a phase of π / 2 with respect to each other. A numerically controlled variable frequency oscillator for outputting first and second carrier signals different from each other, an output signal of the first multiplication circuit, and the first and second phases different from each other in phase by π / 2. Carrier signal and
Second and third multiplication circuits for multiplying, respectively, first and second low-pass filters to which output signals of the second and third multiplication circuits are supplied, and outputs of the first and second low-pass filters Receiving a frequency control signal for controlling the numerical control variable frequency oscillator so that the frequency and the phase of the output carrier signal of the numerical control variable frequency oscillator follow the carrier wave component included in the intermediate frequency signal. And a phase of the pseudo noise code output from the pseudo noise code generator based on the outputs of the first and second low pass filters. And a second control signal generation circuit for generating a control signal for controlling the code drive device so as to match the above.